TWI443543B - Method of simulating an esd circuit layout - Google Patents

Description

Simulation method for electrostatic discharge circuit layout

The present invention relates to electrostatic discharge (ESD), and more particularly to a simulation method for an electrostatic discharge circuit layout.

Electrostatic discharge (ESD) is detrimental to the semiconductor materials of integrated circuits (such as germanium and antimony oxide), causing permanent damage due to transient and transient currents or voltages. Therefore, the integrated circuit is usually equipped with an electrostatic discharge protection circuit; and must undergo various electrostatic discharge tests at the design and manufacturing stages to verify resistance and endurance to electrostatic discharge. The human-body model (HBM) is a commonly used electrostatic discharge test mode that simulates the human body's touch on integrated circuits; machine mode (MM) is another commonly used electrostatic discharge test mode, which simulates The machine's contact with the integrated circuit.

The shortcomings of electrostatic discharge circuits can be found to be better and more cost effective if they are designed and manufactured. However, most of the current testing mechanisms allow defective ESD circuits to pass circuit function tests without being able to identify defects.

Therefore, it is necessary to wait until the manufactured solid bulk circuit is burned by the electrostatic discharge test to truly find the defective electrostatic discharge circuit. At this time, it is necessary to discard the mask of the original integrated circuit, modify the circuit layout, prepare another mask to remanufacture the integrated circuit, and then Electrostatic discharge testing of newly manufactured integrated circuits. The above procedure must be repeated multiple times until the integrated circuit passes the electrostatic discharge test.

Therefore, there is a need to propose a novel method for simulating an ESD circuit layout efficiently, economically, and quickly.

In view of the above, one of the objects of the embodiments of the present invention is to provide a simulation method for the layout of an electrostatic discharge circuit, which can find the back-end layer of the defect before the circuit layout is taped out, thereby avoiding errors and being expensive. The manufacture of photomasks and integrated circuits.

In accordance with an embodiment of the present invention, a network netlist is provided that describes the connection relationship between electronic circuit components. The front end simulates the network connection table to model the circuit operation of the electronic circuit. Based on the results of the front end simulation, a circuit layout corresponding to one of the electronic circuits is generated that includes an electrostatic discharge circuit layout. Parasitic extraction is performed according to the resulting circuit layout. An electrostatic discharge waveform is provided to simulate the layout of the electrostatic discharge circuit; and based on the results of the electrostatic discharge waveform and the parasitic extraction, the back-end simulation of the electrostatic discharge circuit layout is performed.

11‧‧‧Network Connection Table

12‧‧‧ Front end simulation

13‧‧‧Layout

14‧‧‧ Parasitic extraction

15‧‧‧Backend simulation

16‧‧‧ Electrostatic discharge waveform

I/O‧‧‧output mat

VDD‧‧‧Power pad

VSS‧‧‧Grounding pad

The first figure is a flow chart of a simulation method of an electrostatic discharge (ESD) circuit layout of an embodiment of the present invention.

The second A diagram illustrates an electrostatic discharge circuit including an N-type diode and a P-type diode.

Figure 2B shows a schematic diagram of an integrated circuit and its electrostatic discharge path, the electrostatic discharge circuit The formation of the track is to couple one of the pads with an electrostatic discharge waveform and ground the other pad.

The third diagram illustrates a schematic diagram of the circuit layout on which the reported current segments are displayed.

The first figure is a flow chart of a simulation method of an electrostatic discharge (ESD) circuit layout of an embodiment of the present invention.

In step 11, a network connection table (netlist) is first prepared, which describes the connection relationship between the electronic circuit components. Next, in step 12, the network connection table is transferred to a circuit level circuit simulation tool, such as the HSIM provided by Synopsys, which models the circuit to simulate (or verify) circuit behavior. In this specification, the verification performed in step 12 is also referred to as pre-simulation.

Next, at step 13, the results of the front end simulation are used to create a circuit layout (including an electrostatic discharge circuit layout) that is depicted with a pattern shape representing various levels of circuit composition. The manufacturing levels of semiconductor devices are generally divided into two broad categories: front-end layers and back-end layers. The front layer (e.g., the formation of the well and P/N type regions) is related to the fabrication of the components, while the back layer (e.g., metal layers, vias, and contacts) are related to the connections of the components. According to observations, the defective electrostatic discharge circuit usually burns at the back layer, which is usually caused by an excessively narrow metal layer, or the number of contact holes and vias is insufficient or the position is not appropriate.

At step 14, parasitic extraction (also commonly referred to as RC extraction) is performed in accordance with the resulting circuit layout to obtain parasitic effects (eg, parasitic capacitance (C) and parasitic resistance (R)). In this way, an accurate analog circuit model can be generated, based on digital and The analogy field is tested accurately. The extracted parasitic values can be stored in the Detailed Standard Parasitic Format (DSPF) file. In addition, in the above simulation tools (such as HSIM), a layout versus Schematic (LVS) tool may be included to verify whether the circuit layout conforms to a netlist. The layout engineer must modify the circuit layout until the circuit layout is verified by the layout versus circuit (LVS).

Next, in step 15, according to the output of step 12 (ie, the verified network connection table), the output of step 14 (ie, the DSPF file), and the electrostatic discharge waveform provided in step 16, (can be used) Synopsys' HSIM tool) further simulates the ESD circuit layout (also known as post-simulation) to simulate an ESD circuit. In this embodiment, the back end simulation is performed specifically for the back layer (eg, metal layer, via, and contact holes). The electrostatic discharge waveform provided in step 16 may be a standard electrostatic discharge waveform used to generally verify an electrostatic discharge circuit.

The second A diagram illustrates an electrostatic discharge circuit including an N-type diode and a P-type diode. The figure also shows the I/O pad, power pad (VDD), and ground pad (VSS). When the voltage of the input and output pads is greater than VDD, the P-type diode is turned on by the forward bias, thereby protecting the internal circuit from damage. In a similar situation, when the voltage input to the pad is less than VSS, the N-type diode is turned on by the forward bias, thereby protecting the internal circuit from damage.

In this embodiment, any two pads of the circuit can be respectively coupled to the electrostatic discharge waveform and the ground, thereby forming an electrostatic discharge path, and performing electrostatic discharge simulation (ie, back-end simulation) to verify the reliability of the electrostatic discharge path. degree. Figure 2B shows a schematic diagram of the integrated circuit and its electrostatic discharge path. The electrostatic discharge path is formed by an electrostatic discharge waveform. One of the pads and the other pad are grounded. The pad of each electrostatic discharge path can be a power pad (eg, VDD), a ground pad (eg, VSS), or an input pad. In general, the ESD path can be one of the following: (1) power/ground pad to power/ground pad; (2) input pad to power/ground pad, and vice versa; (3) output pad to output Into the mat.

For each ESD path, the back-end simulated simulation tool reports the corresponding current flowing through each metal layer. In this embodiment, the reported current is compared to a nominal current for each metal layer of the circuit layout. Next, classification is performed according to the comparison result of the metal layers, and different colors are visually used to represent different grades. For example, when the reported conductive current of the metal layer is equal to or greater than the corresponding rated current, it is displayed in red; when the reported conductive current of the metal layer is much smaller than the corresponding rated current, it is displayed in green. The third diagram illustrates a schematic diagram of the circuit layout (shown in dashed box) on which the reported current segments are shown (as indicated by the solid boxes). In the drawings, the cross-hatched area indicates that the reported conductive current of the metal layer is equal to or greater than the corresponding rated current. When the circuit layout appears red (for example, the cross-hatched area in the drawing) metal layer, the layout engineer can modify the width of the metal layer according to the comparison result (for example, the ratio of the conductive current to the rated current), or change the via or The number or location of contact holes.

According to the present embodiment, the defect area of the ESD circuit layout can be detected before the layout data tape-out or the physical layout mask is manufactured, thereby greatly reducing unnecessary labor and cost. Furthermore, when finding a defective ESD circuit layout, the layout engineer can quantitatively modify the back layer based on the comparison result. In contrast to the traditional method, when the ESD circuit burns out, the layout engineer can only modify the ESD circuit layout according to his experience.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

11‧‧‧Network Connection Table

12‧‧‧ Front end simulation

13‧‧‧Layout

14‧‧‧ Parasitic extraction

15‧‧‧Backend simulation

16‧‧‧ Electrostatic discharge waveform

Claims (10)

A method for simulating an ESD circuit layout includes: providing a netlist that describes a connection relationship between components of an electronic circuit; and a front end simulating the network connection table for modeling the electronic Circuit operation of the circuit; generating a circuit layout corresponding to the electronic circuit according to the result of the front end simulation, the generated circuit layout comprising an electrostatic discharge circuit layout and a plurality of back-end layers for connecting individual components of the electronic circuit and The back layer layer performs back-end simulation; performs parasitic extraction according to the generated circuit layout; provides an electrostatic discharge waveform for simulating the electrostatic discharge circuit layout; and according to the electrostatic discharge waveform and the result of the parasitic extraction, The electrostatic discharge circuit layout performs a back end simulation; wherein the back end simulation step includes: coupling the electrostatic discharge waveform to one of the plurality of pads of the electronic circuit, and grounding the other pad to form an electrostatic discharge path; reporting the flow Corresponding current through the back layer; comparing the reported conductive current with a corresponding rated current; and reporting the back layer When the stream is equal to or larger than the rated current, the rear section highlights layer. The simulation method of the ESD circuit layout according to claim 1, wherein the network connection table is simulated by a circuit level simulation tool of a transistor level. The simulation method of the ESD circuit layout according to Item 1, wherein the back layer comprises at least one of the following: a metal layer, a via, and a contact hole. (contact). The simulation method of the electrostatic discharge circuit layout according to claim 1, wherein the parasitic extraction includes parasitic capacitance and parasitic resistance. The simulation method of the electrostatic discharge circuit layout according to claim 1, wherein the parasitic storage of the extraction is a detailed standard parasitic format (DSPF) file. The simulation method of the electrostatic discharge circuit layout according to claim 1, wherein in the parasitic extraction step, a layout-to-circuit (LVS) tool is used to verify whether the circuit layout is related to the network connection table. meets the. The simulation method of the electrostatic discharge circuit layout according to claim 1, wherein the pad of the electrostatic discharge path is a power pad, a ground pad or an input pad. The simulation method of the electrostatic discharge circuit layout according to claim 7, wherein the electrostatic discharge path is formed by the following two pads: (1) two power/ground pads; (2) the output pad and the Power/ground pad; (3) two of the output pads. The simulation method of the ESD circuit layout according to Item 1, wherein the back end simulation step further comprises: classifying according to the comparison result of the back layer; and visually using different colors to represent different levels. The back layer. The simulation method of the ESD circuit layout according to Item 1, wherein the back end simulation step further comprises: modifying the width, the number or the position of the back layer according to the comparison result.