TWI440165B - High voltage device and manufacturing method thereof - Google Patents

Description

High voltage component and method of manufacturing same

The present invention relates to a high voltage component and a method of manufacturing the same, and more particularly to a high voltage component for enhancing a breakdown protection voltage and a method of fabricating the same.

1A and 1B are respectively a cross-sectional view and a perspective view of a double diffused metal oxide semiconductor (DMOS) device of the prior art. As shown in FIGS. 1A and 1B, the P-type substrate 11 has a plurality of insulating regions. 12, to define the device region 100, the insulating region 12 is, for example, a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown; the P-type substrate 11 further includes N Type well area 14. A DMOS device is formed in the device region 100 and includes a gate 13, a drain 15, a source 16, a body region 17, and a body electrode 17a. Wherein, the drain 15 and the source 16 are masked by lithography or part or all of the gate 13 and the insulating region 12 to define regions, and respectively, the ion implantation technique is used to apply N-type impurities to Accelerate the form of ions into the defined area. Wherein, the drain 15 and the source 16 are respectively located below the two sides of the gate 13; the body region 17 and the body pole 17a are masked by lithography or part or all of the gate 13 and the insulating region 12 to define each The regions, and ion implantation techniques, respectively, implant P-type impurities into the defined regions in the form of accelerated ions. Further, in the DMOS device, a part of the gate 13 is located on the insulating region 12. The DMOS component is a high voltage component, that is, it is designed to supply a higher operating voltage, but when the DMOS component needs to be integrated on the same substrate as the generally lower operating voltage component, it is a component process with a lower operating voltage. The DMOS component and the low voltage component need to be fabricated with the same ion implantation parameters, so that the ion implantation parameters of the DMOS component are limited, thereby reducing the DMOS component collapse protection voltage and limiting the application range of the component. If the DMOS component collapse protection voltage is not sacrificed, the process steps must be added, and the DMOS components are separately fabricated with different ion implantation parameters, but this will increase the manufacturing cost to achieve the desired collapse protection voltage.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and provides a high-voltage component and a manufacturing method thereof, which can improve the breakdown protection voltage of the component operation, increase the application range of the component, and can be integrated in the process without increasing the process steps. Process of low voltage components.

It is an object of the present invention to provide a high voltage component and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a high voltage component formed in a first conductive type substrate having a second conductive type well region and an element region, wherein the component region is composed of at least one insulating region Defined in the well region of the substrate, the high voltage component includes: a field oxide region formed in the component region on the substrate; a gate formed in the component region on the surface of the substrate, and a portion of the gate is located in the field a second conductive type source and a second conductive type drain are respectively located on opposite sides of the gate in the element region, and viewed from a top view, the drain and the source are connected to the gate Separating from the field oxide region; and a second conductivity type first low doped region formed in the well region below the gate, and viewed from a top view, the first low doped region is in a range Within the gate, the second conductive type impurity concentration of the first low doped region is lower than that of the surrounding well region, and further, the depth of the first low doped region is extremely deeper than the source and the germanium .

In another aspect, the present invention also provides a method for manufacturing a high voltage component, comprising: providing a first conductive type substrate, and forming a second conductive type well region in the first conductive type substrate, wherein the substrate has an element region The component region is defined by the at least one insulating region in the second conductive type well region of the substrate; forming a field of oxidation in the device region on the substrate; forming a second conductive type first low doped region in the well Forming a gate in the element region on the surface of the substrate, and a portion of the gate is located on the field oxide region; and forming a second conductivity type source and a second conductivity type drain, respectively located in the element region In the upper side of the gate, and viewed from a top view, the drain and the source are separated from the field oxide region by the gate; wherein the first low doped region is located under the gate In the well region, and viewed from a top view, the first low doped region is within the gate, and the second conductive type impurity concentration of the first low doped region is lower than that of the surrounding well region. In addition, the depth of the first low doped region is extremely larger than the source and the drain .

In a preferred embodiment, the first lowly doped region is covered by a top view or adjacent to a boundary of the field oxide region, and is viewed from a cross-sectional view, the boundary being below the gate.

In another preferred embodiment, the high voltage component further includes a second conductive type second low doped region formed in the well region below the insulating region, and viewed from a top view, the second low doping The location of the region is on a side of the field oxide region relative to the first low doped region, or forms a ring structure with the first low doped region, and a portion of the second low doped region is relative to the first a field of the field oxide region of the low doped region, and a second conductivity type impurity concentration of the second low doped region is lower than a surrounding well region, and further, a depth of the second low doped region is compared to the source Extremely strong and extremely deep.

In another preferred embodiment, the first low doped region and the well region are formed by the same lithography process and ion implantation process steps.

In still another preferred embodiment, the high voltage component further includes: a first conductive type body region formed under the surface of the substrate in the component region, wherein the body region covers the second conductive type source a body, wherein the body region is adjacent to the gate; and a first conductivity type body electrode is formed under the surface of the substrate in the body region; wherein the high voltage component is a double diffusion metal oxide A double diffused metal oxide semiconductor (DMOS) device.

In still another preferred embodiment, the high voltage component further includes: a first conductive type base region formed under the surface of the substrate in the component region, wherein the base region and the gate are viewed from a top view Adjacent; and a first conductive type base formed under the surface of the substrate in the base region; wherein the high voltage component is a bipolar junction transistor (BJT) component, the source is The second conductive type emitter of the BJT element, and the drain is the second conductive type collector of the BJT element.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 2A-2B, there is shown a first embodiment of the present invention. This embodiment shows a schematic diagram of a method of fabricating the present invention for use in a DMOS device. In the substrate 11, an insulating region 12 is formed to define an element region 100, wherein the substrate 11 is, for example, P-type but not limited to being P-type (it may also be N-type in other embodiments); the insulating region 12 is, for example, an STI structure or The region shown in the figure oxidizes the LOCOS structure, and the substrate 11 includes a well region 14 of a N type (which may also be a P type in other embodiments) having a conductivity type different from that of the substrate 11. Further, as shown in FIG. 2A, in the well region 14, a first low doped region 18 having the same conductivity type as the well region 14 but having a lower impurity concentration than the surrounding well region 14 is formed. On the surface of the substrate 11, in the element region 100, a field oxide region 22 is formed on the surface of the substrate 11 by an oxidation technique, which is, for example, an STI structure or a region oxide LOCOS structure; and the field oxide region 22 can utilize, but is not limited to, an insulating region. 12 identical process steps are formed. Next, referring to FIG. 2B, in the element region 100, a gate 13, a drain 15, a source 16, a body region 17, and a body electrode 17a are formed; wherein the drain 15 and the source 16 are, for example, N-type but not Limited to N-type (P-type in other embodiments), respectively located on both sides of the gate 13 in the element region 100, and viewed from the top view (not shown), the drain 15 and the source 16 Separated by the gate 13 from the field oxide region 22; The body region 17 is, for example, P-type but is not limited to being P-type (it may be N-type in other embodiments). Furthermore, the depth of the first low doped region 18 is deeper than the source 16 and the drain 15 .

Unlike the prior art, in the present embodiment, the well region 14 includes a first low doped region 18, which is, for example, N-type but not limited to N-type (in other embodiments, it may also be P-type) . The advantages of this arrangement include: in the component specification, the collapse protection voltage of the DMOS component can be improved; in the process, the first low-doped region 18 can utilize the process and mask for forming the well region 14 in the ion implantation process. In the step, the first low-doped region 18 is covered by a photoresist or other mask to block accelerated ion implantation into the first low-doped region 18. In the subsequent high-temperature process step, after the impurity is diffused, the DMOS device is formed into an impurity. The first low doped region 18 having a lower concentration than the surrounding well region 14 is applied to the DMOS device without the need for an additional mask or process step, thereby reducing manufacturing costs.

Fig. 3 shows a second embodiment of the present invention, and Fig. 3 also shows a perspective view of the present invention applied to a DMOS device. Different from the first embodiment, the DMOS device of the embodiment further includes the same conductivity type as the first low-doped region 18 (N-type in this embodiment, and may be The second low doped region 19 of the P-type) is formed in the well region 14 below the insulating region 12 on the side of the drain 15 .

Figures 4 and 5 show two of the above views of the previous embodiment. As seen from the top view of FIG. 4, the position of the second low doped region 19a may be on the other side of the field oxide region 22 with respect to the first low doped region 18; or as shown in Fig. 5 of the above view, the second low The doped region 19b and the first low doped region 18 form a ring structure as shown, and a portion of the second low doped region 19b is located on the other side of the field oxide region 22 with respect to the first low doped region 18. And the impurity concentration of the second low doped region 19b is lower than that of the surrounding well region 14. In addition, in either form, the depth of the second low doped regions 19a and 19b is compared with the source 16 and the drain 15 Deep.

6A-6B shows a preferred range of the first low doped region 18, as shown in Figure 6A of the above view, the first low doped region 18 is preferably located in the gate 13 range (the gate 13 is indicated by a dashed line) See the perspective view of the embodiment of FIGS. 2B and 3). A preferred range of the first low doped region 18, as seen in section 6B of the cross-sectional view, envelops or abuts the left side boundary 22a of the field oxide region 22, as indicated by the dashed line in the figure, and is viewed from section 6B of the cross-sectional view. The left boundary 22a of the oxidation zone 22 is located below the gate 13. With the present invention, the electric field generated by the insulating region 12 during operation can be reduced to increase the component collapse protection voltage.

The 7A-7C diagram illustrates a method of forming the first low doped region 18. As shown in FIG. 7A, in the process of forming the well region 14, the first low doped region 18 is covered by the photoresist 14a or other mask to block the first low acceleration ion implantation as indicated by the dotted arrow. The doped region 18, in the subsequent high-temperature process step, after the impurities are diffused, causes the DMOS device to form the first low-doped region 18 having a lower impurity concentration than the surrounding well region 14 as shown in FIG.

Of course, the method of forming the first low-doped region 18 may be performed in addition to the step shown in FIG. 7A, and the additional step is as shown in FIG. 7C, and the region other than the first low-doped region 18 is photoresist or Other masks are obscured and, as indicated by the dashed arrows, implant a lower dose of accelerated ions into the first low doped region 18, or even implant an opposite conductivity type of impurity to adjust the first low doped region. The impurity concentration of 18 is lower than that of the surrounding well region 14. The concept of the present invention is not limited to only one method implementation.

Figure 8 is a cross-sectional view showing another embodiment of the present invention, illustrating the application of the present invention to a BJT device. Unlike the first embodiment, the BJT device has a base region 17b, a base 17c, an emitter 16a, and a collector 15a, and preferably couples the gate 13 to the emitter 16a.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography. The above and other equivalent variations are intended to be covered by the scope of the invention.

11. . . Substrate

12. . . Insulating area

13. . . Gate

14. . . Well area

14a. . . Photoresist

15. . . Bungee

15a. . . Collector

16. . . Source

16a. . . Emitter

17. . . Body area

17a. . . Body pole

17b. . . Base area

17c. . . Base

18. . . First low doped region

19,19a,19b. . . Second low doped region

twenty two. . . Field oxidation zone

22a. . . Left border

100. . . Component area

Figure 1A shows a cross-sectional view of a prior art DMOS device.

Figure 1B shows a perspective view of a prior art DMOS device.

Figures 2A and 2B show a first embodiment of the present invention.

Figure 3 shows a second embodiment of the invention.

Figures 4 and 5 show two of the above views of the second embodiment.

Figures 6A-6B show a preferred range of the first low doped region 18.

The 7A-7C diagram illustrates a method of forming the first low doped region 18.

Figure 8 shows another embodiment of the present invention.

11. . . Substrate

12. . . Insulating area

13. . . Gate

14. . . Well area

15. . . Bungee

16. . . Source

17. . . Body area

17a. . . Body pole

twenty two. . . Field oxidation zone

Claims (10)

A high voltage component is formed in a first conductive type substrate, the substrate has a second conductive type well region, and an element region, wherein the component region is defined by at least one insulating region in the well region of the substrate, The high voltage component comprises: an oxidation zone formed in the component region on the substrate; a gate formed in the component region on the surface of the substrate, and a portion of the gate is located on the field oxide region; the second conductivity type source And a second conductive type drain, respectively located on the two sides of the gate in the element region, and viewed from a top view, the drain and the source are separated from the field by the gate; a second conductive type first low doped region formed in the well region below the gate, and viewed from a top view, the first low doped region is within the gate, and the first low The second conductivity type impurity concentration of the doped region is lower than that of the surrounding well region, and further, the depth of the first low doped region is extremely deeper than the source and the germanium; and the second conductivity type is the second lowest a doped region formed in the well region below the insulating region, and viewed from a top view, the first The low doped region is located on the other side of the field oxide region relative to the first low doped region, or forms a ring structure with the first low doped region, and a portion of the second low doped region is opposite And the second conductive type impurity concentration of the second low doped region is lower than the surrounding well region, and the depth of the second low doped region is It is extremely deep compared to the source and the source. The high-voltage component of claim 1, wherein the first low-doped region is covered by a top view or adjacent to a boundary of the field oxide region, and the boundary is located at the gate Extremely below. The high-voltage component of claim 1, wherein the first low-doping The impurity zone and the well zone are formed by the same lithography process and ion implantation process steps. The high voltage component according to claim 1, further comprising: a first conductive type body region formed under the surface of the substrate in the component region, wherein the body region covers the second conductivity type a source, and viewed from a top view, the body region is adjacent to the gate; and a first conductive type body electrode is formed under the surface of the substrate in the body region; wherein the high voltage component is a double diffusion metal oxide Double diffused metal oxide semiconductor (DMOS) component. A high voltage component is formed in a first conductive type substrate, the substrate has a second conductive type well region, and an element region, wherein the component region is defined by at least one insulating region in the well region of the substrate, The high voltage component comprises: an oxidation zone formed in the component region on the substrate; a gate formed in the component region on the surface of the substrate, and a portion of the gate is located on the field oxide region; the second conductivity type source And a second conductive type drain, respectively located on the two sides of the gate in the element region, and viewed from a top view, the drain and the source are separated from the field by the gate; a second conductive type first low doped region formed in the well region below the gate, and viewed from a top view, the first low doped region is within the gate, and the first low The second conductivity type impurity concentration of the doped region is lower than that of the surrounding well region. Further, the depth of the first low doping region is extremely deeper than the source and the germanium; a first conductive type base region, Formed under the surface of the substrate in the component region, viewed from a top view, the base region and the gate And a first conductive type base formed under the surface of the substrate in the base region; wherein the high voltage component is a bipolar junction transistor (BJT) component, the source is used as the Second conductivity type of BJT component The emitter is the second conductivity type collector of the BJT element. A method for manufacturing a high voltage component, comprising: providing a first conductive type substrate, and forming a second conductive type well region in the first conductive type substrate, wherein the substrate has an element region defined by at least one insulating region Forming a field of oxidation in the element region on the substrate; forming a second conductivity type first low doped region in the well region; forming a gate on the substrate a surface region of the component, and a portion of the gate is located on the field oxide region; forming a second conductivity type source and a second conductivity type drain, respectively located on the sides of the gate in the component region, and Viewing, the drain and the source are separated from the field oxide region by the gate; and forming a second conductive type second low doped region in the well region below the insulating region, and Viewing, the second low doped region is located on the other side of the field oxide region relative to the first low doped region, or forms a ring structure with the first low doped region, and a portion of the first The second low doped region is on the other side of the field oxide region relative to the first low doped region, The second conductive type impurity concentration of the second low doped region is lower than that of the surrounding well region, and further, the depth of the second low doped region is extremely deeper than the source and the germanium; wherein the first low The doped region is located in the well region below the gate, and is viewed from a top view, the first low doped region is within the gate, and the second conductive type of the first low doped region The impurity concentration is lower than the surrounding well region, and further, the depth of the first lowly doped region is extremely deeper than the source and the germanium. The method of manufacturing a high-voltage component according to claim 6, wherein the first low-doped region is viewed from a top view, which covers or abuts a boundary of the field oxide region, and is viewed from a cross-sectional view. The boundary is below the gate. The method of manufacturing a high voltage component according to claim 6, wherein the step of forming the first low doped region and the well region is formed by the same lithography process and ion implantation process step. The method for manufacturing a high voltage component according to claim 6, further comprising: forming a first conductive type body region under the surface of the substrate in the component region, wherein the body region covers the second conductive a source, which is viewed from a top view, the body region is adjacent to the gate; and a first conductive body is formed under the surface of the substrate in the body region; wherein the high voltage component is a double diffusion metal oxide Double diffused metal oxide semiconductor (DMOS) component. A method for manufacturing a high voltage component, comprising: providing a first conductive type substrate, and forming a second conductive type well region in the first conductive type substrate, wherein the substrate has an element region defined by at least one insulating region Forming a field of oxidation in the element region on the substrate; forming a second conductivity type first low doped region in the well region; forming a gate on the substrate a surface region of the component, and a portion of the gate is located on the field oxide region; forming a second conductivity type source and a second conductivity type drain, respectively located on the sides of the gate in the component region, and Viewing, the drain and the source are separated from the field oxide region by the gate; wherein the first low doped region is located in the well region below the gate, and is viewed from a top view, The first low doped region is within the gate, and the second conductive type impurity concentration of the first low doped region is lower than the surrounding surrounding well region, and further, the depth of the first low doped region Relatively deeper than the source and the germanium; forming a first conductive type base region The lower region of the surface of the substrate member, and Viewed from the top view, the base region is adjacent to the gate; and a first conductive type base is formed under the substrate surface in the base region; wherein the high voltage component is a bipolar junction transistor ( A bipolar junction transistor (BJT) device, the source is a second conductivity type emitter of the BJT device, and the drain is used as a second conductivity type collector of the BJT device.