TWI336081B - System and method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates - Google Patents

Description

1336081 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to non-volatile memory technology. [Prior Art]

Semiconductor memory is increasingly used in a variety of electronic devices. For example, non-volatile semiconductor memory can be found in poetic cellular telephones, digital (four) computers, personal digital assistants, mobile computing devices, non-mobile computing devices, or other devices. Electrically erasable and programmable memory (eepr〇m) and flash memory are among the most popular non-volatile semiconductor memories. Both the EEPROM and the flash memory use a floating gate 35 that is positioned above and instasis of the channel region in the semiconductor substrate. The floating gate is positioned between the source region and the drain region. The _ control gate is disposed above the floating gate and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between its source and drain is controlled by the charge level on the floating gate. When programming an EEPROM or flash memory device (such as a NAND flash memory device), a stylized voltage is typically applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When an electron accumulates in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the storage element rises, thereby causing the storage element to be in a stylized state. More information about stylization can be found in the US Patent No. 121185.doc 1336081 M59, 397, and "Detect Over, "s〇urce side self Boosting Technique for N〇n_v〇Utile Mem〇ry" U.S. Patent No. 6,917,542, the disclosure of which is hereby incorporated by reference in its entirety in its entirety in its entirety in its entirety in its entirety in Some EEPROM and flash memory devices have a floating gate for storing two charge ranges and, therefore, can be programmed/erased between two states, such as an erased state and a stylized state. Store components. Such flash memory devices are sometimes referred to as binary flash memory devices. Multi-state flash memory devices are constructed by identifying a plurality of different allowed/validized threshold voltage ranges separated by respective forbidden ranges. Each of the different threshold voltage ranges corresponds to a predetermined value of a set of data bits encoded in the memory device. In current non-volatile memory devices (e. g., NAND flash memory devices), temperature changes can cause various problems with reading and writing data. The memory device is subject to varying temperatures based on its environment. For example, some existing s-resonance devices are considered to be at -40. Used between +85 0C. Devices in industrial, military, and even consumer applications can experience significant temperature changes. Temperature affects many transistor parameters, the most important of which is the Ss limit voltage. In particular, temperature changes can result in read errors and widen the threshold voltage distribution of different states of the non-volatile storage element. Currently, the temperature change is compensated for by changing the read/verify voltage applied to the selected word line in a manner that selects the temperature change of the threshold voltage of the storage element. This method can solve at most the problem of the average offset of the threshold voltage distribution of the storage element. For the sake of simplicity, it is assumed that the threshold voltages are all in the same data state. However, there is a need for an improved technique to further reduce (S:) 121185.doc 1J36081 J by the extension of the threshold voltage distribution for each state due to a change in the degree of coffee. SUMMARY OF THE INVENTION The present invention addresses the above and other problems by providing a system and method for operating a non-volatile memory in which a temperature compensated voltage is applied to a non-selective non-volatile storage element and/or selection Gate. The present invention achieves various benefits' including improved read and write performance. In an embodiment, the non-volatile storage is operated by:

A first voltage (e.g., a read or verify voltage) is applied to the -select word line to determine & the weighted state of the first non-volatile storage element associated with the selected word line. The first non-volatile storage element is disposed in a set of 70 pieces of non-volatile storage. For example, the __ voltage can be a read voltage that is used to read the stylized state of the first non-volatile storage element after its stylization. Alternatively, the dust may be a verification voltage that is used to verify that the first non-volatile storage element has reached the desired stylized state. For example, 'this verification voltage can be applied to a series of such stylized individual stylizations

Between the pulsations. Moreover, a temperature compensated power is applied to one or more non-selected word lines associated with the non-volatile storage element group upon application of the first voltage. In one method, the same temperature compensated voltage is applied to each of the selected word lines. In the other way, different temperature compensation voltages are applied to different non-selected word lines. In the re-method, " or two non-selected word lines directly adjacent to the selected word line receive - the amount of compensation or temperature compensation - the amount of reduction (relative to the application to other (four) word lines) The voltage of the temperature compensated voltage). The compensated voltage of '_121185.doc 1336081 can also be applied to the source and/or drain to select the gate, for example when the selected non-volatile storage element is in a NAND string. The first voltage can also be temperature compensated. In another embodiment, the non-volatile memory is operated by applying a first voltage to a selected word line to determine a first non-volatile storage element associated with the selected word line. Stylized state. The first non-volatile storage element is disposed in a set of non-volatile storage elements. Additionally, the first voltage is temperature compensated according to a relative position of the selected word line in a plurality of word lines associated with the set of non-volatile storage elements, eg, when the selected word line is included When the source of a plurality of word lines is closer to the drain, a larger temperature compensation value can be used. In another embodiment, the non-volatile memory is operated by applying a first voltage to a selected word line to determine a first non-volatile associated with the selected word line. A stylized state of the storage element, wherein the first non-volatile storage element is disposed in a set of non-volatile storage elements. • Applying a temperature compensated voltage to at least one first unselected word line associated with the set of non-volatile storage elements while applying the first voltage. In addition, while applying the first voltage, applying a voltage that is not temperature compensated or temperature compensated by a decrease (relative to a temperature compensated voltage applied to the first unselected word line) is applied to at least one A second unselected word line associated with the set of non-volatile storage elements. In one method, the at least one first unselected word line is not directly adjacent to the selected word line, and the at least one second unselected word line is directly adjacent to the selected word line. In a further embodiment, the non-volatile storage 121185.doc •9-OR .° is applied by a method of applying a first voltage to a selected word line to determine a associated word line. A stylized state of the first non-volatile storage element, wherein the first non-volatile storage element is disposed in a set of non-volatile storage elements. When the first non-volatile storage element is not directly adjacent to the selection gate, applying a first temperature-compensated voltage to the selection gate associated with the first non-volatile storage element while applying the first voltage pole. When the first volatile storage element is directly adjacent to the selection gate, an amount that is not temperature compensated or temperature compensated is reduced (with respect to the first temperature compensation) while the first pressure is applied The voltage of the voltage) is applied to the selection gate. The select gate and the first non-volatile storage element can be disposed in a NANE>, wherein the select gate is at one of the source or the NMOS side of the NAND string. Provides a method for operating non-volatile storage and non-volatile storage systems. The non-volatile charge system includes a set of non-(four) storage elements - and one or more circuits for operating the non-volatile storage element set as described herein. [Embodiment] The present invention provides a system and method for operating a non-volatile memory in a manner that improves read and write performance, and operates π sonar and 10,000 methods. The improved performance is achieved by applying a voltage of .-i, hematocrit compensation to the selection of non-volatile storage elements and/or selection of gates. The tedious reduction between the specific benefits of the state of the state is salty...the interference, the ^^ Λ ^ lattice, due to the use of the larger stylized step size =: and / or by compressing the state closer - The operating window that is reduced. 121185.doc

-10- < S 1336081 An example of a memory system suitable for use in constructing the present invention uses a NAND flash memory structure comprising a plurality of transistors arranged in series between two select gates. The series transistors and the select gates are referred to as a NAND string. Figure 1 is a top plan view showing a NAND string. Figure 2 is an equivalent circuit of the NAND string. The nand string illustrated in Figures 2 and 2 includes four transistors 100, 102, 1〇4, and 1〇6 connected in series and sandwiched between a first selection gate 120 and a second selection gate 122. Select gate 120 strobes the NAND string connections to bit line 126. Select gate 122 strobes the NAND string connection to source line 128. The selection gate 12 is controlled by applying a suitable voltage to the control gate 12 〇 Cg. The selection gate 122 is controlled by applying a suitable voltage to the control gate 122CG. Each of the transistors 1〇〇, 1〇2, 1〇4, and 1〇6 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate i〇〇FG. The transistor 1〇2 includes a control gate 102CG and a floating gate 102FG. The transistor 1〇4 includes a control gate 104CG and a floating gate i〇4FG. The transistor 1〇6 includes a control gate i〇6CG and a floating gate 106FG. The control gate i〇〇CG is connected to (or is) the word line WL3'. The control gate i〇2CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate i〇6CG is connected to the word line. WL0. In one embodiment, the transistors 1〇〇, 1〇2, 1〇4, and 1〇6 are all storage elements, also referred to as memory cells. In other embodiments, the storage element may comprise a plurality of transistors ' or may be different than that depicted in Figures 1 and 2. The selection gate 120 is connected to the selection line SGD. The selection gate 122 is connected to the selection line SGS. Figure 3 provides a cross-sectional view of the above NAND string. As illustrated in FIG. 3, the transistors in the N AND string are formed in the p-well region 140. Each transistor is packaged 121185.doc 1336081 includes a stacked gate structure consisting of control gates (100CG, 102CG, 104CG, and 106CG) and a floating gate (100FG, 102FG, 104FG, and 106FG). The control gates and floating gates are typically formed by depositing a polysilicon layer. The floating gates are formed on the surface of the P-well on top of an oxide film or other dielectric film. The control gate is located above the floating gate, and an intermediate polysilicon dielectric layer separates the control gate from the floating gate. Storage Element - The control gates of (100, 102, 1, and 106) form a word line. The N+ doped diffusion regions 13, 132, 134, 130, and 138 are shared between adjacent storage elements, whereby the storage elements are connected in series to each other to form a NAND string. The N+ doped regions form the source and drain of each of the storage elements. For example, the L'N+ doped region 13 is used as the drain of the transistor 122 and the transistor 1〇6. The source 'N+ doped region 132 is used as the drain of the transistor 1〇6 and the transistor 104/ The source 'N+ doping region 134 is used as the drain of the transistor 1〇4 and the source of the transistor 102. The N+ doping region 136 is used as the drain of the transistor 1〇2 and the source of the transistor ι〇〇. And the N+ doping region 138 is used as the source of the drain of the transistor 1 and the gate of the transistor. N+ doped region 126 is coupled to the bit line of the NAND string while doped region 128 is coupled to one of the plurality of NAND strings to share the source line. 'Main', although Figure 1_3 shows four storage elements in the NAND string, the use of four Thunderbolt 曰9 bodies is only an example. For the techniques described herein - NAND strings can have less than four storage elements or more than four storage elements. For example, some NAND strings will include 8, 16, 32, or 64 memory elements.士~ ^ The discussion of the text is not limited to any special ~ quantity of storage elements in a NAND string.疋 Each storage element can be stored in analogy or in digital form. When storing a bit of digital data, the possible threshold voltage range of the storage component is divided into two ranges 'Shaw two ranges are assigned to logical materials "1" and "0. In an example of a flash memory, the threshold voltage is negative after the erased storage element and is defined as a logical " and after the stylization operation, the threshold voltage is positive and defined as a logical "〇" When the voltage limit is negative and a read is attempted by applying a stagnation to the control gate, the storage element will turn on a to indicate that the logic 1 is being stored. When the threshold voltage is positive and the stagnation is applied to the control gate When a read operation is attempted, the storage element will not be turned on, and the indication stores the logical volume. A storage element can also store multiple states, thereby storing a plurality of digital data bits. In the case of storing multiple data states, The voltage-limited window is divided into multiple states. For example, if four states are used, four threshold voltage ranges will be assigned to the data values "11", "10", "01" and, 〇〇&quot ; In an example of a NAND-type memory, 'the threshold voltage is negative after the erase operation and is defined as "11." Use positive thresholds for states "10", 01", and "〇〇 Voltage. In some embodiments, a Gray code assignment scheme is used to assign a data value (eg, a logic state) to a threshold range such that if a threshold voltage of a floating gate is erroneously offset to its neighbor The physical state affects only one bit. The specific relationship between the data stored in the storage element and the threshold voltage range of the storage element depends on the data encoding scheme used by the storage element. For example, US Patent No. U.S. Patent Application Serial No. 1/461,244, filed on Jun. The schemes are both incorporated herein by reference in the form of 121185.doc 13 in full text, and the nand-type flash memory is provided in the next US patent/patent n case, and its operation is related (4), all such US patents/ The details of the patent application are hereby incorporated by reference: U.S. Patent No. 5,57,31, 5, US Patent No. 5,774,397; US Patent No. 6, 〇46,935; U.S. Patent No. 5,38M22 U.S. Patent No. M56,528 and U.S. Patent No. 6,522. Other types of non-volatile memory can be used in the present invention in addition to flash memory. Another type of flash EEPR〇M system The storage element utilizes a non-conductive dielectric material in place of the conductive floating gate to store the charge in a non-volatile manner. Such a storage element is described in an article by True et al. Nitride-Oxide eepr〇m Device)" (IEEE Ε1_〇η Device L_rs, edl_8, No. 3, March 1987, pp. 93-95). One by yttrium oxide, yttrium oxide and oxidation The three layers of dielectric formed by Shi Xi ('0N0") are sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the channel of the storage element. The storage element is channeled by an electron self-storing element Stylized by injection into the nitride, where the electrons are trapped Stored in a finite area. The stored charge then changes the threshold voltage of a portion of the channel of the storage element in a detectable manner. The storage element is erased by injecting a thermal cavity into the nitride. See by Nozaki et al. "a l_Mb EEPROM with MONOS Memory Cell for Semiconductor Disk

Application" (IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501), which describes a split gate structure having 121185.doc 1336081 to a similar storage element, one of which The heteropolylithic elliptical pole extends over a portion of the channel of the storage element to form a separate-selective transistor. Both of the above articles are incorporated herein by reference in their entirety. in

The stylized technique mentioned in Williams Brown and JGe E Brewer, edited by N.〇latile Semiconductor Memory Technology- (IEEE Press, 1998) 1.2, is also described in the section as applicable to Charge trapping device, the article is incorporated by reference herein. This symbol φ. August can also use the storage components described in this paragraph. Therefore, the techniques described herein are also applicable to the coupling between dielectric regions of different storage elements. Another method for storing two bits in each storage element has been described by Eitan et al. "NR0M: a N〇vel L〇caHzed Trapping, 2_ • Bit Nonvolatile Memory Cell)» (IEEE Electron Device - Letters), Volume 21, No. 11, 2 ji ji, pp. 543·545). A dielectric layer extends across the channel between the source diffusion region and the drain diffusion region. The charge of one data bit is localized in the dielectric layer φ adjacent to the drain, and the charge of the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading the binary states of the charge storage regions that are spatially separated within the dielectric. The storage elements described in this paragraph can also be used in the present invention. Figure 4 illustrates an example of an example of their NAND storage element array as shown in Figure _3. Along each row, a bit line 206 is coupled to the NMOS terminal 126 of the NAND string 150. Along each column of the NAND string, a source line 204 can connect all of the source terminals 128 of the source select gates of the NAND strings. An example of the operation of a uniform portion of Na can be found in U.S. Patent Nos. 5,570,315, 5,774,397, and 121,185, doc, 15-1336081, M46,935.歹 歹 J and its memory system is divided into large (four) deposits (four) flash bribe 0 Μ system for the 'block is the erase unit' is also the block: ::: dry: the minimum number of vents The health component block is usually slashed to the right page. The page is a stylized unit. The first page is divided into a plurality of segments, and the segments may contain a minimum number of storage elements as a basic process. Store one or more data pages in the - column health card... page to store - one or more ^ sectors. One sector includes user data and overhead data. The overhead data usually includes an error correction code (talking) calculated from the user data of the sector. The controller (described below) calculates the ECC when the data is being programmed into the array and also checks the ECC while reading data from the array. Or 'store Ecc and/or other overhead data on a different page than the user data to which it belongs. - The user data sector is typically 512 bytes, which is equivalent to the size of the sector-sector in the disk drive. The overhead data is usually _additional ι (four) bytes. A large number of pages form a block, for example from 8 pages (for example) to as many as 32, 64, 128 or more pages. In some embodiments, a column of NAND strings includes one block. In one embodiment, the ρ·well is raised to an erase voltage (eg, 20 volts) for a sufficient period of time while the source line and the bit line are floating, and the word line of a selected block is grounded. To erase the memory storage element. Since the capacitive coupling non-selected word line, bit line, select line and c source are also raised to

I21l85.doc -16- S 1336081 Erasing voltage - a small part. Thus, a strong. electric field is applied to the channel oxidation of the selected storage element (4), and is typically by FQwier_N. When the Qin^ channelization mechanism transmits the electrons of the floating gate to the substrate side, the data of the selected storage element is erased. When the electrons are transferred from the floating gate to the p-well region, a storage element is selected to erase the entire (four) array, the individual dock, or another unit of storage elements.

Figure 5 illustrates a memory device 296 having read/write circuits for reading and programming one of the pages of a storage element in parallel, in accordance with one embodiment of the present invention. Memory device 296 can include one or more memory dies 298. The memory die 298 includes a two-dimensional array of storage elements 3, a control circuit 310, and a read/write circuit 365. In some embodiments, the array of storage elements can be three dimensional. The memory array 3 can be addressed by the word line by the column decoder 330 and by the bit line by a row of decoders 36A. The read/write circuit 365 includes a plurality of sensing blocks 4 and allows one of the pages of the memory to be read or programmed in parallel. Typically, a controller 35 is included in the same memory device 296 (e.g., a removable memory card) in the form of one or more memory die 298. Commands and data are transferred between the host and controller 350 via line 32 and between the controller and one or more memory dies 298 via line 318. Control circuit 310 cooperates with read/write circuit 365 to perform memory operations on memory array 300. The control circuit 310 includes a state machine 312, an on-chip address decoder 314, a temperature compensation control 315, and a power control module 316. Temperature compensation control 315 will be further elaborated below in particular in conjunction with Figure 4. State machine 312 provides wafer level control of memory operations. Wafer 121l85.doc • 17· 1336081 The upper address decoder 3 14 provides an address interface between the address used by the host or memory controller and the hardware address used by decoders 330 and 360. Power control module 3 16 controls the power and voltage supplied to the word lines and bit lines during memory operation. In some embodiments, certain components of Figure 5 can be combined. In a different design, one or more of the groups (individually or in combination) of Figure 5 other than the array of storage elements 3A can be considered a management circuit. For example, one or more management circuits may include control circuit 310, state machine 312, decoder 314/360, power control 316, sensing block 4, read/write circuit, and control 1 § 350 Any one of the specialties or a combination thereof. Figure ό illustrates another arrangement of the memory device 296 shown in Figure 5. The access of each of the peripheral circuits to the memory array 3 is implemented in a symmetrical form on the opposite side of the array, thereby halving the density of the access lines and circuits on each side. Therefore, the column decoder is split into column decoders 33A and 33A, and the row decoder is split into row decoders 360A and 360A. Similarly, the read/write circuit is split into a read/write circuit 365A connected from the bottom of the array to the bit line and a read/write circuit 365A connected from the top of the array 300 to the bit line. In this way, the density of the read/write modules is substantially halved. The apparatus of Figure 6 can also include a controller as described above with respect to the apparatus of Figure 5. Figure 7 is a block diagram of a different sensing block 400. The sensing block is partitioned into a core portion called a sensing module 380 and a common portion 39A. In one embodiment, each bit line will have a single sensing module 38 and a plurality of sensing modules 380 will have a common portion 390. In an instance, a sense

121185.doc • 18 · (S 1336081 The test block will include a shared portion 390 and 8 sensing modules 380. Each of the sensing modules in a group is associated with a data bus 3 72 Sharing part of the communication. For other details, please refer to the application on December 29, 2004, and the name is "Non-Volatile Memory & Method with Shared

U.S. Patent Application Serial No. 1/026,536, the disclosure of which is incorporated herein by reference.

Sensing module 380 includes a sensing circuit 370 that determines whether the conductive current in a connected bit line is above or below a predetermined threshold level. Sensing module 380 also includes a bit line latch 382 for setting a voltage state on the connected bit 7L. For example, latching in a predetermined state in bit line latch 382 will cause the connected bit line to be pulled to a specified stylized inhibit state (e.g., Vdd).

The shared portion 390 includes a processor 392, a set of data latches, and an i7 interface 396 coupled between the data latch 394 and the data bus 32. The processor 392 performs the calculation. One of its functions is to verify the data stored in the sensed storage element and store the determined data in the data latch H group. The data latch 394 group is used to store the processor during the read operation. 392. The data bit is also used to store the data bit input from the data bus 32 during the process. The input poor bit indicates the data to be programmed into the memory. The /0 interface 396 provides an interface between the data latch 394 and the f-bus 32 (). In the "or sensing period, the operation is under the control of the state machine 312", the state machine control will have different control gates. Pole (4) Supply Addressed 121185.doc -19· , :S ) 1336081 Storage Element 》 When the sensing module 380 steps through various predetermined control gate voltages corresponding to various memory states supported by the memory , which can trip under one of these voltages and Stream 372 provides an output self-sensing module 38A to processor M2. At this time, the processor 392 determines the result memory state by taking into account the trip event of the sense module and the information about the control gate voltage applied by the state line 393 from the state machine. It will then calculate one of the binary states of the memory state and store the result in data latch 394. In another embodiment of the core portion, the 1-wire latch 382 has a dual function, that is, a latch for latching the output of the sensing module can also function as a bit as described above. Line latch. It is anticipated that certain embodiments will include multiple processors 392. In the embodiment, the parent treatment benefit 392 will include an output line (which is not shown in the figure) so that each of the rounds is connected by " or •. In some embodiments, the output lines are inverted before connecting to the "wire" of the connected line. = Build a stylization process during the stylization verification process. The state machine that receives the connection " or, can determine: when the stylized bit reaches the desired level. For example, when it reaches the desired level, the bit-logic = Capital: "Connected" or "quote" (or reverse data... when all bitization process. Since each - processor is 2 state machine known to terminate the program state machine needs to be connected to the "four" sense 8 Mice, so the device 392 adds logic to read the L, or to process the result of the ', the bit line to make the state machine only 121185.doc

• 20-S 1336081 Hanging, 'wired•• or " line for one reading. Similarly, by correctly selecting the logical level 'global state', the state can detect when the first bit changes its state and change the algorithm accordingly. During stylization or verification, the data to be stylized is stored in the data latch 394 from the data bus 320. Under state machine control, the stylization operation involves applying a series of programmed voltage ripples to the control poles of the addressed storage element. Readback (verification) is performed after each program pulsation to determine if the storage element has been programmed into the desired memory state. The processor 392 monitors the memory state read back relative to the desired memory state. When the two match, the processor 222 sets the bit line latch 214 to pull the bit line to the _specified stabilizing state. This prevents the storage elements coupled to the bit line from further stylizing, even when stylized pulsations appear on their control gates. In other embodiments, the processor initially loads bit line latch 382 and the sense circuit sets the latch to a disable value during the verify process. The data latch stack 394 includes a data latch stack corresponding to the sense module. In one embodiment, each sensing module 380 has three data latches. In some embodiments, but not required, the data latch is implemented as a shift register to convert the parallel data stored therein into serial data of the data bus 320 and vice versa. In the preferred embodiment, all of the data latches corresponding to the read/write blocks of the m storage elements can be linked together to form a shift register for input or output by serial transfer. A data block. Specifically, r reads/write blocks are used to have each of the data latch groups sequentially in the data 121185.doc -21 -

:S 1336081 Moves in or out of the data bus as if it were part of a shift register for the entire read/write block.

Additional information regarding the structure and/or operation of various embodiments of the non-volatile memory device can be found in the following patents: (1) U.S. Patent Application Serial No. 2004/0057287, issued March 25, 2004, "Non -Volatile Memory And Method With Reduced Source Line Bias Errors; (2) US Published Patent Application No. 2004/0109357, published on Jun. 10, 2004, "Non-Volatile Memory And Method with Improved Sensing"; (3) 2004 U.S. Patent Application Serial No. 11/015,199, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire content The US patent application No. 11/099, 133, filed by the Japanese Patent Application No. 11/099, 133, the inventor is Jian Chen; and (5) the application filed on December 28, 2005 U.S. Patent Application Serial No. 11/321,953, entitled "Reference Sense Amplifier For Non-Volatile Memory", invented by Siu Lung Chan and Raul-Adrian Cernea. All of the five patent documents just listed are incorporated herein by reference in their entirety. NAND flash EEPROM. The data stored in each block can be erased simultaneously. In one embodiment, the block is the smallest unit of the erased storage element at the same time. In each block, there are 8,512 in this example. Corresponding to the bit line BL0, 121185.doc -22- 1336081 LM11. In an embodiment called all bit line (abl) architecture, all bits of a block can be selected simultaneously during read and program operations. A line can simultaneously program a storage element along a common word line and connected to any bit line. Figure 8 shows four storage elements connected in series to form a excitation string. Although the figure shows each N-string Included in the four storage elements, but can also use more than: less than four storage elements (for example, 16, 32, 64 or other) one terminal of the NAND string by a drain Select the gate (which is connected to the selected gate drain line S GD) is connected to a corresponding bit line, and the other terminal is connected to the c source by a source-selective gate connected to the selected inter-source line S G S . • In another embodiment of the no-parity architecture, as shown in Figure 9, the bit lines are divided into even bit lines and odd bit lines. Figure 9 illustrates an example of organizing a memory array into blocks of an even memory structure. In an odd-numbered/even-numbered twisted-line architecture, the memory elements are connected in parallel along a common word line to the odd-numbered lines, and at another time along a common word line and connected to even-numbered bits. Line storage component. The data can be programmed into different blocks and the data can be read simultaneously from different blocks. In each block, in this example, there are 8,512 rows divided into even rows and odd rows. The bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo). In this example, four storage elements are shown connected in series to form a nand string. Although the figure shows that four storage elements are included in each NAND_, more or less than four storage elements can be used. During the construction of one of the item fetching and stylization operations, select 4,256 121185.doc •23· 1336081 storage conditions. The selected storage elements have the same word line and a 7G line of the same type (e.g., an even bit line or an odd bit line). Therefore, 532 data bytes can be explicitly fetched or programmed (which form a logical page), and a memory block can store at least 8 logical pages (four word lines, each with odd logical pages and even numbers) The logical page stores 70 pieces for multi-state. When each storage element stores two data bits, wherein each of the two bits is stored in a different page, one block stores 16 logical pages. Blocks and pages of other sizes. For ABL or parity architecture 'storage elements can be erased by raising the p_ well to an erase voltage (eg, 20 volts) and grounding the word line of a select block. The pole line and the bit line float. The wiper can be applied to the entire memory array, a separate block: or another element of the memory component in which the memory is loaded: & ° The floating gate of the electronic self-storing component is transferred to ρ • Well area to make the VTH of the storage element negative. In the read and verify operation, select the gate (SGD and SGS) to connect to a voltage ranging from 2.5 volts to 4.5 volts and non-selected words Line (eg when WL2 is selected) When it is WL0, purchase and milk 3) rise to a read pass voltage (usually - within the range of 45 volts to 6 volts) to make the transistor operate as a transfer gate. Select word line WL2 is connected to "turn", which is specified for each read and verify operation to determine whether the VTH of the associated 7L piece is above or below this level. For example, one for two bits In the read operation of the quasi-storage element, the selected word line can be grounded 'to ❹iVTd is higher than 〇V. In the verification operation for the two quasi-storage elements, the selected word line WL2 can be connected to (for example) 08 volts, I21185.doc

-24· C S 1336081 The fox has reached at least 0.8 volts. Miscellaneous and Ρ well is in the dormant. The = bit line (assumed to be an even bit line (7) (4)) is precharged to a level of (for example, 5) 〇·7 volts. If % is higher than the read or verify bit on the word line, the criteria associated with the primary storage element are maintained at a high level due to the non-conductive storage element. On the other hand, if the TH is lower than the 4 or verify level, the potential level of the associated bit line will be reduced by the discharge of the bit line by the conductive storage element - for example, less than 〇 $

Low level of volts. Therefore, the state of the storage element is detected by a voltage comparison sense amplifier connected to the bit line. The above-described erasing, reading, and inspection operations are performed in accordance with the techniques of the prior art, and thus many of the details explained can be changed by those skilled in the art. Other erasure, reading and verification techniques known to the art can be made. Figure Η illustrates an exemplary threshold (four) distribution of the storage element (4) when each storage element stores two data bits. The -th-threshold voltage distribution 经 of the erased storage element is provided. The three threshold voltage distributions of the programmed storage elements, BACe, in one embodiment, the threshold voltage in the distribution is negative and the threshold voltage in the A, BAC distribution is positive. Each of the five (5) Pro 16 voltages corresponds to a predetermined value of the data bit at that location. The specific relationship between the data stylized into the storage element and the threshold voltage level of the storage element is the same as the code scheme used for the storage element. t: 'US Patent Nos. 6,222,762 and 2〇〇4 U.S. Patent Application Publication No. 2/, No. 255, filed on Jan. 16, the disclosure of which is incorporated herein by reference. The manner of full reference is incorporated herein. In one embodiment, a Gray code assignment scheme is used to assign a data value to the threshold voltage range so that if the threshold voltage of the floating gate is erroneously shifted to its neighboring physical state, only one bit is affected. "An instance assigns a threshold voltage range 状态 (state £) "11", assigns a threshold voltage range Α (status Α) "1〇", assigns a threshold voltage range B (state B)" 〇〇”, and assign 〇1 to the threshold voltage range c (state c). However, in other embodiments, the Gray code is not used. Although four states are shown, the invention is also applicable to other polymorphic structures, including those that include more or less than four states. Three read reference voltages Vra, Vrb, and Vrc are provided to read data from the storage element. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb, and Vrc, the system can determine what state the storage element is in. In addition, three verification reference voltages Vva, Vvb, and Vvc are also provided. When the storage elements are programmed to state A, the system will test whether their storage elements have a threshold voltage greater than Vva or equal to vva. When the storage unit is programmed to state B, the system will test whether the storage elements have a threshold voltage greater than or equal to Vvb. When the storage element is programmed to state C, the system will test the storage element to be a limited power house with greater than or equal to Vvc. The embodiment is referred to as a full sequence stylized embodiment towel, and the storage element can be directly programmed from the erase state E to the stylized state a, 8 or 匚. Niu illusion and α can first erase a group of staging storage elements so that all storage elements in the group are in an erased state, and then, will make 121185.doc -26· 1336081 with a series of graphs The stylized pulsation depicted by the control gate voltage sequence of 13 directly programs the storage element into state A, B or C. When some of the storage elements are being programmed from state E to state A, the other storage elements are programmed from state E to state B and/or from state E to state C. When staging from state E to state C on WLn, the parasitic coupling amount coupled to the adjacent floating gate below WLn-1 can be maximized, and the self-state E is programmed to state A or self-state E. The amount of charge on the floating gate below WLn varies the most as compared to the voltage change when stylized to state B. When the state e is programmed to state B, the amount of coupling coupled to the adjacent floating gate is reduced but still very good. When the state E is programmed to the state A, the light combination is further reduced. Therefore, the amount of correction required to subsequently read each state of WLn-丨 will vary depending on the state of the adjacent storage elements on WLn. Figure 11 illustrates an example of a two-pass technique for a stylized multi-state storage element that stores data for two different pages (the next page and an upper page). The four states shown are: state e (ii) state A (1〇), state B (00), state C (〇l). For state E, two pages are stored white 1 » for state A The next page stores a "〇,, and the previous page stores a "1". For state B, both pages store "〇". For state C, the next page stores "1" and the upper page is stored in ";n". 1 1 Babe storage 0. Note that although each of these states is assigned a phase; in the ~ will be 70 patterns, but can also assign a different bitmap in one:: program In the middle of the process, according to the bit to be programmed into the next logical page, there is no limit to the thunder of the storage component, and the voltage level is limited. If the bit is a series, "1" Then, the power limit will not change because it is in the appropriate state of I21I85.doc -27-1336081 due to previous erasure. However, if the bit to be programmed is a logic ' Then the threshold level of the storage element is increased to become the state A' as indicated by the arrow 11〇〇. This terminates the first pass stylization. In a second pass stylization, 'set the threshold voltage level of the storage element according to bit 70 in the normalized upper logical page. If the upper logical page bit wants to store a logical "1" Stylized, this is due to the fact that the store is in the state E or A (the two φ. both carry a page bit "1") If the upper logical page bit is to be a logical "0", then the threshold voltage offset. If the first pass keeps the storage element in the erased state, then in the second phase, The storage element is stylized such that the threshold voltage is increased to be in state c, as indicated by arrow 1120. If the storage element is programmed as a result of the first pass, the piece has been programmed into state A, then The storage element is further programmed in the second pass to increase the threshold voltage to be in state 8, as depicted by arrow 1110. The result of the second pass is to program the storage element into a designated To store one of the pages on the logic "0" The state of the data of the page is changed. In both of Figures 10 and 11, the amount of coupling of the floating gates coupled to adjacent word lines depends on the final state. In one embodiment, if writing is sufficient to fill an entire Information on the page, • Material settings—the system to implement a full sequence of writers. If there is not enough data to write to the entire page, then the stylization process can program the page with the received data. When receiving subsequent data, The system then stylizes the page. In the re-implementation, the system can begin writing in the stylized page mode and if it subsequently receives all of the storage elements sufficient to fill a word line, 12I185.doc -28· 1336081 or most of the data 'is converted to full sequence stylized mode. Further details of this embodiment are disclosed in the inventor Sergy A. Gorobets and Yan Li, filed on December 14, 2004, "Pipe lined Programming of Non-Volatile Memories Using Early Data" 11/013, 125 In U.S. Patent Application, the entire disclosure of which is incorporated herein by reference.

12A-C disclose another method for staging non-volatile for any particular storage element that reduces floating by writing to a particular storage element associated with a particular page after writing an adjacent storage element for a previous page. The coupling effect of the gate to the floating gate. In an exemplary embodiment, the non-volatile storage element uses four data states to store two data bits for each storage π piece. For example, assume that state E is the erased state and states A, Β, and C are stylized. Status Ε Save Data u ^ Status A Stores Data 01. State B stores data 1〇. Status 〇 Save data 00. This is an example of a non-Gray code, since both bits are between adjacent states A and B. Other codes for data status to physical data status can also be used. Each storage element stores two data pages. For the purposes of this reference, these data pages are referred to as the upper page and the lower page; however, other markings may be assigned thereto. For state A, the upper page stores the bit and the next page stores the bit! . For state B, the upper page stores the bit] and the next page stores the bit 0. For state C, both pages store the bit data. This stylized process is a two-step process. In the first step, the page is compressed. If the next page is to remain in the data i, the storage element: the state remains in the state Εβ. If the data is to be programmed to 0, the storage element 121185.doc

The threshold voltage of -29* 1336081 is increased to program the storage element to state B. Thus, Figure 12A shows the stylization of the storage element from state E to state B. State B is an intermediate state B, so 'the verification point is shown as Vvb, Vvb, lower than Vvb. In one embodiment, after a storage element is programmed from state E to state B, its neighboring storage elements (WLn+1) in the NAND string will be programmed with respect to its lower page. For example, see Figure 2 again, in stylized

After storing the page below element 106, the page below the program storage element 1〇4 will be programmed. After the stylized storage element 1〇4, if the storage element ι4 has a threshold voltage from state E to state B, the coupling effect of the floating gate to the floating gate will rise to the storage element 106. Apparent threshold voltage. This will have the effect of widening the threshold voltage distribution of state B to the threshold voltage distribution depicted by the threshold voltage distribution 1250 of Figure 12B. When the page is stylized, the apparent widening of the threshold voltage distribution will be corrected.

Figure 12 (: shows the process of stylizing the page. If the storage element is in the erased state E and the upper page remains in the 丄' then the storage element will remain in shape (4). If the storage element is in state E, and on it If the page data is to be programmed to 0', the threshold voltage of the storage element will be raised so that the storage unit is in state A. The right storage element is in the middle threshold voltage distribution, and the upper page information is desired. Keeping at 1, the memory component will be (four) to the most 'shape, i B. The right storage element is in the middle threshold voltage extension 1250' and the upper page data is to be changed to data 0, then the storage element is睦 睦 么 么 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , This is 121185.doc •30· 1336081 because the page stylization on the adjacent storage element only affects the apparent threshold voltage of a given storage element. An example of an alternative status code is when the page data system 1 is Move from distribution 1250 to state c, and when the previous page data is Time shifts to state B. Although circle 12A-C provides an example of four data states and two data pages, the concept taught by AC in Fig. 12 can also be applied to have more or less than four states and different Other embodiments of the two pages. Figure 13 shows a voltage waveform 1300 comprising a series of stylized pulses 131, 132, 133, 1340, 1350, ... applied to a word line selected for programming. In one embodiment, the programmed pulsations have a voltage Vpgm that begins at 12 volts and is incremented by, for example, 0.5 volts for each successive stylized pulsation until a maximum of 2 volts is reached. The programmed pulsations are between the verification pulsation groups 1312, 1322, 1332, 1342, 1352, .... In some embodiments, each data can be programmed to have a verification pulse. In other embodiments There may be more or less verification pulsations. The verification pulsations in each group may have amplitudes such as Vva, Vvb, and Vvc (Fig. 1A). In one embodiment, the data is along a common word line. Stylized to a storage component. Thus, one of the word lines is selected for programming prior to applying the program pulsations. The word line will be referred to as a selected word line. The remaining word lines in a block are referred to as unselected word lines. The line may have one & two adjacent word lines. If the selected word line has two adjacent word lines, the adjacent word lines on the drain side are referred to as the drain side adjacent word lines and the adjacent word lines on the source side As the source Z is adjacent to the word line. For example, if the WL2 of Figure 2 selects the word line, then the heart is 121185.doc

-31- :S 1336081 is the source side adjacent word line and the WL3 system is on the drain side adjacent to the word line. Each of the storage element blocks includes a set of bit lines forming a row and a set of word lines forming a column. . In one embodiment, the bit line is divided into odd bit lines and even bit lines. Simultaneously staging a storage element along a common word line and connected to an odd bit line' while staging a storage element along a common word line and connected to an even bit line at another time (, odd/even stylized &quot ;). In another embodiment, the storage elements ("all bits are threaded") are threaded along a word for all bit lines in the block. In other embodiments, the bit lines or blocks may be decomposed into other groups (e.g., left and right groups, more than two groups, etc.). Figure 14 illustrates a threshold voltage as a function of temperature and word line position. Line 14 10 represents the relationship of temperature coefficient to word line position. Line 142 〇 represents the ratio of the threshold voltage change to the temperature change (Δντ/<^) versus the word line position, where vread is the temperature compensation for the voltage applied to the unselected word line. In this case, the 'temperature dependency magnitude decreases' although the word line position dependence decreases, but the word line position dependency dependence still exists. Line 1430 represents the relationship of (Δντ/c) to the position of the sub-wire where Vread is the temperature compensation for the voltage applied to the unselected word line and Vcgr is the temperature compensation for the voltage applied to the selected U-line. In this case, the magnitude of the temperature dependence is further reduced relative to line 142' and the word line position dependence still exists. Line 144 〇 represents the relationship of (ΔvT/°c) to the position of the word line, where Vread is temperature compensated for the voltage applied to the non-selected sub-line and is applied to the selected word due to further word line position dependence Vcgr ' The voltage of the line is implemented as Vcgri temperature compensation. In this case, the 121185.doc •32-[:S ) word line position dependency word line is substantially removed relative to the line 143〇. The word line dependence can also be applied to the non-selection by Vread: while the 6th voltage of the non-volatile storage element is observed to decrease with temperature. The voltage change with respect to temperature change can be expressed by a temperature coefficient (8), which is usually about . The temperature coefficient is dependent on various features of the stealth device, such as doping, layout, and the like. In addition, it is expected that the temperature coefficient will increase in magnitude as the memory size decreases. The temperature coefficient identifies the ratio of voltage or current change to temperature change. For example, for an operating range of -40 C to +85 C The threshold voltage can vary by approximately (85_(·40))χ(·2)=250 mV. Therefore, one or more can be improved by reading or verifying the voltage applied to a selected sub-line according to the temperature bias. The read or verify operation accuracy of the selected storage element associated with the selected word line. Further, when temperature compensation dependent on the word line is not used, the temperature coefficient may vary depending on the word line position, such as line 141 For example, assuming that there are 32 word lines in a block, line 1410 can have a value of about -1.9 mVrc at WL〇 (source side word line) and at WL31 (bungee side word line) Has a value of approximately -2 _ 1 mV/C. Therefore, in a possible design, the temperature coefficient varies across the word line to 〇, 2 mV. Experimental data obtained from a 70 nm ABL architecture wafer is based on Approximately 15% of the average page temperature coefficient of the word line address, where WL3 1 (which The junction resistor is completely on its source side. It suffers more damage due to temperature-induced series resistance changes on its source side, and thus experiences a series resistance change (but only at its drain side). , resulting in additional body effects. Various techniques are known for providing temperature compensated read voltages to select 121185.doc -33-1336081 word lines. Most of these techniques do not rely on obtaining an actual temperature measurement. But this method is also possible. For example, 'nominal' "v〇ltage Generati〇n

U.S. Patent No. 6,801,454, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the The circuit uses a bandgap current that includes a portion that is independent of temperature and a temperature dependent portion that increases with increasing temperature. The nominal "Non-Volatile Memory With Temperature-Compensated

U.S. Patent No. 6,560,152, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the the the the the U.S. Patent No. 5,172,338, the entire disclosure of which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire disclosure Incorporate this article by reference. The reference storage units provide reference levels for comparing the measured current or voltage of the selected unit to the reference level. Temperature compensation is provided because the temperature affects the reference level in the same way as the value read from the data storage unit. As described herein, any of these techniques, as well as any other known techniques, can be used to provide temperature compensation for selecting a word line, selecting a word line, and/or selecting a gate voltage. Thus, with conventional techniques, the read or verify voltage applied to one or more selected storage elements by the selected word line is temperature compensated. However, the voltage applied to the remaining word line (which is called a read voltage core (10) is applied to the selected 121185.doc • 34· (s)

The closed-pole power (which is called the selection of the interpole, the source of the vsgs or the selection of the closed pole, and the bungee of the Vsgd) has not been temperature compensated. It has been thought that temperature compensation is only performed on selected storage elements. In particular, people have been thinking that the non-selective storage element and the selection gate are overdriven to exceed their voltage so that the temperature change does not significantly affect its conductivity, however, when the transistor is scaled down to smaller In the case of dimensions, the features are degraded, and the saturation: current is increasingly deviated from a flat profile, as indicated by the small ramp (6) versus the control gate voltage (Vcg). In order to address these issues, it is recommended that Vread, Vsgd, Vsgs, and any other necessary transistors in the path of a storage element that is currently being read have a temperature compensated bias applied to their gates, such that each The on current of the transistor becomes less dependent on temperature. By performing temperature tracking on these applied voltages, the spread of the threshold distribution per _ state due to temperature changes can be further reduced. This result can be added in a variety of ways (it is not necessarily mutually exclusive)

To use. For example, Vreade can be reduced, thus reducing overdrive: !:, that is, the extent to which Vread exceeds the threshold voltage of the highest programmed state of the storage element', thereby reducing associated reads due to the use of high Vread values. interference. This reduction in Vread helps with many different read/verify techniques. This reduction is especially important for read/verify techniques that employ multiple read operations. For example, applied by Jian Chen on April 5, 2015 and is called Compensating For Coupling During Read Operations Of

Non-Volatile Memory, co-pending U.S. Patent Application Serial No. 11/099, No. 133 (No. SAND-1040US0), which is incorporated herein by reference.

Each stylized state performs a plurality of read operations on selected storage elements at different levels, which is incorporated herein by reference. For example, the increment between levels can be 50-100 mV. This technique opposes the capacitive coupling effect of the word line to the word line, where the threshold voltage of a previously programmed memory element is shifted higher when a neighboring storage element (usually a drain side neighbor) is subsequently programmed. . If the offset is large enough, a read error can be caused. This coupling is highest when the adjacent storage element is programmed to a higher state (e.g., state C). To address this problem, one of a plurality of read operations is selected for each stylized state based on the state of the adjacent storage elements on the adjacent word lines that are programmed after the storage element is selected. In one variation of this technique, a read level is used for each state on the selected word line, as determined by the verify pulse group in FIG. 13, while the read voltage applied to the adjacent word line is adjusted, this change The form is stated in the application by Nima Mokhlesi on March 17, 2, and is called "

The Operational Non-Volatile Storage With Compensation For Coupling " co-pending U.S. Patent Application Serial No. 1/384, filed on Jan. No. 57 (S. . In either of the above cases, the number of read operations for reading the same data increases, and the influence of read disturb increases. The temperature compensation techniques provided in this article can alleviate this problem. A further advantage of the temperature compensation technique provided herein is the force, various stylized states (eg, the margin between the state limit and the distribution of thresholds can be reduced with each state due to a decrease in the degree of brewing. The extension is increased. Another advantage is that 'the program 12I185.doc • 36- c S can be added by the following method; 1336081 performance can be increased by the threshold of the voltage distribution of various stylized states. Ample and use a larger step size in the stylized pulsating staircase series. Another advantage is that the entire memory operating window port (for example, the threshold voltage range used to store the lean material in the storage element) It can be reduced by compressing the stylized L closer to __, thereby not only reducing read and write interference, but also increasing write performance, which is required to achieve a desired stylized state. The stylized pulsations will be reduced by a smaller window.

The accuracy of the voltage correction can be further improved by providing a reference word line in the other non-selected word lines (which are associated with the set of non-volatile storage elements). This accuracy improvement can be seen by comparing line 1 to 1430. This temperature compensation can be implemented for the selected word line alone or in combination with the temperature compensation of the non-selected word line. See Figure 15 for a word line dependency for non-selected sub-lines.

Figure (5) is a timing diagram that explains the behavior of certain waveforms during a read/verify operation. The voltage in the a-cafe compensation is applied to all non-selected word lines and to two (four) _ poles - in general, in reading During the fetch and verify operation, select the word line or its (4) financial connection to the mf μ-bit ^ for the per-read and verify operation I is concerned with the storage of the component - the limit of electricity waste has been the same level . After the word line voltage is applied, the conduction current of the storage element is measured to determine if the storage element is conductive. If the measured conduction current is greater than a certain value, it is assumed that the storage element has a voltage of ==! the line is greater than the threshold voltage of the storage element. If the measurement "conducting electrical level is not greater than this value, then the storage element is assumed to be non-conducting and 121185.doc

(S -37-1336081 The voltage applied to the word line is not greater than the threshold voltage of the storage element.

There are many ways to measure the conduction current of a storage element during a read or verify operation. In one example, y or not allowed is allowed to measure the conduction current of the storage element at a rate at which the NAND string comprising the storage element discharges the bit line. The charge on the bit line is measured after a period of time to determine if it has been discharged. In another embodiment, the selection of the conduction of the storage element allows current to flow or not flow on a single bit line, which is measured based on whether a capacitor in the sense amplifier is charged due to current flow. Two examples are discussed above.

Figure 15a shows the waveforms SGD, WLunselected, WLn, SGS, select BL, and the source starting at a steady state voltage Vss of about 0 volts. SGD represents the gate of the gate selection gate. WLunselected represents a non-selected word line. WLn is selected for reading/verifying word lines. The gate of the gate side of the SGS system selects the gate of the gate. The bit line selected by the BL system for reading/verification is selected. The source line of the source storage element (see Figure 4). Note that there are two variations of the SGS and the selected BL. A set of such waveforms SGS (option 1) and select BL (option 1) illustrate a read/verify operation for an array of storage elements by determining whether the bit line has been discharged Measure the conduction current of a storage component. Another set of such waveforms SGS (option 2) and select BL (option 2) illustrate a read/verify operation of a one-to-one array of storage elements for discharging a dedicated capacitor in the sense amplifier The rate is used to measure the conduction current of a storage element. First, reference will be made to SGS (option 1) and selection BL (option 1) to determine the conduction current of a storage element by determining whether the bit line has been discharged. S) 121185.doc • 38· Sensing involved The behavior of the circuit and the array of storage elements. At time 11, SGD and SGS (option 2) are raised to Vsgd tcA Vsgs tc, respectively, where "tc" represents a temperature compensated voltage. Vsgd_tc & Vsgs are obtained by biasing Vsgd and Vsgs for temperature respectively. For example, ^ buckle and about 3 5 volts. For example, temperature compensation can be applied in accordance with the compensation techniques described above. Raise the non-selected word line to Vread-tc. Vread_tc is obtained by biasing Vread for temperature. For example, Vread is approximately 6 volts. The selected word line is boosted to Vcgr-tc (control gate read voltage) for a read operation, such as Vra, Vrb or Vrc. of FIG. 1, or raised to a verify level for a verify operation, such as Figure 10 is Vva, Vvb or Vvc. In one approach, BL will be selected (option precharged to about 0.7 volts. Application to unselected word line 2Vread_tc acts as an overdrive voltage because it causes the non-selected storage element to conduct and act as a transfer gate. The overdrive voltage of the selected storage element is equal to the amount of voltage applied to the control gate that exceeds the threshold voltage. As mentioned, Vread is selected to a level well above the highest threshold voltage of the storage element to ensure non-selective storage. The components are in a conducting or conducting state. For example, the threshold voltages of states E, A, B, and C can be assumed to be -2 volts, volts, 2 volts, and 4 volts, respectively, while deuterated "in the absence of temperature compensation. The lower can be 6 volts. In this case, the storage element in state E is driven by 6_(-2)=8 volts, and the storage element in state a is driven by 6〇=6 volts, in state B. The storage element is driven over 6·2 = 4 volts, and the storage element in state C is driven over 6-2 = 2 volts. Although in each case the non-selective storage element is in a conducting state, Conductivity will vary based on the degree of overdrive The higher the received drive unselected storage element

121185.doc • 39- S The better conductivity of the 81 is due to its smaller source-drain resistance and higher current carrying capacity. Similarly, the lower the drive, the worse the conductivity of the non-selected components due to their larger source-drain resistance and lower current carrying capacity. Therefore, the storage elements in the same NAND string as the selected storage elements will have different conductivities depending on their stylized state, even if they are all in a general conductive state. Therefore, the read level of the selected storage element will be affected by the non-selected storage element according to its corresponding stylized state.

Assuming a temperature compensation of -0.2 volts, Vread_tc = 6_〇2K = 58 volts. For example, for reasons similar to non-selective storage elements, the voltage applied to the select gate can be temperature compensated, thereby allowing volts / g tc or Vsgs-tc 〇 unselected word lines and select gate temperature Compensation often results in a more dependent temperature reading of the selected word line threshold voltage. Thus, each non-selective component in series with the selected storage element has a small effect on the read obtained by selecting the threshold voltage of the storage component, for example, 3 mV. Although a non-selective storage element has less effect on reading, when there are 31 unselected word lines, the cumulative effect of each of the (4) non-selected (four) memory elements can be aggregated to a significant amount, such as 93 mV. The temperature compensation effect of the unselected word lines is more pronounced for memory devices with more word lines and when using reduced overdrive voltages. At time t2, the NAND string can control the bit line. Also at time ^, the source (4) selects the gate system, and by means of the coffee (option 1} is raised to ^7, the reference is turned on to dissipate the charge on the bit line. If selected for reading If the threshold voltage of the storage element & _ & is greater than Vcgr or the verification level applied to the selected word line WLn, then the selected storage element will not be turned on and the bit line 121185.doc

.40-S does not discharge' as depicted by line 1450. If the threshold voltage in the storage element selected for reading is lower than Vcgr_tc or lower than the verify level applied to the selected word line WLn', the storage element selected for reading will be conductive (conductive) and the bit The line voltage will dissipate as shown by curve 1452. At a point before time t2, which is determined by the particular implementation, at a point before time t3, the sense amplifier will determine if the bit line has been dissipated by a sufficient amount. Between t2 and t3, the sense amplifier measures the estimated BL voltage. At time t3, the waveform depicted will be reduced to Vss (or another alternate or recovered value). The behavior of the sensing circuit and the storage element array to measure the conduction current of the storage element at a rate at which a dedicated capacitor is charged in the sense amplifier is discussed below with reference to SGS (option 2) and selection BL (option 2). At time u, SGD rises to Vsgd_tc, the unselected word line (WLunselected) rises to Vread-tc, and the selected word line (WLn) rises to vcgr_tc (eg, Vra, Vrb, or Vrc) for a read operation. Or escalate to a verification level (eg, Vva, Vvb, or Vvc) for a verification operation. In this case, regardless of what the NAND string is doing, the sense amplifier keeps the bit line voltage constant so that the sense amplifier measures the current flowing in the bit line "clamp" to the voltage. At some point after time U and before time t3, which is determined by the particular implementation, the sense amplifier will determine if the capacitor in the sense amplifier has been dissipated - a sufficient amount. The waveform depicted at time t3 will be reduced to Vss (or another alternate or recovered value). Note that in other embodiments, the timing of certain waveforms can be changed. Figure 15b illustrates the timing diagram of Figure 15a in which different temperature compensated voltages are applied to the selected word line based on the word line position. As discussed in connection with FIG. 14, in a method of 121185.doc,, 1336081, when the position of the word line is closer to the drain than the source, a higher magnitude temperature compensation (eg, a negative value) can be used. Larger) applied to the selection strand. This is illustrated by the timing diagram of Figure 15b, in which the temperature compensated voltage applied to a selected word line (e.g., WL 更) closer to the source is shown by a dashed line and applied to a selected word line that is closer to the drain. The temperature compensated voltage (e.g., WL31) is shown by a solid line. The temperature compensated voltage applied thereto when the selected word line is in the middle of the source and the drain is in the middle of the voltage applied thereto when the selected sub-line is on the source side or the drain side, for example, from the source or the drain The distance is proportional. A word line position dependency can be provided for the voltage applied to one or more of the select gate and the unselected word line. Figures 16-18 can be modified in an analogy manner to provide a word line position dependency. Figure 16 is a timing diagram illustrating the behavior of certain waveforms during a read/verify operation where the temperature compensated voltage is applied to all non-selected word lines except for the word line directly adjacent to a selected word line, and applied to both Select the gate. The waveforms SGD, SGS (option 1) and SGS (option 2) are the same as in Figure i5a. The selection of the BL and source waveforms (not shown) is also the same as in Figure i5a. Note that the waveforms labeled WL0 through WLn-2 represent temperature compensated reads applied to word lines located between the first word line WL0 and the sub-line WLn-2 and including the first word line WL0 and the word line WLn-2. Taking the voltage, the word line WLn_2 is next to the source line side adjacent to the word line WLn. The waveforms labeled WLn 2 through WL3 1 represent application to word line WLn+2 (which is followed by one of the drain side adjacent word lines WLn+丨 of the selected word line WLn) and WL3丨 (which is directly adjacent to the drain side select gate) The temperature compensated read voltage is between and including the word lines of word lines WLn+2 and WL3 1. Assume that there are thirty-two stocks on the sjAND string

121185.doc -42· '·: S J 1336081 components, but different quantities are also available. For such non-selected word lines, temperature compensation is applied as described. Similarly, for the selected word line WL11, a temperature compensated control gate read voltage Vcgr-tc is applied. For any one or both of the word lines WLn-Ι and WLn+i directly adjacent to the selected word line, the applied read voltage is not temperature compensated, or is temperature compensated by a reduced amount, for example, The temperature compensation applied to other unselected word lines is significantly reduced compared to a significant amount. The optimal φ. compensation for a particular pair of memory devices can be determined by testing. It is desirable that the word lines WLn-i and WLn+1 are treated differently than other word lines by selecting a parasitic capacitance path between the storage element and the adjacent storage element. That is, a temperature compensated voltage applied to Vread adjacent to the storage element can be capacitively coupled to the optional storage element to shift its threshold voltage higher. In particular, it is possible to use multiple read level read/verify techniques for each stylized state, which can be problematic. Further, it is desirable that the word lines WLn-Ι and WLn+Ι are processed in a manner different from each other with respect to temperature compensation. φ Circle 17 is a timing diagram that illustrates the behavior of certain waveforms during a read/verify operation, with a select word line directly adjacent to a source side select gate. The waveforms SGD, SGS (option 1) and SGS (option 2) are the same as in Figure I5a. The selection of the BL and source waveforms (not shown) is also the same as in Figure 15a. Here, the selected word line WL0 is directly adjacent to the source side selection gate. As mentioned, for some read/verify techniques, it is desirable that temperature compensation is not applied to the read voltage applied to the transistor adjacent to the selected storage element. These adjacent transistors include a source side select gate on the side and a storage element associated with and on the other side. Therefore, in one possible method, the applied voltage 12I185.doc 1336081 is not temperature compensated, or the temperature compensation is applied to other unselected word lines and another select gate (which is not directly adjacent to the selected storage element) The compensation of the gate on the drain side is a small amount. In particular, Vsgs can be applied Vread-tc can be applied to WL0 and WL2 to red 3 1, Vread can be applied to WL1, and Vsgd-tc can be applied to SGD. Figure 18 is a timing diagram illustrating the behavior of certain waveforms during a read/verify operation, with the selected word line directly adjacent to a drain side select gate. Waveforms SGD, SGS (option 1) and SGS (option 2) are the same as in Figure 15a. The selection of BL and source waveforms (not shown) is also the same as in Figure 15a. Here, the selected word line WL3 1 is directly adjacent to the drain side selection gate. As mentioned, for some read/verify techniques, it is desirable not to apply temperature compensation to the transistor applied to the adjacent selected storage element. The voltage is read. These adjacent transistors include a gateless select gate on the side and WL3〇 on the other side. Therefore, in one possible method, the applied voltage is not temperature compensated, or the temperature compensation is applied to other unselected word lines and another selected gate (not directly adjacent to the source side select gate of the selected storage element) The compensation of the pole is a small amount. In particular, Vsgs-tc can be applied to SGS, Vread-tc can be applied to WL0 to WL39' Vread can be applied to WL30, and Vsgd can be applied to SGD. Therefore, in the methods of FIGS. 17 and 18, the voltage applied to one or two selection gates can be set to a different level depending on whether the adjacent storage elements are selected or not selected, for example, an un-temperature. The level of compensation or the level of compensation. Figure 19 is a flow diagram illustrating one embodiment of a method for staging non-volatile memory. In some embodiments, the storage element is erased (in blocks or other units) prior to being formatted as -44.121185.doc 1336081. In step 19, the controller issues a "data load," command and the control circuit 31 receives the round. In step 1905, the address data of the specified page address is input from the controller or host to the decoder 314. In step 191, one of the programmed pages of the addressed page is input to a data buffer for stylization. The data is latched into a suitable set of latches. In step 1915, the controller issues a "stylized" command to state machine 312. After being triggered by the "stylized" command, the data latched in step 1910 is programmed to the state using the stepped pulsations 1310, 1320, 1330, 1340, 1350, ... of Figure 13 applied to the appropriate word line. The machine 312 controls the selection in the storage element. In step 1920, the stylized electric dust Vpgm is initialized to a start pulse (e.g., 12 volts or another value) and the programmed counter PC maintained by the state machine 312 is initialized to 〇. In step 1925, a first marshal pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. The right logic "0" is stored in a specific data latch, which indicates that the corresponding storage element is stylized, and the corresponding bit line is grounded. On the other hand, if the logic "1" is stored in the specific latch If the corresponding storage element remains in its current data state, the corresponding bit line is connected to prohibit stylization. In step 1930, as discussed, the state of the stored 7L piece is verified using a suitably temperature compensated voltage and a voltage $ without temperature compensation or temperature compensated by a reduced amount. If it is detected that the target threshold voltage of a selected storage element has reached the appropriate level, the bead stored in the corresponding data latch is changed to logic "1". If it is detected that the threshold voltage has not yet reached the appropriate level of 121185.doc -45-1336081, the material change (4) is stored in the corresponding material of the material. In this way, there is no need to stylize the bit line of the logic "1" stored in its data latch. When all data latches store logic τ, the state machine (by the above-mentioned via) Or "type mechanism] know that all selected storage components are stylized. In step (10), it is checked whether the data latches are stored with logic T. If so, the stylization process is complete and the success of all selected storage components is programmed and verified.

Report the "pass" status in step mo. In one embodiment, as previously described with reference to Figures 15-18, the verification of step 193 includes providing a temperature compensated voltage to one or more unselected word lines and providing to one or more select gates .

Right to step 1935, it is determined that not all data latches store logic "1" and the stylization process continues. In step 1945, the stylized counter pc is checked against the stylized limit value PCmax. An example of a stylized limit value is twenty, but other quantities can be used. ^ If the stylized count Pc is not less than PCmax, the stylization process has failed and is reported in the step, failure status. If the stylized counter PC is less than pCmax Then, the Vpgm level increases the step size and increments the counter PC in step 1955. After step 1955, the process loops back to step 1925 to apply the next Vpgm pulse. For illustrative purposes and description @, above The present invention has been described in detail. The invention is not limited to the precise form of the present invention. Many modifications and changes can be made in accordance with the teachings above. It is a good idea to explain the principles of the present invention and its practical application so that other skilled practitioners can make the best use of the present invention in various implementations suitable for the specific application of the specific 121185.doc -46 - 1336081 concept. The invention is intended to be defined by the scope of the accompanying claims. [Simplified Schematic] Figure 1 is a top view of a NAND string. Figure 2 is an equivalent circuit diagram of a NAND string. Figure 4 is a block diagram of a non-volatile memory system. Figure 6 is a block diagram of a non-volatile memory system. Figure 7 is a block diagram of a non-volatile memory system. A block diagram of one embodiment of a sensing block is illustrated. Figure 8 illustrates an example of an organization of memory blocks organized into blocks of all bit line memory architectures. Figure 9 illustrates a memory array organized into An example of the organization of blocks of a parity memory architecture. Figure 10 illustrates an exemplary threshold voltage distribution group. Figure 11 illustrates an exemplary threshold voltage distribution group. Figures 12A-C illustrate various threshold voltage distributions and illustrate A process for staging non-volatile memory. Figure 13 is an exemplary waveform of a control gate applied to a non-volatile storage element during stylization. Figure 14 illustrates a threshold voltage versus temperature and word line. Figure 15a is a timing diagram illustrating the behavior of certain waveforms during a read/verify operation in which a temperature compensated voltage is applied to all unselected word lines and applied to two select gates. 85.doc •47· 1336081 Figure 15b depicts a timing diagram of Figure 15a in which different temperature compensated voltages are applied to the selected word line depending on the word line position. Figure 16 is an illustration of certain waveforms during a read/verify operation. A timing diagram of the behavior in which a temperature compensated voltage is applied to all unselected word lines except for the sub-lines directly adjacent to the selected sub-line, and applied to the two select gates. FIG. 17 is an explanation for reading/verification. Timing diagram of the behavior of certain waveforms during which the selected word line is directly adjacent to a source side select gate. Figure 18 is a timing diagram explaining the behavior of certain waveforms during read/verify 'where the selected word line is directly adjacent The gate is selected on one side of the pole. Figure 19 is a flow chart illustrating an embodiment of a process for staging non-volatile memory. [Major component symbol description] 100 transistor 100FG floating gate 100CG control gate 102 transistor 102FG floating gate 102CG control gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 121185.doc .48 1336081 106FG floating gate 120 transistor 120CG control gate 122 transistor 122CG control gate 126 汲 terminal 128 N+ doped layer 130 N+ doped diffusion region 132 N+ doped diffusion region 134 N+ doped diffusion region 136 N+ doped diffusion region 138 N+ doped diffusion region 140 p well region 150 NAND string 204 source line 206 bit line 286 Memory Device 298 Memory Die 300 Memory Array 310 Control Circuit 312 State Machine 314 On-Chip Address Decoder 315 Temperature Compensation Control 316 Power Control Module 121185.doc -49- 1336081 318 Line 320 Data Bus 330 Decoder 330A Column Decoder 330B Column Decoder 350 Controller 360 Decoder 360A Line Decoder 360B Line Decoder 365 Read/Write Circuit 365A Read/Write Circuit 365B Read/Write Circuit 370 Sensing Circuit 372 Bus Bar 380 Sensing Module 382 Bit Line Latch 390 Common Port 392 Processor 393 Input Line 394 Data latch 396 I/O interface 400 sensing block 1250 threshold voltage distribution 1300 waveform 121185.doc -50- 1336081

1310 1312 1320 1322 1330 1332 1340 1342 1350 1352 1410 1420 1430 1440 1450 ABB' CE Common part verification pulsation group sharing part verification pulsation group sharing part verification pulsation group sharing part verification pulsation group sharing part verification pulsation group line line line state status Status Status Status 121185.doc •51 ·

Claims (1)

1336081 Patent application No. 096119150~ -----__ Chinese patent application scope replacement (99 August) f left no A ten, application patent scope: ------ ', 1. a non A volatile storage system comprising: * a set of non-volatile storage elements; and - one or more circuits that communicate with the set of non-volatile storage elements by a plurality of control lines, the one or more circuits & Applying at least a first voltage to a selection control line to determine at least one stylized state of the first non-volatile storage element associated with the selection control line, and (8) applying the at least the first voltage thereto At least a portion of the time period 'time' applies a temperature compensated voltage to at least - a first non-selected control line associated with the set of non-volatile storage elements. 2. The non-volatile storage system of claim 1, wherein: the one or more circuits apply a series of the first voltages to the selection control line to determine the at least the first non-volatile storage element In the stylized state, the temperature compensated voltage is applied when each of the series of first voltages is applied to the select control line. 3. The non-volatile storage system of claim 1, wherein: the voltage-level of the temperature compensation is set according to the relative position of the at least the first non-selection control line in one of the plurality of control lines . 4. The non-volatile storage system of claim 1, wherein: during at least the portion of time during which the at least the first voltage is applied, the one or more circuits apply a voltage to a direct proximity to the selection A second non-selected control line of the control line that is not temperature compensated or temperature compensated - relative to the amount of decrease in the temperature compensated voltage applied to the first non-selected control line. 121185-9908l8.doc 5. The non-volatile storage system of the requester, wherein: at least the portion of the time at which the first voltage is applied at /, and at least 5 parts of the circuit or the circuit will be temperature compensated A voltage is applied to one of the at least one select gates of the -NAND string comprising the at least one first non-volatile storage element to control the gate. 6. The non-volatile storage system of claim 1, wherein the second 'second degree compensation voltage is sufficient to maintain the non-volatile element associated with the at least the first non-selected control line in a "conductive state" . 7. The non-volatile storage system of claim 1, wherein: the first voltage comprises: a read voltage, and the read voltage is used in the "Hui to 乂". The staggered-non-volatile storage element is programmed to read at least the stylized state of the first non-volatile storage element. 8. The non-volatile storage system of claim 1, wherein: the at least the first Thunder white ii. _ BA. The electric compact comprises a test voltage, the verification voltage is used to determine D Hai to V 4 - Whether the non-volatile storage element has reached a desired stylized state. 9. The non-volatile storage system of claim 1, wherein: s at least the first voltage is temperature compensated. 10. The non-volatile storage system of claim 1, wherein: the at least the first voltage is temperature compensated based on a relative position of the selection control line in one of the plurality of control lines. 11. The non-volatile storage system of claim 1, wherein: the set of non-volatile storage elements comprises a plurality of quasi-storage elements. 12. A method for operating a non-volatile memory, comprising: -2. 121185-990818.doc applying at least a first voltage to a selected word line to determine at least one associated with the selected word line a stylized state of the first non-volatile storage element, wherein at least the first non-volatile storage element is disposed in a set of non-volatile storage elements; and at least a portion of the time during which the at least the first voltage is applied A temperature compensated voltage is applied to at least one first unselected word line associated with the set of non-volatile storage elements. 13. The method of claim 12, wherein: applying a series of the first voltages to the selected word line to determine the stylized state of the at least the first non-volatile storage element, the temperature compensated voltage system Applied when each of the series of first voltages is applied to the selected word line. 14. The method of claim 12, wherein: according to the at least the first non-selected word line is in a plurality of non-volatile groups The relative position of the word line associated with the storage element sets the one of the temperature compensated voltage levels. 15. The method of claim 12, further comprising: applying a voltage to a second unselected word line directly adjacent to the selected word line during at least the portion of time during which the at least the first voltage is applied The voltage is not temperature compensated or temperature compensated by an amount relative to the decrease in the temperature compensated voltage applied to the first non-selected word line. 16. The method of claim 12, further comprising: at least the portion applying a temperature compensated voltage to the at least one of the times 121185-990818.doc 1336081 during which the at least the first voltage is applied The first one of the at least one selection gate of a NAND string of the non-volatile storage element controls the gate. 17. The method of claim 12, wherein: the temperature compensated voltage is sufficient to maintain the non-volatile storage element associated with the at least the first unselected word line in a conductive state. 18. The method of claim 2, wherein: at least the first voltage comprises a read voltage, and the read voltage is used to read the at least the first non-volatile storage element after the program has been programmed The stylized state of the first non-volatile storage element. 19. The method of claim 12, wherein: the at least the first voltage comprises a verify voltage for determining whether the at least the first non-volatile storage element has reached a desired stylized state. 20. The method of claim 2, wherein: at least the first voltage is temperature compensated. 21. The method of claim 12, wherein the at least the first voltage is temperature compensated based on a relative position of the selected word line in a plurality of sub-lines associated with the set of non-volatile storage elements. 121185-990818.doc