、發明說明： 【發明所屬之技術領域】 本發明係有關於-種多晶牌疊封裝結構，特別是有關於—種以晶 片承座形成上下對稱之多晶片偏移堆疊封裝結構。 【先前技術】 近年來’半導體的後段製程都在進行三度空間(Three DimensiQn丨 的封裝，峨侧最少的面積來達顺高_度或是記憶體的容量等。為 了能達到此-目的，現階段已發展出翻晶片堆疊⑽pstaeked)的方式來 達成三度空間(Three Dimension ; 3D)的封裝。 在習知技術中’晶片的堆疊方式係將複數個晶片相互堆叠於一基板 上’然後使用打線的製程(wire bonding process)來將複數個晶片與基板連 接。第1A圖即揭露-種以導線架為基底之晶片堆疊封裝之結構，如第认 圖所示，導線架5可分為内引腳部5a、外引腳部％及一平台部^，其中 平=部5c與内引腳部5a及外引腳部5b具有一高度差。首先將三個晶片 堆豐在-導線架5之内引腳5a上，接著再以金屬導線1〇、u、12來將三 個晶片上的焊塾7、8、9連接至導線架5之平台部5e上，然後，進行封 膠製程(molding process)將三個堆疊晶片及導線架5之内引腳％與部份之 平台部5c封閉，但裸露出外引腳部5b，以作為連接其他界面之引腳。另 外’在第1B圖及第1C圖中也是揭露一種晶片堆疊封裝之結構其與第 认圖之差異處主要是以電路板（咖）為基材，以便在堆叠晶片與電路 板連接後’可以經由錫球（S〇lderBall)與外部電路連接。 上述習知之晶片堆疊封裝結構中，除了晶片間形成偏移，使得在進 行注膠時，會造成顧的不平衡也狗勻之外；還有晶片_的金屬導 線’例如：第1A圖中的ίο、u、12痞b坌 金屬導·声及孤…4 或疋第1C圖中的62，其在每一條 ，屬導線的長度及弧度柄_，鎌了在進行轉雕巾，長度與 =的金«產生位移㈣致“驗料，還會_金屬導線長度 不相同，造成電訊號的相位產生變化等問題。 【發明内容】 有發日讀景中所述堆疊方式之缺點及問題，本發明提 =種使用多“偏移堆疊的方式，來將複數個尺寸相近似的⑼以上下 對稱之方式來堆疊成一種三度空間的封裝結構。 本發明之主要目的在提供—種具有上下對稱之多晶片偏移堆疊封裝 、、'。構，使其具有較高的龍積集度以及㈣的封裝厚度。 本發明之另-目的在提供—種具有上下對稱之多晶片偏移堆疊封裝 4 ’使堆疊結構巾的每—條金料_導_連翻長度及弧度近似。 本發明之再-目的在提供—種具有上下對稱之多晶片偏移堆疊封裝 結構’使得進行轉時的上下模流能賊到平衡。 本發明之還有-目的在提供—種具有上下對稱之多晶片偏移堆疊封 裝結構’其可藉由在導線財配錢赫，使得多㈣偏卿疊封裝結構 具有較佳的電路應用之彈性。 據此，本發明提供-種具有上下對稱之多晶片偏移堆疊封裝結構，包 3.個由複數個成相對排列之内引腳群以及一個晶片承座組成之導線 架，晶片承座位於複數個相對排列之内引腳群之間，且内引腳群與晶片 ，座均各★自具有上表面及下表面；—個由複數個相同尺寸之晶片偏移堆 ®而成的第-多晶片偏移堆疊結構以下層晶片之被動面固接於晶片承座 之上表面、’且第-多晶片偏移堆疊結構中之每一晶片之主動面的一側邊 上配置有複數個焊墊；一個由複數個相同尺寸之晶片偏移堆疊而成的第 -多晶片偏移堆疊結構，以下層晶片之被動面固接於晶片承座之下表 =、且第—夕晶片偏移堆疊結射之每一晶片之主動面的—側邊上配置 複數個焊墊；複數條第—金屬導線由—侧邊將第—多晶片偏移堆疊結 之複數個料與導線架之㈣腳群之上表面電性連接；而複數條第二 金屬導線由另-側邊將第二多晶片偏移堆疊結構之複數個烊塾與導線架 =另-侧㈣腳群之下表面紐連接，m個娜體來包覆第一多、 μ片偏移堆疊結構、第二多晶片偏移堆疊結構、㈣腳群以及晶片承座 接著’本發明再提供一種具有上下對稱之多晶片偏移堆疊封裝結構， 包含：-個由複數個成相對排列之内引腳群、匯流架以及晶片承座組成之 導線架’晶片承錄於複數個相對排列之内引腳群之間，且内引聊群與晶 片承座均各自具有上表面及下表面，而匯流架配置於内引腳群與晶片承座 之間；-個由複數個相同尺寸之晶片偏移堆疊而成的第__多晶片偏移堆疊 結構以下層，片之鶴面固接於晶片承座之上表面，且第一多晶片偏移堆 疊結構中之每-晶片之主動面的—側邊上配置有複數個焊墊；—個由複數 個相同尺寸之晶片偏移堆疊而成的第二多晶片偏移堆疊結構，以下層晶片 之被動面固接於晶片承座之下表面，且第二多晶片偏移堆疊結構中之:一 晶片之主動面的-側邊上配置有複數個焊塾;複數條第一金屬導線由一側 邊將第-多晶片偏移堆疊結構之複數個焊墊與導線架之内引腳群之上表 面電性連接；而複數條第二金屬導線由另—側邊將第二多晶片偏移堆疊姓 構之複數個焊塾與導線架之另-側内引腳群之下表面電性連接；以及^ 個封膝體來包覆第-多晶片偏移堆#結構、第二多晶片偏移堆疊結構、内 引腳群以及晶片承座並《出外引腳；其中該第—多晶片偏移堆疊结構中 之相同尺寸之該些晶片無第二多晶片偏移堆疊結構中之相同尺寸之該 些晶片數量相同且上下對稱’以及該複數條第—金屬導線及該複數條第二 金屬導線形成對稱。 【實施方式】 數個对，來將複 maa “ 城種—度工間的封裝結構。為了驗底地瞭 地太發咖下觸贿巾提料盡㈣裝步職其封裝結構。顯然 j，本發⑽施行縣限定“堆獅方式與技藝者熟㈣特殊細節。另 眾所周♦的sa片形成方式以及晶片薄化等後段製程之詳細步驟並 未描述於細節巾，以避免造成本剌不必要之關。細，對於本發明的 較佳實施例，則會詳細描述如下。此外，除了這些詳細描述之外，本發明 ^可以?泛地贿在其他的實_ *，而本發餐翻細仙之後的申 請專利範圍為準。 在現代的轉體封裝製針，均狀-個已經完成祕製程(F_ End Process)之晶圓(wafer)先進行薄化處理卿⑽㈣p職ss),將晶片的厚 度研磨至2〜20 mil之間；然後，再塗佈(c〇a㈣或網印㈣她幻一層高分 子^)材料於晶片的背面，此高分子材料可以是一麵脂㈣岭特 別是一種B-Stage樹脂。再經由一個烘烤或是照光製程，使得高分子材料 呈現-種具有_度的伟化膠；再接著，將—個可以移除的膠帶㈣〇 貼附於半ID化狀的高分子材料上；然後，進行晶圓的切割(霍㈣ process)使曰a圓成為一顆顆的晶片(脱）；最後，就可將一顆顆的晶片與 基板連接並且將晶片形成堆疊晶片結構。 請參考第2 A與第2B圖所示，係一完成前述製程之晶片2〇〇之平面 示意圖及剖面示意圖。如第2B圖所示，晶$ 2⑼具有_主動面21〇及一 相對主動面之者面220，且晶片背面220上已形成一黏著層230 ;在此要 1333271 強調，本發明之黏著層23〇並未限;^前述之半固化膠，此黏著層a。 之目的在與基板或是晶片形成接合，因此，戶、要是具有此一功能之黏著材 料，均為本發明之實施態樣，例如：夥膜(die attached f_。此外，本發 明之黏著層23G也可以是-種具有絕緣功能之材質所形成。 接著’請參考第2C圖’係本發明之完成多晶片偏移堆疊結構3〇之 面不意圖。如第2C圖所示，晶片2〇〇的主動面21〇上配置有複數個焊 墊240 ’且複數個焊墊240已配置於晶片2⑻的同一侧邊上因此將晶 片背面220上的黏著層230與另一晶片2〇〇的主動面21〇進行偏移 (OFFSET)接合後’即可形成多晶片偏移堆疊結構3〇，其中這種多晶片偏 移堆疊的結構30係以焊線接合區250之邊緣線26〇為參考之排列基準來 形f ’因此可以形成類似階梯狀之多晶片偏移堆疊結構3〇，在此要說明 的疋’邊緣線260實際上是不存在於晶片2〇〇上，其僅作為一參考線。在 此仍然要強調’本實施例之黏著層23〇並未限定為前述之半固化膠，此黏 著層230之目的在與基板或是晶片形成接合，因此，只要是具有此一功能 之黏著材料，均為本發明之實施態樣。同時，晶片200之堆疊數量並未限 制，例如：兩個或複數個晶片200所形成之偏移堆疊結構均為本發明之實 施態樣® 本發明在多晶片偏移堆疊之另一實施例中，係使用一種重配置層 (Redistribution Layer，RDL)來將晶圓上的每一個晶片之焊墊配置到晶片的 側邊上，以便能形成多晶片偏移堆疊的結構，而此重配置層之實施方式 說明如下。 請參考第3A〜3C圖，係為本發明之具有重配置層之晶片結構的製造 過程示意圖。如第3A圖所示，首先提供晶片本體31〇，並且在鄰近於晶 片本體310之一側邊規劃出焊線接合區32〇，並將晶片本體31〇之主動表 面上的多個坏塾3〗2區分為第一焊墊312a以及第二痒墊312b，其中第一 10 1333271 焊塾312a係位於焊線接合區3勒，而第二焊，墊皿則位於焊線接合區 320外。接著請參考第3B 0，於晶片本體31〇上形成第一保護層33〇， 其中第一保護層330具有多個第一開口 332，以曝露出第一焊塾遍與 第二焊塾312b。然後在第一保護層33〇±形成重配置線路層MO。而重配 置線路層340包括多條導線342與多個第三焊墊％，其中第三焊墊％ 係位於銲線接合區320内’且這些導線342係分職第二焊墊獅延伸 至第三焊塾344 ’以使第二料312b電性連接於第三焊墊344。此外，重 配置線路層340的材料，可以為金、銅、錄、鈦化鶴、鈦或其它的導電材 料:再請參考第3C ®，在形成重配置線路層mo後，將第二保護層35〇 覆蓋於重配置線路層34G上，而形成晶片結構·，其中第二保護層35〇 具有多個第二開口 352,以曝露出第一焊塾312a與第三谭墊別4。 *要強調的是’雖然上述之第一焊塾312a與第二焊塾迎係以周圍 型態排列於晶片本體310之主動表面上，然而第一焊墊312&與第二焊墊 通亦可以經由面陣列型態(area array咖)或其它的型態排列於晶片本 體310上’當然第二焊塾312b亦是經由導線3幻電性連接於第三焊墊 344。另外’本實施例亦不限定第三焊塾344 _列方式，雖然在第狃 圖中第三焊墊344與第-焊塾312a係、排列成兩列，並且沿著晶片本體训 之單一側邊排列，但是第三焊墊344與第一焊墊312a亦可以以單列、多 列或是其它的方式排列於焊線接合區320内。 請繼續參考第4A圖與第4B圖，係為第3C圖中分別沿剖面線从 與B-B’所繪製之剖面示意圖。如第4A圖與第4B圖所示，由上述圖示中 可知晶片、结構300主要包括晶片本體3 i〇以及重配置層4〇〇所組成，其中 重配置層400係由第一保護層33〇、重配置線路層34〇與第二保護層乃〇 所形成。晶片本體310具有焊線接合區320，且焊線接合區32〇係鄰近於 晶片本體310之單-側邊。另外，晶片本體31〇具有多個第一焊塾祀& 1333271 以及第二焊塾312b-’其中第一焊塾312a位於焊線接合區咖内，且第二 焊墊312b位於焊線接合區32〇外。 第一保護層330配置於晶片本體31〇上，其中第一保護層33〇具有 多個第-開π 332 ’以曝露出這些第__焊㈣&與第二焊塾现。重配 置線路層340配置於第一保護層33〇上，其中重配置線路層34〇從第二焊 塾312b延伸至焊線接合區32〇内，且重配置線路層34〇具有多個第 墊344 ’其配置於焊線接合區32〇内。帛二保護層35〇覆蓋於重配置線路 層340上，其中第二保護層35〇具有多個第二開口 352，以曝露出這些第 -焊墊312a與第三焊墊344。由於第—焊㈣與第三焊墊344均位於 焊線接合區320内，因此第二保護層35〇上之焊線接合區32〇以外之區域 便能夠提供—個承載的平台，以承載另—個晶片結構，因此可以形成一種 多晶片偏移堆疊的結構。 一立接著’請參考第5 ®，縣發明之—種多晶片偏移堆疊結構之剖面 示意圖。如第5圖所示’多晶片偏移堆疊結構％係由兩個或複數個晶片 5〇〇堆疊而成’其中晶片500上具有重配置層·，故可將晶片上的焊塾 (即3以或別4)配置於晶片5〇〇之焊線接合區汹之上，因此這種多 晶片偏移堆疊結構5G係以谭線接合區32()之邊緣線322為對準線來形 成。而複數個晶4 5〇〇之間係以一黏著層23〇來連接。首先，晶片 之間的黏著層230是位於晶片5⑻之背面，此一黏著層23〇之形成方式如 第2B圖所示，係與晶片同時完成的。由於晶片5〇〇之主動面上配置有重 配置層400，故可將晶片上的谭塾配置於晶片5〇〇之浮線接合區汹之 上’因此’可以將晶片5G0背面上的黏著層mo與另—晶片之重配置 層400進行偏移(〇ffset)接合後，形成一種多晶片偏移堆疊結構％，其令 這種多晶片偏移堆疊的結構50係以焊線接合區MO之邊緣線您為參考 之基準來排列堆疊形成，因此可以形成類似階梯狀之多晶片偏移堆疊結構 12 或疋夕日日片偏移堆疊結構7()(由—個晶片與一個晶片5⑽而 成），如第5A圖或第5B圖所示。 . 接著本翻依據上叙多晶#偏移堆疊結構3G及％更提出-種 "Isa片封裝結構，並且詳細說明如下。同時，在如下之說明過程中， 堆^晶片偏移堆疊結構Μ為例子進行，_要強調的是，多晶片偏移 且結構30及多晶片偏移堆疊結構7〇亦適用本實施例所揭露之内容。 接者’請參考第6圖，係本發明之具有上下對稱之多晶片偏移堆疊 封裝結構之剖面示意圖。首先，如第6圖所示，導線架_係由複數個成 相對排列之内引腳610以及一個晶片承座62〇所組成，其中晶片承座㈣ 位於複數個相對排列之内引腳61〇之間。要強調的是，在本實施例中，晶 片承座620與内引腳61〇之間形成一共平面且内引腳61〇具有一個上表 面611及-個下表面612，而晶片承座62〇也具有一個上表面⑵及一個 下表面622。接著’將一個晶片2〇〇a貼著於晶片承座62〇之上表面621 上，而晶片200a與晶片承座620之上表面622之間的接合係由位於晶片 200a背面上的黏著層23〇來達到黏貼的效果。然後，進行一加熱或是烘 烤製程’藉以固化位於晶片背面22〇及晶片承座62〇之間的黏著層23〇 ; 接著，再將另一晶片200b以一個偏移量黏貼於晶片200a上，使得位於晶 片200b的背面220上的黏著層230貼附於晶片200a的主動面210之 上，以便可以將主動面21〇上的焊墊240曝露》接著，可以選擇性地繼續 重複前述之動作’即可在晶片承座620之上表面622上形成複數個晶片的 堆疊結構30。 接著’將導線架反轉180度，使得導線架600之晶片承座620之了 表面622的面朝上’然後進行本實例先前之步驟，將晶片200c與晶片承 座620之下表面622固接，並在進行烘烤程序後，將另一晶片2〇〇d以— 個偏移量黏貼於晶片200c上，使得位於晶片200c的背面220上的黏著 13 層230貼附於晶片200d的主動面210之上，以便可以將主動面210上的 焊墊240曝露。接著，可以選擇性地繼續重複前述之動作，即可在晶片承 座620之上表面622上形成複數個晶片的堆疊結構3〇。 在完成上述製程後，已經在晶片承座62〇的上表面621及下表面622 上分別形成一個由複數個晶片所形成之偏移堆疊結構3〇 ;很明顯地，位 於晶片承座620的上表面621及下表面622的多晶片堆疊結構3〇是對稱 於晶片承座620,也就是說，晶片2〇〇a與晶片2〇〇d的邊緣是對齊的，而 晶片200b與晶片200c也是對齊的。當然，若選擇將晶片2〇〇a與晶片2〇〇c 的邊緣對齊且將晶片200b與晶片200d也對齊時，也可以形成本發明之上 下對稱之多晶片偏移堆疊封裝結構。 接著，進行金屬導線的連接製程（wire bonding)。首先將金屬導線 640a的一端連接於晶片2〇〇a之焊墊240上，然後將金屬導線640a之另 一端則連接於晶片200b之焊墊240上；再接著，將金屬導線640b之一端 連接於晶片200a之焊墊240上，然後再將金屬導線600b之另一端連接至 位於晶片承座620 —側邊的内引腳61〇之上表面611上。在將導線架600 反轉180度後，繼續進行另一個多晶片偏移堆疊結構的金屬導線連接程 序，也就是重複金屬導線640a及640b的過程，以金屬導線640c來將晶 片200c與晶片200d完成電性連接;再接著，以金屬導線64〇d將晶片200c 與位於晶片承座620另一側邊的内引腳61〇之上表面611上完成電性連 接。如此一來’經由金屬導線64〇a、640b、640c及640d等逐層完成連接 後，便可以將晶片200a、200b、200c及200d電性連接於導線架600，其 中這些金屬導線640的材質可以使用金。最後進行一封膠製程，以一封膠 體700將上下對稱的多晶片堆疊結構3〇、複數條金屬導線64〇、晶片承座 620及内引腳610覆蓋，如第6圖所示。 在此要強調，上述過程中的多晶片堆疊結構可以是由多晶片堆疊結 ^來形成上下對稱之封裝結構，其也可以是.由多晶片堆叠結構絲形 ，當然也可以是由—個多晶片堆疊結構30及-個 成上糊之封裝結構，對此本發明並不加以限BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline stacked package structure, and more particularly to a multi-wafer offset stacked package structure in which a wafer holder is formed to be vertically symmetrical. [Prior Art] In recent years, the semiconductor's back-end process is in the three-dimensional space (Three DimensiQn丨 package, the minimum area on the side of the side to reach the height of _ degrees or the capacity of the memory, etc. In order to achieve this - purpose, At this stage, a flip-chip stack (10) pstaeked) has been developed to achieve a three-dimensional (Three Dimension; 3D) package. In the prior art, the "wafer stacking method is to stack a plurality of wafers on each other on a substrate" and then a plurality of wafers are connected to the substrate using a wire bonding process. FIG. 1A discloses a structure of a wafer stack package based on a lead frame. As shown in the first drawing, the lead frame 5 can be divided into an inner lead portion 5a, an outer lead portion %, and a platform portion ^, wherein The flat portion 5c has a height difference from the inner lead portion 5a and the outer lead portion 5b. First, the three wafers are stacked on the lead 5a of the lead frame 5, and then the solder wires 7, 8, 9 on the three wafers are connected to the lead frame 5 by the metal wires 1〇, u, 12 On the platform portion 5e, then, a molding process is performed to close the inner pin % of the three stacked wafers and the lead frame 5 and the portion of the land portion 5c, but the outer lead portion 5b is exposed to serve as a connection. The interface pin. In addition, in FIG. 1B and FIG. 1C, a structure of a wafer stack package is also disclosed. The difference from the first figure is mainly based on a circuit board (coffee), so that after the stacked wafer is connected to the circuit board, Connected to an external circuit via a solder ball (S〇lderBall). In the above-mentioned conventional wafer-stacked package structure, in addition to the offset between the wafers, when the injection is performed, the imbalance of the film is caused by the unevenness of the film; and the metal wire of the wafer_ is as shown in FIG. 1A. Ίο, u, 12痞b坌 metal guide sound and solitary ... 4 or 62 1C in the figure 62, in each of the strips, the length of the wire and the curvature of the handle _, 镰 在 进行 进行 进行 , , 长度The gold «generating displacement (four) causes "reporting, and the length of the metal wire is not the same, causing changes in the phase of the electrical signal." [Summary of the invention] The shortcomings and problems of the stacking method described in the daily reading scene, The invention proposes to use a plurality of "offset stacking methods" to stack a plurality of dimensions (9) or more in a lower symmetrical manner to form a three-dimensional space package structure. The main object of the present invention is to provide a multi-wafer offset stacked package having 'up and down symmetry'. It has a high degree of dragon accumulation and (4) package thickness. Another object of the present invention is to provide a multi-wafer offset stacked package 4' having upper and lower symmetry for approximating the length and curvature of each of the stacked metal sheets. A further object of the present invention is to provide a multi-wafer offset stacked package structure having upper and lower symmetry so that the upper and lower dies flow during the turn can be balanced. Still another object of the present invention is to provide a multi-wafer offset stacked package structure having upper and lower symmetry, which can make the multi-(4-) biased package structure have better flexibility in circuit application by using the wiring in the wire. . Accordingly, the present invention provides a multi-wafer offset stacked package structure having upper and lower symmetry, and a lead frame composed of a plurality of oppositely arranged inner lead groups and a wafer holder, the wafer holder being located at a plurality Between the opposite pin groups, and the inner pin group and the wafer, each has its own upper surface and lower surface; a first-to-multiple wafer offset stack® of the same size The wafer offset stack structure has a passive surface of the lower layer wafer fixed to the upper surface of the wafer holder, and a plurality of pads are disposed on one side of the active surface of each of the first-multi wafer offset stacked structures a first-multi-wafer offset stack structure formed by stacking a plurality of wafers of the same size, the passive surface of the lower layer wafer is fixed under the wafer holder, and the first-day wafer offset stacking junction a plurality of pads are disposed on a side of the active surface of each of the wafers; a plurality of first metal wires are stacked on the side of the first plurality of wafers by a plurality of materials and a plurality of wires of the lead frame The upper surface is electrically connected; and the plurality of lines are second The metal wire connects the plurality of turns of the second multi-wafer offset stack structure from the other side to the surface of the lead frame = the other side (four) leg group, and the m pieces are covered with the first plurality, the μ piece Offset stack structure, second multi-wafer offset stack structure, (four) foot group and wafer holder. Next, the present invention further provides a multi-wafer offset stack package structure having upper and lower symmetry, comprising: - a plurality of relative arrangement The lead frame of the lead group, the bus bar and the wafer holder is recorded between the plurality of oppositely arranged pin groups, and the inner and the wafer holders respectively have an upper surface and a lower surface. The busbar is disposed between the inner lead group and the wafer holder; a lower layer of the __multi-wafer offset stack structure formed by stacking a plurality of wafers of the same size, and the sheet crane is fixed On the upper surface of the wafer holder, and a plurality of pads are disposed on a side of each of the active faces of the first multi-wafer offset stack; a plurality of wafers of the same size are offset and stacked a second multi-wafer offset stack structure to The passive surface of the lower wafer is fixed to the lower surface of the wafer holder, and the second multi-wafer offset stack structure has: a plurality of solder bumps disposed on the side of the active surface of the wafer; and a plurality of first metal wires The plurality of pads of the first-multi-chip offset stack structure are electrically connected to the upper surface of the lead group of the lead frame by one side; and the plurality of second metal wires are connected by the other side to the second multi-chip The plurality of soldering dies of the offset stacking name are electrically connected to the lower surface of the other side inner lead group of the lead frame; and the sealing body covers the first-multi-chip offset stack # structure, the second largest The wafer offset stack structure, the inner pin group, and the wafer carrier and the outer pins; wherein the wafers of the same size in the first-multi wafer offset stack have no second stack offset structure The plurality of wafers of the same size and the upper and lower symmetry 'and the plurality of first metal wires and the plurality of second metal wires form a symmetry. [Embodiment] Several pairs, to re-maa "City type - the degree of the package structure of the work. In order to thoroughly check the ground, too much coffee to touch the bribe towel to extract the material (four) to install the package structure. Obviously j, This issue (10) implements the county's limited “special details of the pile lion method and the skilled person (4). The detailed steps of the formation of the sa sheet and the subsequent process of wafer thinning are not described in the detail sheet to avoid unnecessary problems. Fine, for the preferred embodiment of the present invention, it will be described in detail below. In addition, in addition to these detailed descriptions, the present invention can be used in other cases, and the scope of the application after the meal is fined. In the modern swivel package needle, the wafer that has completed the F_ End Process is first thinned and processed (10) (four) p ss), and the thickness of the wafer is ground to 2~20 mil. Then, (c〇a (4) or screen printing (4) her phantom polymer ^) material is applied to the back side of the wafer. The polymer material may be a side grease (four) ridge, especially a B-Stage resin. Through a baking or illuminating process, the polymer material is presented with a _ degree of weihua gel; and then, a removable tape (4) 〇 is attached to the semi-ID polymer material. Then, the wafer is cut (the process) so that the 曰a circle becomes a single wafer (off); finally, the individual wafers are connected to the substrate and the wafer is formed into a stacked wafer structure. Please refer to the 2A and 2B drawings, which are schematic diagrams and cross-sectional views of the wafer 2 of the above process. As shown in FIG. 2B, the crystal $2(9) has an active surface 21〇 and a face 220 opposite to the active surface, and an adhesive layer 230 has been formed on the back surface 220 of the wafer; here, 13332271 emphasizes that the adhesive layer 23 of the present invention is emphasized. 〇 is not limited; ^ the aforementioned semi-curing adhesive, the adhesive layer a. The purpose is to form a joint with a substrate or a wafer. Therefore, the adhesive material having such a function is an embodiment of the present invention, for example, a die attached f_. In addition, the adhesive layer 23G of the present invention. It may also be formed of a material having an insulating function. Next, please refer to FIG. 2C for the purpose of completing the multi-wafer offset stack structure of the present invention. As shown in FIG. 2C, the wafer 2〇〇 The active surface 21A is provided with a plurality of pads 240' and a plurality of pads 240 are disposed on the same side of the wafer 2 (8), thereby bonding the adhesive layer 230 on the wafer back surface 220 to the active surface of the other wafer 2 21〇 After the OFFSET bonding, a multi-wafer offset stack structure 3 can be formed, wherein the multi-wafer offset stacked structure 30 is arranged with reference to the edge line 26〇 of the bonding wire bonding region 250. The fiducial shape f' thus forms a step-like multi-wafer offset stack structure 3, and the edge line 260 to be described herein is not actually present on the wafer 2, which serves only as a reference line. I still want to emphasize 'this. The adhesive layer 23 of the embodiment is not limited to the above-mentioned semi-cured adhesive. The purpose of the adhesive layer 230 is to form a joint with the substrate or the wafer. Therefore, as long as it is an adhesive material having such a function, the present invention is implemented. At the same time, the number of stacks of the wafers 200 is not limited. For example, the offset stack structure formed by two or more wafers 200 is an embodiment of the present invention. The present invention is another stack of multi-wafer offset stacks. In an embodiment, a Redistribution Layer (RDL) is used to dispose the pads of each wafer on the wafer to the sides of the wafer so as to form a multi-wafer offset stack structure. The embodiment of the configuration layer is described below. Please refer to FIGS. 3A to 3C, which are schematic diagrams showing the manufacturing process of the wafer structure having the reconfiguration layer of the present invention. As shown in FIG. 3A, the wafer body 31 is first provided, and adjacent thereto. A bonding wire bonding region 32〇 is planned on one side of the wafer body 310, and a plurality of gangrene 3′2 on the active surface of the wafer body 31 are divided into a first bonding pad 312a and a second itch pad 312b, wherein A 10 1333271 solder fillet 312a is located in the wire bond area 3, and a second solder is placed outside the wire bond area 320. Next, refer to the 3rd, forming a first protective layer 33 on the wafer body 31A. The first protective layer 330 has a plurality of first openings 332 for exposing the first solder bumps to the second solder pads 312b. Then, the first protective layer 33 is formed to form a reconfigured wiring layer MO. The circuit layer 340 includes a plurality of wires 342 and a plurality of third pad %, wherein the third pad % is located in the wire bonding region 320' and the wires 342 are divided into the second pad lion to extend to the third pad 344 ' is such that the second material 312b is electrically connected to the third bonding pad 344. In addition, the material of the reconfiguration circuit layer 340 may be gold, copper, recorded, titanium, titanium or other conductive materials: please refer to the 3C ® , after forming the reconfigured circuit layer mo, the second protective layer 35〇 overlies the reconfiguration wiring layer 34G to form a wafer structure, wherein the second protective layer 35 has a plurality of second openings 352 to expose the first solder bump 312a and the third solder bump 4 . * It should be emphasized that although the first solder bump 312a and the second solder bump are arranged on the active surface of the wafer body 310 in a peripheral pattern, the first solder pad 312 & The second solder fillet 312b is also galvanically connected to the third solder pad 344 via the wire 3 via the array array or other types. In addition, the third embodiment is not limited to the third soldering pad 344 _ column mode, although in the third drawing, the third bonding pad 344 and the first soldering pad 312a are arranged in two columns, and the single side along the wafer body is trained. Arranged side by side, but the third pad 344 and the first pad 312a may also be arranged in the wire bonding region 320 in a single row, a plurality of columns or in other manners. Please refer to Figs. 4A and 4B, which are schematic cross-sectional views taken along line C-B from the B-B'. As shown in FIG. 4A and FIG. 4B , it is known from the above diagram that the wafer and structure 300 mainly includes a wafer body 3 i〇 and a reconfiguration layer 4 , wherein the reconfiguration layer 400 is composed of the first protection layer 33 . The germanium, reconfigurable circuit layer 34 is formed with the second protective layer. Wafer body 310 has bond wire bond regions 320, and bond wire bond regions 32 are adjacent to the single-side of wafer body 310. In addition, the wafer body 31 has a plurality of first pads & 1333271 and a second pad 312b-' wherein the first pad 312a is located in the wire bonding area and the second pad 312b is located in the wire bonding area 32. The first protective layer 330 is disposed on the wafer body 31, wherein the first protective layer 33 has a plurality of first-open π 332 ' to expose the first __ solder (four) & The reconfiguration wiring layer 340 is disposed on the first protective layer 33A, wherein the reconfiguration wiring layer 34 extends from the second bonding pad 312b into the bonding wire bonding region 32, and the reconfiguration wiring layer 34 has a plurality of pads 344 ' is disposed in the wire bond zone 32〇. The second protective layer 35 is overlaid on the reconfiguration wiring layer 340, wherein the second protective layer 35 has a plurality of second openings 352 to expose the first pad 312a and the third pad 344. Since the first soldering (four) and the third soldering pad 344 are both located in the bonding wire bonding region 320, the region other than the bonding wire bonding region 32 of the second protective layer 35 can provide a platform for carrying the carrier. A wafer structure, thus forming a multi-wafer offset stack structure. Once again, please refer to section 5 ®, the invention of the multi-wafer offset stack structure schematic diagram. As shown in Fig. 5, 'the multi-wafer offset stack structure % is formed by stacking two or a plurality of wafers 5', wherein the wafer 500 has a re-disposing layer, so that the solder bumps on the wafer can be used (ie, 3) Or (4) is disposed on the bonding wire bonding region of the wafer 5, so that the multi-wafer offset stacked structure 5G is formed with the edge line 322 of the tan wire bonding region 32 () as an alignment line. A plurality of crystals are connected by an adhesive layer 23〇. First, the adhesive layer 230 between the wafers is located on the back side of the wafer 5 (8). This adhesive layer 23 is formed in the same manner as shown in Fig. 2B and is completed simultaneously with the wafer. Since the relocation layer 400 is disposed on the active surface of the wafer 5, the tantalum on the wafer can be disposed on the floating junction region of the wafer 5, so that the adhesive layer mo on the back surface of the wafer 5G0 can be After being offset from the other wafer reconfiguration layer 400, a multi-wafer offset stack structure % is formed which causes the multi-wafer offset stacked structure 50 to be at the edge of the bond wire bonding region MO The lines are arranged in a stacked arrangement for reference, so that a step-like multi-wafer offset stack structure 12 or a day-to-day sheet offset stack structure 7 () (made of one wafer and one wafer 5 (10)) can be formed. As shown in Figure 5A or Figure 5B. Then, according to the above-mentioned polycrystalline #offset stack structure 3G and %, the type of "Isa chip package structure is proposed, and the details are as follows. Meanwhile, in the following description, the stack offset structure is performed as an example, and it is emphasized that the multi-wafer offset and the structure 30 and the multi-wafer offset stack structure 7 are also applicable to the embodiment. The content. Referring to Figure 6, a cross-sectional view of the multi-wafer offset stacked package structure of the present invention having upper and lower symmetry is shown. First, as shown in Fig. 6, the lead frame _ is composed of a plurality of oppositely arranged inner leads 610 and a wafer holder 62 ,, wherein the wafer holder (4) is located in a plurality of oppositely arranged pins 61 〇 between. It should be emphasized that in the present embodiment, the wafer holder 620 and the inner lead 61 形成 form a coplanar and the inner lead 61 〇 has an upper surface 611 and a lower surface 612, and the wafer holder 62 〇 There is also an upper surface (2) and a lower surface 622. Next, a wafer 2A is attached to the upper surface 621 of the wafer holder 62, and the bonding between the wafer 200a and the upper surface 622 of the wafer holder 620 is made of an adhesive layer 23 on the back surface of the wafer 200a. 〇 to achieve the effect of the paste. Then, a heating or baking process is performed to cure the adhesive layer 23 between the back surface 22 of the wafer and the wafer holder 62A; then, the other wafer 200b is pasted on the wafer 200a with an offset. The adhesive layer 230 on the back surface 220 of the wafer 200b is attached to the active surface 210 of the wafer 200a so that the solder pads 240 on the active surface 21 can be exposed. Then, the above actions can be selectively repeated. A stack structure 30 of a plurality of wafers can be formed on the upper surface 622 of the wafer holder 620. Then 'reverse the lead frame 180 degrees so that the surface 622 of the wafer holder 620 of the lead frame 600 faces up' and then perform the previous steps of the present example to fix the wafer 200c to the lower surface 622 of the wafer holder 620. And after performing the baking process, the other wafer 2〇〇d is adhered to the wafer 200c at an offset such that the adhesive 13 layer 230 on the back surface 220 of the wafer 200c is attached to the active surface of the wafer 200d. Above 210, so that the pads 240 on the active surface 210 can be exposed. Then, the foregoing operations can be selectively continued, that is, a stack structure 3 of a plurality of wafers can be formed on the upper surface 622 of the wafer holder 620. After the above process is completed, an offset stack structure 3 formed of a plurality of wafers has been formed on the upper surface 621 and the lower surface 622 of the wafer holder 62, respectively; apparently, on the wafer holder 620 The multi-wafer stack structure 3 of the surface 621 and the lower surface 622 is symmetrical to the wafer holder 620, that is, the wafer 2A is aligned with the edge of the wafer 2〇〇d, and the wafer 200b is aligned with the wafer 200c. of. Of course, if the wafer 2〇〇a is selected to be aligned with the edge of the wafer 2〇〇c and the wafer 200b is also aligned with the wafer 200d, the upper and lower symmetrical multi-wafer offset stacked package structures of the present invention can also be formed. Next, wire bonding of the metal wires is performed. First, one end of the metal wire 640a is connected to the pad 240 of the wafer 2〇〇a, and then the other end of the metal wire 640a is connected to the pad 240 of the wafer 200b; then, one end of the metal wire 640b is connected to On the pad 240 of the wafer 200a, the other end of the metal wire 600b is then connected to the upper surface 611 of the inner lead 61 位于 on the side of the wafer holder 620. After the lead frame 600 is reversed by 180 degrees, the metal wire connection process of the other multi-wafer offset stack structure, that is, the process of repeating the metal wires 640a and 640b, is completed, and the wafer 200c and the wafer 200d are completed by the metal wires 640c. Electrically connected; then, the metal wire 64 〇d is used to electrically connect the wafer 200c to the upper surface 611 of the inner lead 61 位于 on the other side of the wafer holder 620. In this way, after the connection is completed layer by layer through the metal wires 64A, 640b, 640c, and 640d, the wafers 200a, 200b, 200c, and 200d can be electrically connected to the lead frame 600, wherein the material of the metal wires 640 can be Use gold. Finally, a glue process is performed to cover the upper and lower symmetrical multi-wafer stack structure 3, the plurality of metal wires 64, the wafer holder 620 and the inner leads 610 with a glue 700, as shown in Fig. 6. It should be emphasized that the multi-wafer stack structure in the above process may be a multi-wafer stack structure to form a vertically symmetrical package structure, which may also be a multi-wafer stack structure, or may be a multi-wafer stack structure. The wafer stack structure 30 and the package structure of the paste are not limited by the present invention.
UnZ丨ί堆綠構的實施例中，其差異是金屬導線所要連接的 炸墊不同而已，例如，當對多晶片堆疊結構5〇進行 製程時，金屬導線_是連接到晶請上的第—科阳 344上，如第4Α圖及第4Β圖所示。 一鲜 下在Ϊ述的實施例中，由於多晶片偏移堆疊封裝結構是上 及令属⑼#進订注膠時的上下模流能夠達到平衡；而金屬導線640a =金，導線祕與金屬導線她*金屬導線編也是對稱的故也使 4堆豐結構中的每-條金屬導線與導線架連接的長度及弧度近似。另外， =本實施例中’對於導線架_之晶片承座伽與編偏移堆疊結構之 S的接合方式，也可以選擇使用膠帶來做為連接材料特別是一種雙面具 有黏著性之膠帶（die attached film )。 此外，以金屬導線640連接導線架_與多晶片偏移堆疊結構5〇的 方式’除了上述之過程外’也可以選擇分階段完成，例如，在完成晶片承 座20上表面621的多晶片偏移堆疊結構的接合後即先進行晶片加〇玨 與晶片2_的金屬導線電性連接製程，然後，在完成晶片承座62〇之下 表面622的多晶片偏移堆疊結構的接合後，再進行晶片騰與晶片聰 的金屬導線電性連接製程’如此也可形縣㈣之具有上下賴之多晶片 偏移堆疊之封裝結構。 經由以上之說明’本發明中所述之實施例並未限制堆疊晶片2〇〇或 晶片500的數量’凡熟知此項技藝者應可依據上述所揭露之方法，而製作 出具有兩個以上偏移堆疊式封裝結構。同時，本實施例中的多晶片偏移堆 疊結構3G也可換成多晶片偏移堆疊轉％如第7圖所示或是由一個晶 15 1333271 片200與一個晶片5〇〇堆疊所形成之多晶片偏移堆疊結構7〇。由於這兩 個多晶片偏移堆疊結構30及多晶片偏移堆疊結構7〇在與導線架_接合 後的金屬導線連接過程均相同，因此不再贅述。 請繼續參考第8圖及第9圖，係本發明之多晶片偏移堆疊封裝結構 之另一實施例之剖面示意圖。在本實施例中，導線架6〇〇係由複數個成相 對排列之内引腳610以及一個晶片承座62()所組成，其中晶片承座62〇 位於複數個相對排狀㈣腳61G之間並且油引腳61Q形成一個高度 差；當晶片承座620與複數個相對排列之内引腳61〇之間形成一個下置 (d〇wn-set)的高度差時，其與多晶片偏移堆疊結構5〇完成封裝結構剖 面圓，如第8圖所示。由於此導線架600中具有下置晶片承座62〇之封裝 過程與第6圖及第7圖所示相同，故其形成具有上下對稱之多晶片偏移堆 疊封裝結構之過程不再作詳細說明。此外，當晶片承座62〇與複數個相對 排列之内引腳610之間形成一個上置（up_set)的高度差時，其與多晶片 偏移堆疊結構50完成封裝結構刮面圖，如第9圖所示。由於此導線架6〇〇 中具有下置晶片承座620之封裝過程也與第6圖及第7圖所示相同，故其 开>成具有上下對稱之多晶片偏移堆疊封裝結構之過程不再作詳細說明。 接著，請參考第10圖，係本發明之多晶片偏移堆疊封裝結構之再一 實施例之剖面示意圖。如第10圖所示，在本實施例中的導線架600係由 複數個成相對排列之内引腳610、匯流架630以及一個晶片承座62〇所組 成，其中晶片承座620位於複數個相對排列之内引腳61〇之間，而匯流架 630則是位於晶片承座62〇與複數個相對排列之内引腳61〇之間。要強調 的是，在本實施例中，晶片承座620及匯流架63〇與内引腳⑽之間形成 一共平面，且内引腳610具有一個上表面611及一個下表面612，而晶片 承座620也具有一個上表面621及一個下表面622。很明顯地，本實施例 與前述第6圖、第7圖所示 '第8圖及第9圖之間的差異處，在於本實施 16 1333271 例之導線架600上，更進一步配置至少一個通流架63〇配置有匯流架 630其可作為包括電源接點、接地接點或訊號接點之電性連接。由於 此導線架600中具有匯流架630之封裝過程與第6圖及第7圖相同，故其 形成具有_LT雜之多晶#偏移堆疊塊結構之雕不再作詳細說明。此 外’在本實施例中，導線架_巾的匯流架63〇也可以是以不同高度形成 於晶片承座620與複數個相對排列之内5丨腳⑽之間，例如在晶片承座 620之上表面621的一側，其匯流架63〇是一個上置結構，而在晶片承座 620之下表面622的—側’其匯流架63〇是一個下置結構如第n圖所 7JV ° 至於在本發明之具有匯流架630的其他實施例還包括，導線架_ 中的晶片承座620與複數個相對排列之内引腳61〇之間形成一個高度差， 例如，當晶片承座620與複數個相對排列之内引腳61〇之間形成一個下置 (d〇Wn-set)的高度差，且匯流架63〇與複數個相對排列之内引腳6ι〇之 間形成-共平面時，其與上下多晶片偏移堆疊結構5G完成封裝結構剖面 圖’如第12圖所示。由於此導線架6〇〇中具有匯流架63〇及下置晶片承 座620之封裝過程與第6圖及第7圖所示相同，故其形成具有上下對稱之 多晶片偏移堆疊封裝結構之過程不再作詳細說明。另外，當晶片承座62〇 與複數個相對排列之内引腳610之間形成一個下置（d〇wn set)的高度差， 而匯流架630的高度位於複數個相對排列之内α腳61〇與晶片承座62〇 之間時，其與上下多晶片偏移堆疊結構50完成封裝結構剖面圖，如第13 圖所示。由於此導線架600中具有匯流架630與下置晶片承座62〇之封裝 過程也與第6圖及第7圖所示相同，故其形成具有上下對稱之多晶片偏移 堆疊封裝結構之過程不再作詳細說明。 再接著，請參考第14圖，係本發明之多晶片偏移堆疊封裝結構之再 一實施例之剖面示意圖。如第14圖所示，在本實施例中的導線架6〇〇係 17 1333271 晴_細料咖所喊，其中内引腳 群61〇包括有複數個平行且具有上表面611及下表面 嶋與第二㈣腳物B所形成，並且第—内引腳群61(^引= 腳群隨之末端係以-間隙來隔開，同時第一内引腳群嶋 弓腳群麵為均藉由一平台部613與相連之連接部614來形成具有下置 /ηοΓΓ構，使得第—㈣腳群罐與第二㈣腳群雜形成 14圖所示°此外，本發明對連接部614的形狀並 接心二斜面或是近似垂直面。在此還要強調，平台部613與連 接勒!4也可叹第職或是二邮丨腳群咖的一部份。 請繼續參考第14圖所示，導線架_之第-内引腳群嶋之上表 面犯與多晶片偏移堆疊結構％之間係由一黏著層2 料。很明顯地，此黏著層230係貼附於晶片之背面上，如第2圖所干材 另外，此黏者層230也可以選擇配置在導線架6〇〇之第一内引腳群罐 之上表面61卜絲與多晶片偏移堆疊結構5()連接。除此之外在 ==T6GG之第—㈣腳群舰與多㈣移堆疊結構 之間的接合方式，也可以選擇使用膠帶來做為連接材料，特別是一 具有黏著性之膠帶（die attached film)。 在完成導線架_與多晶片偏移堆疊結構％的接合後隨即進行金 導線的連接。首先，金屬導線係以打線製程將金屬導線咖的一端 連接於晶片麻之焊塾，例如前述第3圖中第一焊墊仙或第墊 344 ’而金麟線⑽之另—端則連接於晶片獅之第—焊㈣ -焊塾344上，接著金屬導線64〇b之一端係連接於晶片篇之第—焊 皿或第三雜344，而金屬導線祕之另一端則連接於第—内⑽ 610A之上表面611上；接著，將導線架㈣反轉18〇度使得内 _的下表面612朝上，然後將多晶片偏移堆疊結構％與第一内弓|腳= 18 1333271 610A之下表面612固接，緊接著，進行金屬導線64〇的連接製程，金屬 導線640c的一端係連接於晶片5〇〇c之焊墊，例如前述第3圖中第一焊墊 312a或第二焊墊344 ’而金屬導線64〇c之另一端則連接於晶片5〇〇d之第 一焊墊312a或第三焊墊344上；接著金屬導線64〇d之一端係連接於晶片 500c之第焊塾312a或第三焊塾344,而金屬導線640d之另一端則連接 於第二内引腳群61GB之下表面612之上。如此—來，經由金屬導線64此、 640b、640c及640D等逐層完成連接後，便可以將晶片5〇〇a、5〇%、5〇〇c 及500d紐連接於導線架6⑽之第一内引聊群6說及第二内引腳群 610B，其中這些金料線64G的材f可以錢金。最後，再將完成電性 連接之多⑸偏移堆疊封裝結構以—封裝賴覆蓋於多晶片偏移堆 疊結構50及導線架_之平台部613之上，並且將導線架㈣之外引腳 650曝路在封裝膠體·之外，即可形成堆疊式晶片封裝結構。 此外，形成本實施例之方式，除了上述之難外，也可以選擇在 晶片偏移堆疊結構50分別與第一内引腳群6腿的上表面6ιι及下表面 犯完成固接後’先進行晶片5〇〇a、屬的金屬導線電性連接製程秋 後再進行“麻、細的金屬導線f性連接製程。對此，本、 加以限制。另外，多晶片偏移堆疊結構5〇與内引卿群6i〇的連接 騎示，軸—個上谓歡多晶Μ姆疊封裝結構。’ =5圖所示，其與第Η圖之間的主要差異處為：晶片承座62鼻 19 1333271 ==;二：包括電源接點、接地接點或訊_ 旦由以上之說明，本發明中所述之實施例並未限制堆疊晶片的數 量，凡熟知此項技藝者應可依據上述所揭露之方法，而製作出具有兩個以 上之晶片的堆封⑼縣結構。峰在第H W及第U _實施例中 的多晶>{偏移堆疊結構5G也可換成多晶片偏移堆疊結構％或是多晶片偏 移堆疊結構70。由於這多晶片偏移堆疊結構3〇、多晶片偏移堆疊結構兄 及多^ _靴轉70在抓_ _接合後的金解_接以及封 膝之過程均相同，因此不再贅述。 綜上所述，本發明所提出之晶片結構除了可以是在前段製程中’就 將晶片^複數個焊墊配置於晶片之—側邊之外，還财包括$ 一方式， 其主要疋軸適當的焊線接合區的賴重配置線路層，將第—谭塾與 第二;^塾集巾於晶片結構之單—側邊，使得晶片結構適於經由焊線接合區 以外的區域直接承載其他晶片結構。因此，經由上述晶片結構堆疊而成之 堆疊式晶片封裝結構’相較於習知技術而言，便能夠具有較薄的厚度，以 及具有較高的封裝積集度。 又 顯然地’錢上©實關巾的贿，本發明可能有許多的修正與差 異。因此需要在其附加的權利要求項之範圍内加以理解，除了上述詳細的 描述外，本發明還可以廣泛地在其他的實施财施行吐述料本發:之 較佳實施例而已，並非用以限定本發明之申請專利細；凡其它未脫離本 發明所揭紅精神谓完·較改變或舞，均聽含在下述巾請專利 【圖式簡單說明】 20 1333271 第1A圖 係一先前技術之剖視圖； · 第1B圖 另一先前技術之剖視圖； 第1C圖 另一先前技術之剖視圖； 第2A圖 係本發明之晶片結構之上視圖； 第2B圖 係本發明之晶片結構之剖視圖； 第2C圖 係本發明之多晶片偏移堆疊結構之剖視圖； 第3A-C圖 係本發明之重配置層製造過程之示意圖； 第4A〜B圖 係本發明之重配置層中之焊線接合區之剖視圖； 第5A圖 圖， 係本發明之具有重配置層之多晶片偏移堆疊結構之剖視 第5B圖 施例剖視圖； 係本發明之具有重配置層之多；偏移堆疊結構之另一實 第6圖 第7圖 例剖視圖； 係本發明之具有上下_之多晶片偏_疊結構之剖視圖； 係本發明之具有上下對稱之多晶片偏㈣疊結構之另—實施 第8圖 例剖視圖； 係本發明之具有上下對稱之多晶片偏轉疊結構之另—實施 第9圖 例剖視圖； 係本發明之具有上下對稱之多晶片偏师疊結構之再-實施 第10圖 係本發明之具有匯流架且具有 疊結構之剖視圖’另一實施例剖視圖； 上下對稱之多晶片偏移堆 21 1333271 $ π圖 係本發明之具有匯流架且具有上下對稱之多晶片偏移堆 疊結構之另一實施例剖視圖； 圖 係本發明之具有匯流架且具有上下對稱之多晶片偏移堆 疊結構之再一實施例剖視圖。 第13圖 係本發明之具有匯流架且具有上下對稱之多晶片偏 疊結構之剖視圖； 第14圖 係、本發明之具有上下對稱之多晶片偏移堆疊結構之另一 實施例剖視圖； 第15圖 實施例剖視圖 係本發明之具有上下對稱之多晶片偏移堆疊結構之再— 下對稱之多晶片偏移堆 第16圖 係本發明之具有匯流架且具有上 疊結構之再一實施例剖視圖。 【主要元件符號說明】 2、3、4:半導體元件 5 : 導線架引線 5a: 導線架内引腳部 5b:導線架外引腳 5c:導線架平台部 7、8、9 :電極 1〇、11、12 :金屬導線 200(a，b，c，d).晶片 21〇 :晶片主動面 220:晶片背面 22 1333271 230 :黏著層 240 :焊墊 250 ： 焊線接合區 260 ： 焊線接合區邊緣線 30 :多晶片偏移堆疊結構 310 :晶片本體 312a :第一焊墊 312b :第二焊墊 320 ： 焊線接合區 322 ： 焊線接合區邊緣線 330 ： 第一保護層 332 ： 第一開口 340 ： 重配置線路層 344 ： 第三焊墊 350 ： 第二保護層 352 ： 第二開口 300 ： 晶片結構 400 ： 重配置導線層 50 ： 多晶片偏移堆疊結構 500(a,b，c，d):晶片 600 :導線架 610 ： 内引腳 610A :第一内引腳群 610B :第二内引腳群 611 ： 内引腳之上表面 612 ： 内引腳之下表面 23 1333271 613:平台部 614 :連接部 620 :晶片承座 621 :晶片承座之上表面 622 :晶片承座之下表面 630 :匯流架 640(a〜e):金屬導線 650 :外引腳 70:多晶片偏移堆疊結構 700 :封膠體In the embodiment of the UnZ丨ί heap green structure, the difference is that the metal pad is connected to the fried pad. For example, when the multi-wafer stack structure is processed, the metal wire is connected to the crystal. On the Keyang 344, as shown in Figure 4 and Figure 4. In the embodiment described above, the upper and lower mold flow can be balanced due to the multi-wafer offset stacked package structure and the upper (9)# binding injection; and the metal wire 640a = gold, the wire secret and the metal The wire and her metal wire braid are also symmetrical, so that the length and curvature of each of the four metal wires in the four stacks are connected to the lead frame. In addition, in the present embodiment, the bonding method of the wafer holder gamma of the lead frame and the S of the offset stacking structure may be selected as the connecting material, in particular, a double-sided adhesive tape ( Die attached film ). In addition, the manner in which the metal lead 640 is connected to the lead frame _ and the multi-wafer offset stack structure 5' can be selected in stages except for the above process, for example, the multi-wafer partiality of the upper surface 621 of the wafer holder 20 is completed. After the bonding of the stacked structure, the wafer is twisted and electrically connected to the metal wire of the wafer 2, and then, after the bonding of the multi-wafer offset stack of the surface 622 of the wafer holder 62 is completed, The process of electrically connecting the metal wires of the wafer to the wafer is carried out, and thus the package structure of the multi-wafer offset stack having the upper and lower layers is also available. Through the above description, the embodiment described in the present invention does not limit the number of stacked wafers 2 or wafers 500. Those skilled in the art should be able to make more than two biases according to the methods disclosed above. Move the stacked package structure. At the same time, the multi-wafer offset stack structure 3G in this embodiment can also be replaced by a multi-wafer offset stack turn % as shown in FIG. 7 or formed by stacking a crystal 15 1333271 sheet 200 and a wafer 5 stack. Multi-wafer offset stack structure 7〇. Since the two multi-wafer offset stack structures 30 and the multi-wafer offset stack structure 7 are the same in the metal wire connection process after bonding with the lead frame, they will not be described again. Please refer to FIG. 8 and FIG. 9 for a cross-sectional view of another embodiment of the multi-wafer offset stacked package structure of the present invention. In the present embodiment, the lead frame 6 is composed of a plurality of oppositely arranged inner leads 610 and a wafer holder 62 (), wherein the wafer holder 62 is located in a plurality of opposite rows (four) feet 61G. And the oil pin 61Q forms a height difference; when the wafer holder 620 forms a lower (d〇wn-set) height difference between the plurality of oppositely arranged inner pins 61〇, it is different from the multi-wafer Move the stack structure 5〇 to complete the package structure cross-section circle, as shown in Figure 8. Since the packaging process of the lead frame 600 having the lower wafer holder 62 is the same as that shown in FIGS. 6 and 7, the process of forming the multi-wafer offset stacked package structure having the upper and lower symmetry is not described in detail. . In addition, when an upper (up_set) height difference is formed between the wafer holder 62〇 and the plurality of oppositely arranged inner leads 610, the package structure is completed with the multi-wafer offset stack structure 50, such as Figure 9 shows. Since the packaging process of the lead frame 6 with the lower wafer holder 620 is also the same as that shown in FIGS. 6 and 7, it is a process of forming a multi-wafer offset stacked package structure with upper and lower symmetry. No further details will be given. Next, please refer to FIG. 10, which is a cross-sectional view showing still another embodiment of the multi-wafer offset stacked package structure of the present invention. As shown in FIG. 10, the lead frame 600 in this embodiment is composed of a plurality of oppositely arranged inner leads 610, a bus bar 630, and a wafer holder 62, wherein the wafer holder 620 is located in a plurality of The opposite arrangement is between the pins 61〇, and the bus bar 630 is located between the wafer holder 62〇 and a plurality of oppositely arranged inner pins 61〇. It should be emphasized that in this embodiment, the wafer holder 620 and the bus bar 63 形成 form a coplanar plane with the inner lead (10), and the inner lead 610 has an upper surface 611 and a lower surface 612, and the wafer bearing Seat 620 also has an upper surface 621 and a lower surface 622. Obviously, the difference between the present embodiment and the above-mentioned FIG. 6 and FIG. 7 'the eighth figure and the ninth figure is that the lead frame 600 of the embodiment 16 1333271 is further configured with at least one pass. The flow frame 63 is configured with a bus bar 630 which can be electrically connected as a power contact, a ground contact or a signal contact. Since the encapsulation process of the lead frame 600 having the bus bar 630 is the same as that of the sixth and seventh drawings, the engraving of the polypyramid #offset stack structure having the _LT heterogeneous structure will not be described in detail. In addition, in the present embodiment, the lead frame 63 of the lead frame can also be formed at different heights between the wafer holder 620 and the plurality of oppositely arranged 5 feet (10), for example, in the wafer holder 620. On one side of the upper surface 621, the bus bar 63 is an upper structure, and on the side of the lower surface 622 of the wafer holder 620, its confluence frame 63 is an underlying structure such as the 7JV ° of the nth figure. Other embodiments of the present invention having a bus bar 630 further include forming a height difference between the wafer carrier 620 in the lead frame _ and the plurality of oppositely disposed inner pins 61 ,, for example, when the wafer holder 620 is A lower (d〇Wn-set) height difference is formed between the plurality of oppositely arranged inner pins 61〇, and a common-plane is formed between the bus bar 63〇 and the plurality of oppositely arranged inner pins 6ι〇 The package structure cross-section of the upper and lower multi-chip offset stack structure 5G is as shown in FIG. Since the packaging process of the lead frame 6 具有 having the bus bar 63 〇 and the lower wafer holder 620 is the same as that shown in FIGS. 6 and 7 , it forms a multi-wafer offset stacked package structure having upper and lower symmetry. The process is not described in detail. In addition, when the wafer holder 62 is formed with a plurality of oppositely arranged inner pins 610, a height difference is formed, and the height of the bus bar 630 is located within a plurality of opposite rows. When the crucible is between the wafer holder 62 and the wafer holder 62, the stack structure 50 is offset from the upper and lower wafers to complete the package structure, as shown in FIG. Since the packaging process of the lead frame 600 having the bus bar 630 and the lower wafer holder 62 is also the same as that shown in FIGS. 6 and 7, the process of forming a multi-wafer offset stacked package structure having upper and lower symmetry is formed. No further details will be given. Next, please refer to Fig. 14, which is a cross-sectional view showing still another embodiment of the multi-wafer offset stacked package structure of the present invention. As shown in Fig. 14, the lead frame 6 in the present embodiment is swayed by a thinner, wherein the inner lead group 61 includes a plurality of parallel and has an upper surface 611 and a lower surface. Formed with the second (four) foot B, and the first inner pin group 61 (^ cited = the foot group is separated by a gap - the first inner pin group 嶋 bow foot group is borrowed Formed by a platform portion 613 and the connected connecting portion 614 having an underlying structure, such that the first (four) leg group can and the second (four) leg group are formed as shown in FIG. 14 in addition, the shape of the connecting portion 614 of the present invention. It is also important to emphasize that the platform part 613 and the connecting line! 4 can also sigh part of the first or second post. Please continue to refer to Figure 14. It is shown that the surface of the lead-frame of the lead frame _ is caused by an adhesive layer between the surface of the multi-wafer offset stack and the % of the multi-wafer offset stack. Obviously, the adhesive layer 230 is attached to the back of the wafer. In addition, as shown in FIG. 2, the adhesive layer 230 may also be disposed on the upper surface of the first inner lead group can of the lead frame 6 The wire is connected to the multi-wafer offset stack structure 5(). In addition to the joint between the (=) foot group ship and the multi-(four) shift stack structure, the tape can also be selected as the connecting material. , in particular, a die attached film. After the completion of the bonding of the lead frame _ to the multi-wafer offset stack structure, the gold wire is connected. First, the metal wire is made by a wire bonding process. One end is connected to the soldering pad of the wafer, for example, the first pad or the pad 344 ' in the foregoing figure 3 and the other end of the Jinlin line (10) is connected to the first part of the wafer lion - the welding (four) - the pad 344 Then, one end of the metal wire 64〇b is connected to the first electrode of the wafer piece—the third dish 344, and the other end of the metal wire is connected to the upper surface 611 of the first inner (10) 610A; then, the wire is connected The frame (four) is reversed by 18 degrees so that the lower surface 612 of the inner side faces upward, and then the multi-wafer offset stack structure % is fixed to the lower surface 612 of the first inner bow|foot = 18 1333271 610A, and then the metal wire is made. 64-inch connection process, one end of metal wire 640c a pad connected to the chip 5〇〇c, such as the first pad 312a or the second pad 344' in the foregoing FIG. 3, and the other end of the metal wire 64〇c is connected to the first pad of the wafer 5〇〇d Pad 312a or third pad 344; then one end of the metal wire 64〇d is connected to the first pad 312a or the third pad 344 of the wafer 500c, and the other end of the metal wire 640d is connected to the second inner pin The group is 61GB below the surface 612. Thus, after the metal wires 64, 640b, 640c, and 640D are connected layer by layer, the wafers 5〇〇a, 5〇%, 5〇〇c, and 500d can be used. The first inner chat group 6 connected to the lead frame 6 (10) and the second inner lead group 610B, wherein the material f of the gold feed line 64G can be used for money. Finally, the plurality of (5) offset stacked package structures that complete the electrical connection are overlaid on the platform portion 613 of the multi-wafer offset stack structure 50 and the lead frame _, and the lead 650 outside the lead frame (four) The exposed wafer is packaged outside the encapsulant. In addition, in the manner of forming the embodiment, in addition to the above difficulties, the wafer offset stacking structure 50 may be selected to be fixed after the upper surface 6 ι and the lower surface of the first inner lead group 6 are respectively fixed. The wafer 5〇〇a, the metal wire of the genus is electrically connected to the process, and then the “hemp and fine metal wire f-connection process is carried out in the autumn. This is limited by this. In addition, the multi-wafer offset stack structure is 5〇 and The connection of the 6i〇 group of the Yinqing group is shown in the figure. The axis is a polycrystalline Μm stack package structure. '=5, the main difference between it and the figure is: wafer holder 62 nose 19 1333271 ==; 2: including power contacts, ground contacts or signals. From the above description, the embodiments described in the present invention do not limit the number of stacked wafers, and those skilled in the art should be able to The disclosed method is to fabricate a stacked (9) county structure having two or more wafers. The peaks in the HW and the U_th embodiment are polycrystalline>{the offset stack structure 5G can also be replaced by a multi-wafer offset. Stack structure % or multi-wafer offset stack structure 70. Due to this multi-wafer bias The stacking structure 3〇, the multi-wafer offset stacking structure brother and the multi-shoe turn 70 are the same in the process of the gold solution_connection and the sealing of the knee after the grab__ joint, and therefore will not be described again. The wafer structure proposed by the invention can be arranged in the front-end process to arrange the plurality of solder pads of the wafer on the side of the wafer, and further includes a method, which is mainly for the appropriate wire bond area of the wire. Relying on the wiring layer, the first layer and the second side are disposed on the single side of the wafer structure, so that the wafer structure is adapted to directly carry other wafer structures via regions other than the bonding wire bonding region. The stacked wafer package structure of the above wafer structure can have a thinner thickness and a higher degree of package integration than the prior art. There are many modifications and differences to the present invention, and it is intended to be understood within the scope of the appended claims. In addition to the detailed description above, the present invention can be widely practiced in other embodiments. The preferred embodiment of the present invention is not intended to limit the scope of the patent application of the present invention; any other invention that does not deviate from the spirit of the present invention is more than a change or dance, and is included in the following patents. Description: 20 1333271 FIG. 1A is a cross-sectional view of a prior art; FIG. 1B is a cross-sectional view of another prior art; FIG. 1C is a cross-sectional view of another prior art; FIG. 2A is a top view of the wafer structure of the present invention; Figure 2 is a cross-sectional view of the multi-wafer offset stack structure of the present invention; Figure 3A-C is a schematic view of the fabrication process of the re-configuration layer of the present invention; Figure 4A-B is a diagram A cross-sectional view of a wire bond area in a reconfigured layer of the invention; FIG. 5A is a cross-sectional view of a cross-sectional view of a multi-wafer offset stack structure having a reconfigured layer of the present invention; A cross-sectional view of another embodiment of the offset stack structure; FIG. 7 is a cross-sectional view of the multi-wafer partial-stack structure of the present invention; A multi-wafer partial (four) stack structure is another embodiment of the present invention; a cross-sectional view of the ninth embodiment of the multi-wafer deflecting stack structure of the present invention; the multi-wafer polarized stack structure having the upper and lower symmetry of the present invention Figure 10 is a cross-sectional view of another embodiment of the present invention having a busbar and having a stacked structure. A multi-wafer offset stack of up and down symmetry 21 1333271 $ π is a busbar having the upper and lower sides of the present invention A cross-sectional view of another embodiment of a symmetrical multi-wafer offset stack structure; FIG. 1 is a cross-sectional view of still another embodiment of a multi-wafer offset stack structure having a bus bar and having upper and lower symmetry. Figure 13 is a cross-sectional view showing a multi-wafer offset structure having a bus bar of the present invention and having upper and lower symmetry; Fig. 14 is a cross-sectional view showing another embodiment of the multi-wafer offset stack structure having upper and lower symmetry of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 16 is a cross-sectional view of a multi-wafer offset stack having a vertically symmetrical multi-wafer offset stack structure according to the present invention. FIG. 16 is a cross-sectional view showing still another embodiment of the present invention having a bus bar and having an upper stack structure. . [Description of main component symbols] 2, 3, 4: Semiconductor component 5: Lead frame lead 5a: Lead frame inside lead frame 5b: Lead frame outer lead 5c: Lead frame platform part 7, 8, 9: Electrode 1〇, 11, 12: metal wire 200 (a, b, c, d). wafer 21 〇: wafer active surface 220: wafer back surface 22 1333271 230: adhesive layer 240: pad 250: wire bond area 260: wire bond area Edge line 30: multi-wafer offset stack structure 310: wafer body 312a: first pad 312b: second pad 320: wire bond region 322: wire bond region edge line 330: first protective layer 332: first Opening 340: reconfigured wiring layer 344: third bonding pad 350: second protective layer 352: second opening 300: wafer structure 400: reconfigured wiring layer 50: multi-wafer offset stacked structure 500 (a, b, c, d): Wafer 600: lead frame 610: inner pin 610A: first inner pin group 610B: second inner pin group 611: inner pin upper surface 612: inner pin lower surface 23 1333271 613: platform Portion 614: connection portion 620: wafer holder 621: upper surface of the wafer holder 622: wafer carrier lower surface 630: busbar 640 (a ~ e): metal wire 650: outer pin 70: multi-wafer offset stack structure 700: sealant