TW200837919A - Offset stacked chip package structure with vertical balance - Google Patents

Abstract

The present invention provides an offset stacked chip package structure with vertical balance. The offset stacked chip package structure comprises: a lead-frame composed of a plurality of groups of inner leads in opposite arrangement and a die paddle disposed among the plurality of groups of inner leads in opposite arrangement, the groups of inner leads and the die paddle each having an upper surface and a lower surface; a first offset stacked chip package structure composed of a plurality of offset stacked chips and fixedly connected to the upper surface of said die paddle, an active surface of each chip in the first offset stacked chip package structure being disposed with a plurality of pads; a second offset stacked chip package structure composed of a plurality of offset stacked chips and fixedly connected to the lower surface of the die paddle, a side of an active surface of each chip in the second offset stacked chip package structure being disposed with a plurality of pads; a plurality of first metallic leads electrically connecting the plurality of pads of first offset stacked chip package structure with the upper surface of the groups of inner leads of the lead-frame from one side; a plurality of second metallic leads electrically connecting the plurality of pads of second offset stacked chip package structure with the lower surface of the groups of inner leads on the other side of lead-frame from the other side; and an encapsulant to encapsulate the first offset stacked chip package structure, the second offset stacked chip package structure, the groups of inner leads, and the die paddle and to expose the outer leads.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer stacked package structure, and more particularly to a multi-wafer offset stacked package structure in which a wafer holder is formed to be vertically symmetrical. [Prior Art] In recent years, the semiconductor back-end process has been packaged in a three-dimensional space (ThreeDimenskm; 3D) in order to achieve a higher density or a memory capacity with a minimum area. In order to achieve this goal, the use of chip stacking has been developed at this stage to achieve a second-degree space; In the prior art, the stacking of wafers is performed by stacking a plurality of wafers on a substrate, and then wiring a plurality of wafers to the substrate using a wire bonding process. FIG. 1A discloses a structure of a wafer stack package based on a lead frame. As shown in FIG. 1A, the lead frame 5 can be divided into an inner lead portion 5a, an outer lead portion 5b, and a platform portion 5c, wherein the platform The portion 5e and the (4) leg portion 5a and the outer lead portion % have a height difference. The first three chips stack S is on the lead 5a of the lead frame 5, and then the metal wires 1〇, u, 12 are used to connect the pads 7, 8, 9 on the three pieces to the platform of the lead frame 5. And then, the molding proeess are used to close the three stacked wafers and the lead brothers of the lead frame 5 and the part of the platform portion 5〇, but the exposed outer portion is exposed as a connection. Pins for other interfaces. In addition, the structure of a wafer stack package is also disclosed in FIG. 1B and FIG. 1c. The difference from FIG. 1A is mainly based on a circuit board (pcB), so that after the stacked wafer is connected to the circuit board, It can be connected to an external circuit via a solder ball (SolderBall). In the above-mentioned conventional wafer stack package structure, in addition to the offset between the wafers, the unevenness of the mold flow is not uniform when the injection molding is performed; and the metal guide between the wafers is 6200837919: FIG. 1A In the 10, 11, 12 or 62 in the 1C figure, the difference between each degree and the degree of curvature is not the same, so in addition to the length and the degree of lolence during the sealing process, the wire is easily displaced to the wafer. In addition to the short circuit, the phase of the electrical signal will change due to the different lengths of the metal wires (4). SUMMARY OF THE INVENTION The invention has the disadvantages and problems of the multi-wafer stacking method described in the invention of the moon, and the present invention provides

For the purpose of shifting the stack of the shirt wafers, the plurality of wafers having similar dimensions are stacked in a symmetrical manner to form a three-dimensional space-packing structure. The main purpose of t-month is to provide a multi-wafer offset stacked package structure with upper and lower symmetry, so that it has a high-profile "four" thickness. Another object of the present invention is to provide a multi-wafer offset stacked package structure having upper and lower symmetry, so that the length and the arc of each of the metal wires in the stacked structure are connected to the lead frame. A multi-wafer offset stacked package structure with upper and lower symmetry enables the upper and lower mold streams to be balanced. There is also a purpose of providing a multi-wafer offset stacking package with upper and lower symmetry. It can be equipped with a flow carrier in the transfer frame, so that the multi-(9) offset stacked package structure is better. The flexibility of the circuit application. Accordingly, the present invention provides a multi-wafer offset stacked package structure having upper and lower symmetry, wherein the package is located in a plurality of rows of opposite rows (four) and a wafer carrier. a plurality of oppositely arranged inner pin groups, and the inner lead group and the wafer carrier f each have an upper surface and a lower surface; a second wafer offset stacked structure formed by stacking a plurality of wafers offset Connected to the upper surface of the wafer holder, and a plurality of pads are disposed on each side of the first-wafer offset stacking structure; and a plurality of wafers are offset from the stack a second multi-wafer offset stack structure, fixed to the lower surface of the cymbal holder' and a plurality of pads disposed on one side of each active surface of the second multi-wafer offset stack The plurality of first metal wires electrically connect the plurality of pads of the first multi-chip offset stack structure to the upper surface of the lead group of the lead frame by one side; and the plurality of second metal wires are further- The side of the second multi-wafer offsets the plurality of solder bumps of the stacked structure The surface of the wire frame is electrically connected under the other lead group; and the _ a sealant is used to cover the 第 a 偏移 偏移 offset stack structure, the second multi-chip offset stack structure, the inner lead group and the wafer bearing Block and expose the outer pins. Θθ

The present invention further provides a multi-wafer offset stacked package structure having upper and lower symmetry, comprising: a lead frame composed of a plurality of oppositely arranged (four) leg groups, a turbulent flow frame and a wafer holder, and a crystal holder The plurality of pairs are arranged in a relatively aligned inner pin group, and the inner pins=sheet holders each have an upper surface and a lower surface, and the _flow frame is disposed between the (four) foot group disk crystals and is offset by a plurality of wafers The stacked _ multi-wafer offset stack structure is fixed on the upper surface of the wafer holder, and each wafer in the first-multi-wafer offset stack structure

surface? A plurality of pads are disposed; one is stacked by a plurality of wafers and the structure is fixed to the lower surface of the wafer holder, and the second plurality of mothers are disposed on the surface of the wafer, and a plurality of pads are disposed on the woman The upper surface of the side is electrically connected; and the plurality of second metal wires are represented by another group: the following: shift: configuration, second multi (10) nanostructure, ___== [embodiment] 8 200837919 The present invention is here The direction of the discussion is to use a wafer offset stack (four) method to stack a plurality of wafers with similar dimensions into a three-dimensional space package structure. ^ A thorough understanding of the present invention will be detailed in the following The step of the county's structure. - Apparently, the special details of the skill of the present invention. The detailed steps of the other aspects of the wafer formation method and the wafer thinning process are not described in the details, in order to avoid causing this (four) unnecessary _ n for the good example of the stick will be described in detail as follows. Further, in addition to these detailed descriptions, the present invention can also be described in the context of the present invention, and the side details of the present invention will be subject to the scope of the patent application. In the modern semi-guided bribery, all H wafers that have been reduced in the front-end process (4) are thinned (5) She (4) (4) Grind the thickness of the wafer to between 2 and 20 mils' Then, Recoating (4) (4) or screen printing (4) nti (10) a layer of polymer (4) (4) material on the back side of the wafer, the polymer material may be one side of the month (4) e), especially - Β-Stage resin. Then, through a baking illuminating process, the polymer material exhibits a viscous half-g) gel; and then, a removable tape (the shovel is attached to the semi-cured polymer material) Then, the wafer is cut (four), and the wafer is made into a single wafer (here); finally, the individual wafers are connected to the substrate and the wafer is formed into a stacked wafer structure. Referring to Figures 2A and 2B, it is a schematic plan view and a cross-sectional view of the wafer 2 of the above process. As shown in FIG. 2B, the wafer has an active surface 21〇 and a back surface 22〇 opposite to the active surface, and an adhesive layer 23() has been formed on the back surface 22 of the wafer; The adhesive layer 230 is not limited to the aforementioned semi-cured adhesive. The adhesive layer is now formed to be bonded to the grade or the crystal. Therefore, as long as the adhesive material of the present invention is used, the embodiment of the present invention is For example: glue away from e coffee (four) mm). Further, the adhesive layer 23 of the present invention may be formed of a material having an insulating function. 9 200837919 Next, please refer to Section 2c ® for a cross-sectional view of the completed multi-wafer offset stack structure of the present invention. As shown in FIG. 2C, a plurality of solder " pads 240' are disposed on the active surface 21 of the wafer, and a plurality of pads 240 are disposed on the same side of the wafer 200. After the adhesive layer 23 is offset (OFFSET) with the active surface 21G of the other wafer 2GG, a multi-wafer offset stack structure 3 is formed, wherein the multi-wafer offset stacked structure 30 is bonded by wire bonding. The edge line 26〇 of the region 25〇 is formed as a reference alignment reference, so that a step-like multi-wafer offset stack structure 3〇 can be formed, and it is obvious that the edge line 260 is actually absent. Above, it serves only as a reference line. Here, it should be emphasized that the adhesive layer 23G of the present embodiment is not limited to the aforementioned semi-cured adhesive. The purpose of the adhesive layer 230 is to form a bonding with the substrate or the wafer, and therefore, as long as it is an adhesive material having such a function. 'Either the solid silk of the present invention. At the same time, the number of stacks is not limited, for example, the offset stack structure formed by two or a plurality of wafers 200 is in the embodiment of the present invention. In another embodiment of the polymorphic shift stack, the present invention uses a reconfiguration layer (4) disMbuticmLayer; RDL) to dispose the pads of each wafer on the wafer to the two sides of the wafer so as to form more The wafer is offset from the stacked structure, and the implementation of this reconfiguration layer is as follows. Please refer to Figs. 3A to 3C, which are schematic views showing the manufacturing process of the wafer structure having the reconfiguration layer of the present invention. As shown in FIG. 3A, the wafer body is first provided, and the bonding wire bonding region 32 is planned adjacent to the side of the wafer body 310, and the plurality of bonding pads 312 on the active surface of the wafer body 31 are distinguished. The first pad 312a and the second pad 312b are in which the first pad 312a is located in the wire bonding area 32A, and the second pad 312b is located outside the wire bonding area 320. Referring to FIG. 3B, a first protective layer 33A is formed on the wafer body 31, wherein the first protective layer 330 has a plurality of first openings 332 to expose the first pads 312 & and the second pads 312b. . Then, a reconfiguration wiring layer 34 is formed on the first protective layer 33. The reconfigurable 200837919 circuit layer 340 includes a plurality of wires 3 and a plurality of third pads 344, wherein the third pads 344 are located in the wire bonding regions 32, and the wires 342 are respectively from the second pads. The second soldering 344 is extended to the third soldering pad 344 to electrically connect the second bonding pad 312b to the third bonding pad 344. In addition, the material of the reconfiguration circuit layer 340 may be gold, copper, nickel, titanium, crane, or other conductive materials. Referring again to FIG. 3C, after forming the reconfiguration wiring layer, the second protective layer 35 is formed. The germanium is overlaid on the reconfigurable wiring layer 34 to form a wafer structure, wherein the second protective layer has a plurality of second openings 352 to expose the first pad 312a and the third pad 344. ▲ It should be emphasized that although the first solder fillet 312a and the second solder fillet are arranged in a surrounding pattern on the active surface of the wafer body 31G, the first solder fillet 31 and the second solder fillet 313⁄4 may also be It is arranged on the wafer body 310 via a surface array type or other types. Of course, the second solder joint is electrically connected to the third solder bump 344 via the wire 342. In addition, the embodiment does not limit the arrangement of the third pads 344, although the third pad 344 and the pad 312a are arranged in two rows, and the single-side along the wafer body. Arranged, but the third pad 344 and the first pad may also be arranged in the wire bonding region 320 in a single row, a plurality of columns or in other manners. Please refer to Fig. 4A and Fig. 4B for a cross-sectional view taken along line C-B and B-B, respectively. As shown in FIG. 4A and FIG. 4B, it is known from the above diagram that the wafer structure 3GG mainly includes a wafer body and a reconfiguration layer, wherein the relocation layer 400 is composed of a first protective layer 33 and a reconfigured circuit layer. 34〇 is formed with the second protective layer. The wafer body 310 has a wire bond area 32A, and the wire bond area 32 is adjacent to the single-side of the wafer body 310. In addition, the wafer body 31A has a plurality of first solder dies and a second solder pad 312b' wherein the first solder pads are located in the bonding wire bonding regions 32, and the second solder pads 312b are located outside the bonding wire bonding regions 32. . The first protective layer 330 is disposed on the wafer body 31, wherein the first protective layer 33 has a plurality of first-opening π 332 ' to expose the first pads 3 to be adjacent to the second pads. The reconfigurable 200837919 circuit layer 340 is disposed on the first protective layer 330, wherein the reconfigurable circuit layer extends from the second pad 312b into the bonding wire bonding region 32, and the reconfigurating circuit layer 34 has a plurality of third tamers The pad 344' is disposed in the wire bonding area 32〇0. The second protective layer 35 is overlaid on the reconfiguration wiring layer 340' wherein the first protective layer 35q has a plurality of second openings to expose the first and second pads 312a, 344. Since the first pad welcomes the third pad 344 away from the wire bonding area 320, the area other than the bonding wire bonding area 32 of the second protective layer 35 is sufficient to provide a supporting platform for carrying Another wafer structure, therefore, can form a multi-wafer offset stack structure.

Next, please refer to the fifth _ 'section of the multi-wafer offset stack structure of the present invention: as shown in FIG. 5, the multi-offset stack structure % is composed of two or more wafers In the case of a reconfigured layer on the wafer, the solder bumps on the wafer (ie, 3 or 344) can be placed on the bond wire bonding area 32〇 of the wafer, so the multi-wafer is biased. The shift stack structure 5 is formed with the edge lines 322 of the bond wire bonding regions 32 () as alignment lines. The plurality of wafers 500 are connected by an adhesive layer 23〇. First, the adhesive layer 230 of the wafer (10) is located on the back side of the crystal, and the formation of the adhesive layer 23 is performed simultaneously with the wafer as shown in Fig. 2B. Since the relocation layer 400 is disposed on the active surface of the wafer, the pads on the wafer can be disposed on the bonding pads of the wafer. Therefore, the adhesive layer on the back surface of the wafer can be reconfigured with another wafer.进行 After the offset_kiss bond is formed, a multi-wafer offset stack structure is formed, and the structure of the multi-wafer offset stack in the pot is formed by the edge line milk of the wire bond area. Therefore, a step-like multi-wafer offset stack structure or a wafer offset stack structure 70 (stacked from one wafer 2 〇〇 and one wafer stack) can be formed as shown in FIG. 5A or FIG. 5B. Next, the present invention further proposes a suitable chip package structure according to the above-described multi-wafer offset stack structure 3 and %, and in detail as follows, in the following description, 12 200837919 will be a multi-wafer offset stack structure 50 For example, it is emphasized that the multi-wafer offset stack is also covered by the structure 30 and the multi-wafer offset stack structure.

^, please refer to Fig. 6 ' is a cross-sectional view of the multi-crystal lion stack with the upper and lower symmetry of the present invention, as shown in Fig. 6, _ _ is composed of a plurality of relative arrangement and - The wafer holder (4) is composed of a wafer holder 62 〇 between a plurality of oppositely arranged inner bows. It should be emphasized that in the present embodiment, the wafer _620 forms a coplanar plane with the inner leads 610, and the inner leads _ have an upper surface 611 and a lower surface 612, and the wafer 62 〇 also has an upper surface. Surface 621 and a lower surface 622. Next, a wafer is heard on the upper surface (2) of the wafer holder 62, and the bonding between the wafer 200a and the upper surface of the wafer holder 62 is made of an adhesive layer 23 on the back surface of the wafer 2A. 〇 to achieve the effect of the paste. Then, a heating or copying process is performed to cure the adhesive layer 23〇 between the back surface 22 of the wafer and the wafer holder 62〇; then 'add another wafer 2_ to the wafer with an offset An adhesive layer 23 位于 on the back surface 22 of the wafer 2〇〇b is applied to the active surface (10) of the wafer pulse so that the soldering on the active surface 210 can be exposed. Alternatively, the foregoing operations can be selectively repeated to form a plurality of stacked structures 30 of wafers on the upper surface 622 of the wafer holder 62G. Next, the lead frame is reversed by 180 degrees so that the surface of the lower surface 622 of the wafer holder 62 of the lead frame 600 faces upward, and then the previous steps of the present example are performed to bond the wafer 2 (9) to the lower surface 622 of the wafer holder 620. After bonding, and after the baking process, the other wafer 2〇〇d is adhered to the wafer 200c with an offset so that the adhesive layer 230 on the back surface 22 of the wafer 2〇〇c is attached to the wafer. The active surface 21〇 of the 20〇〇1 is so as to expose the solder pad 240 on the active surface 21〇. Next, the foregoing operations can be selectively repeated to form a plurality of stacked structures 30 of wafers on the upper surface 622 of the wafer holder 620. After the above process, an offset stack structure 30 formed by a plurality of wafers has been formed on the upper surface 621 and the lower surface 622 13 200837919 of the wafer holder 62, respectively; obviously, the wafer holder 620 is located. The multi-wafer stack structure 30 of the upper surface 621 and the lower surface 622 is symmetrical to the wafer holder 620, that is, the wafer 200a is aligned with the edge of the wafer 200d, and the wafer 200b is also aligned with the wafer 200c. Of course, if the wafer 200a is selected to be aligned with the edge of the wafer 200c and the wafer 200b is also aligned with the wafer 200d, the overlying symmetrical multi-wafer offset stacked package structure of the present invention can also be formed. Next, wire bonding of the metal wires is performed. First, one end of the metal wire 640a is connected to the pad 240 of the wafer 2A, and then the other end of the metal wire 64A is connected to the pad MO of the chip 200b; and then, the metal wire 64〇b One end is connected to the pad 240 of the wafer 200a, and then the other end of the metal wire 600b is connected to the upper surface 611 of the inner lead 610 on the side of the wafer holder 620. After the lead frame 6 is reversed by 180 degrees, the metal wire connection process of another multi-wafer offset stack structure is continued, that is, the process of repeating the metal wires 640a and 64〇b, with the metal wire 64〇c The wafer 200c is electrically connected to the wafer 2〇〇d; and then, the wafer 2〇〇c is placed on the upper surface 611 of the inner lead 61〇 on the other side of the wafer holder 62 by the metal wire 64〇d. Complete the electrical connection. In this way, after the connection is completed layer by layer through the metal wires 64〇a, 64〇b, 64〇c and 6, the wafers 200a, 200b, 2 and 2_ can be electrically connected to the lead frame _, wherein These metal wires 64G can be made of gold. Finally, the Na-process is covered by a colloid 700 with a vertically symmetrical multi-wafer stack structure 3, a plurality of metal conductors, a wafer holder 620 and an inner pin 610, as shown in FIG. It should be emphasized here that the multi-wafer stack structure in the above process may be a structure in which the multi-wafer stack structure 30 is vertically symmetrical, or it may be a multi-wafer stack structure, and the upper and lower symmetrical package structure, of course. The present invention is not limited by a multi-wafer stack structure such as a multi-wafer stack structure 50. In the embodiment of the different multi-wafer stack structure, the difference is that the 14 200837919 pads to which the metal wires are to be connected are different, for example, when the multi-wafer stack structure is connected to the metal wires 64〇, the metal is kept. The wire 64A is connected to the first pad μ% or the third pad 344 on the wafer 5, as shown in FIGS. 4A and 4B. Obviously, in the above embodiment, since the multi-wafer offset stacked package structure is vertically symmetrical, the lower mold and the flow can be balanced when the glue is injected; and the metal wire _ and the metal wire 6 are connected with the metal wire. The 64 〇c and the metal wire 6 are also symmetrical, so that the length and the arc of each strip metal squama line of the stacked structural towel are approximated. another

In addition, in the embodiment, for the bonding manner between the first crystal holder _ and the multi-wafer offset stacked structure of the lead frame, tape can also be selected as the connecting material, especially a double-sided adhesiveness. Tape (dieattachedfllm). In addition, the manner in which the lead frame and the multi-wafer offset stack structure are connected by the metal wire 640 can be completed in stages, in addition to the above-mentioned materials, for example, the multi-wafer offset of the upper surface 621 of the wafer holder 620 is completed. After the bonding of the stacked structure, the metal wire is electrically connected to the wafer 2_, and then the wafer is bonded to the lower surface of the wafer carrier 622. The metal wire of the thin d of the wafer is electrically connected to the female circuit, and thus the package structure of the upper and lower offset stacks can be formed. Through the above description, the embodiments described in the present invention do not limit the amount of debris of the stacked wafers such as the wafers 500, and the squash scales of the squadrons are said to have a two-folded scaly stacked female structure. The actual folded structure 30 can also be replaced by a multi-wafer offset stack (4) as shown in the first job, or a multi-wafer offset stack structure % formed by stacking the wafer 200 and the wafer 500. Since the multi-wafer offset stack structure 3〇 and the multi-_-stack stack structure 7___ are connected in the same manner, the metal wire connection process is the same, and therefore will not be described again. Please refer to the eighth embodiment, which is a multi-wafer partial stack structure of the present invention. In this embodiment, the lead frame 6 is composed of a plurality of oppositely arranged inner leads 610 and a wafer holder 620, wherein the wafer holder 620 is located in a plurality of phase-like (four) feet. Lay (four) feet _ form a height 纟 'When the wafer holder 620 and a plurality of oppositely arranged inner leads 610 form a wnset N degree difference' with the multi-wafer offset stack structure % complete package structure The section view ' is shown in Figure 8. Since the lead frame 6 has the packaging process of the lower wafer holder 62 and the 6th and 7th shows, the process of forming the package structure with the upper and lower facing offset stacks is not described in the most detailed manner. In addition, when the wafer holder is formed with a plurality of opposing (aligned) pins _ between the upper and lower (four) height differences, the multi-wafer offset stack structure 50 completes the package structure profile, such as Figure 9. Since the sealing process of the lower wafer "620" in this lead frame_ is also the same as that shown in Fig. 6 and Fig. 7, it forms a polycrystalline offset stacking structure with upper and lower symmetry. Next, please refer to FIG. 10, which is a cross-sectional view showing still another embodiment of the multi-wafer offset stacked package structure of the present invention. As shown in FIG. 1, the lead frame in this embodiment _ is composed of a plurality of oppositely arranged inner pins _, a bus bar 63G and a wafer holder 62 ' 'where the wafer holder 62G is located between a plurality of oppositely arranged (four) feet (10), and the production rack 2 It is located between the wafer holder 620 and a plurality of oppositely arranged inner pins (10). In this embodiment, the wafer holder 62 and the bus bar (four) and the inner pin (10) are coplanar. 'And the inner pin 61' has an upper surface from 611 and a lower surface 612, The wafer carrier 620 also has an upper surface 621 and a lower surface 622. It is apparent that the difference between this embodiment and the sixth, seventh, eighth, and ninth drawings is just described. In the lead frame _± of the embodiment, the at least one bus bar (4) is further configured with a bus bar 63〇, which can be used as an electrical connection including a power contact, a ground contact or a signal point. The packaging process with the bus bar 63〇 in 600 is the same as that of FIGS. 6 and 7, so the process of forming a multi-wafer offset stacked package structure having upper and lower symmetry is not described in the most detailed manner. Further, 'in this embodiment' The busbar 600+ of the leadframe 600+ may also be formed at a different height between the wafer holder 620 and the plurality of oppositely disposed inner leads 610, such as on the side of the upper surface 621 of the wafer holder 620. The bus bar 63A is an upper structure, and on the side of the lower surface 622 of the wafer holder 620, the bus bar 630 is a lower structure as shown in Fig. u. As for the present invention, the bus bar 63 is provided. Other embodiments of the crucible include the lead frame 6 A height difference is formed between the wafer holder 620 and a plurality of oppositely arranged inner pins 61, for example, 'when the wafer holder 620 and the plurality of oppositely arranged inner pins 61〇 form a lower portion (adding a marriage) The height difference is formed between the bus bar 63〇 and the plurality of oppositely arranged inner pins 61〇: when it is coplanar, it is more than the upper and lower sides; the offset stack structure 5() completes the package structure sectional view as the 12th As shown in Fig. 6 , the package process of the lead frame _ having the bus bar 63 〇 and the lower wafer holder 620 is the same as that shown in FIGS. 6 and 7 , so that the multi-chip offset stack package having the upper and lower symmetry is formed. The process of the structure is no longer the most detailed. In addition, the #wafer holder 62〇 and the plurality of oppositely arranged inner pins 61〇 form a lower (d〇(8) height difference, and the height of the bus bar 630 is located. A plurality of oppositely arranged inner leads 61 〇 and a wafer holder _ 1 / , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Since the lead frame _ has a busbar 630 and a lower wafer carrier must be packaged = also the same as shown in FIGS. 6 and 7, so the process of forming a multi-wafer offset stacking package structure having upper and lower symmetry No longer the most detailed description. Further, referring to the second drawing, the d-face of the re-implementation of the multi-wafer offset stacked package structure of the present invention is not tolerated. As shown in FIG. 14, the lead frame _ in the present embodiment is composed of a plurality of oppositely arranged inner pin groups (10) and outer pin groups 65A, wherein the inner lead group (10) includes a plurality of parallels and The first inner pin group can having the upper surface 611 and the lower surface 612 is formed by the second inner pin group, and the first inner pin group is followed by the end of the second inner pin group 1GB. Off, at the same time, the - (four) foot group and the second inner pin group are deleted by a platform portion of the anode and the connected connection portion (10) to form a sink 17 200837919 phase (d with the first inner pin group ship and The second inner lead group 6 is unrestricted and can be shown as a graph of the slanting 149. In addition, the present invention has the shape of the connecting portion 6 并: ', f-plane or approximately vertical plane. The platform part of the plaque ° Ρ 614 can also be the first - (four) foot group ship or two inside? 丨 foot group coffee - part, please _ refer to Figure 14 'lead frame _ the first - inner pin Above the group == folding structure 50 is connected by an adhesive layer 230

Alternatively, the adhesive layer 230 may alternatively be disposed on the first inner pin group 表面 of the lead frame 表面 611 '' and the multi-wafer offset stack structure 5Q. In addition, in the embodiment, for the bonding method between the first (-) leg group and the multi-wafer offset stacking of the wire, it is also possible to use tape as the connecting material, especially a double. The adhesive has adhesive _ (this attached film). After completing the test 60 (); after the offset stack structure 5 (4) is joined, the metal wires are connected. First, the metal wire is connected to the pad of the wafer 500a by one end of the metal wire _a, such as the first pad 3 or the third pad 344 in the foregoing FIG. 3, and the metal wire 64〇a The other end is connected to the first solder bump of the wafer or the third solder pad = 4; then one end of the metal wire 64〇b is connected to the first solder bump 3 or the third solder pad 344 of the wafer cassette. The other end of the metal wire is connected to the first inner lead group 6·the upper surface 611; then 'the lead frame _ is reversed by 18 degrees, so that the lower surface 612 of the inner lead group 610 faces upward' and then The multi-wafer offset stack structure 5 is connected to the lower surface 612 of the first inner lead group 610A, followed by the connection process of the metal wires 64, and the metal wire ends are connected to the solder joints of the wafer ore, for example, the foregoing In FIG. 3, the first turn 312a or the second solder fillet 344' and the other end of the metal wire 6 is connected to the first pad 3 of the wafer 5_ or the third pad 344; One end is connected to the first pad of the wafer 5〇〇c or the third pad 344, and the metal wire is connected to the other end of 2008. 37919 is over the surface 612 below the pin group 61〇B. In this way, after the connection is completed through the metal wire secret, _c and _D layers, the wafer can be torn and the 500d is electrically connected to the first inner pin group and the second inner portion of the lead frame (4): The metal wires 640 may be made of gold. Finally, the electrically connected multi-wafer offset stacked package structure is overlaid on the platform portion 613 of the abundance structure and the lead frame _, and the lead frame (4) = the ankle 650 is exposed. In addition to the encapsulant 7〇〇, a stacked chip package structure can be formed.

In addition, in the manner of forming the embodiment, in addition to the above process, the wafer offset stack structure 50 may be selected to be completed with the upper surface 6 ιι and the lower surface (10) of the first inner pin group ship respectively. The gold wire is connected to the process, and then the metal wire is electrically connected to the wafer. In this regard, the invention is limited. Further, the multi-wafer offset stack structure 5 is connected to the inner lead group (10), and a multi-wafer offset stacked package structure of the upper and lower symmetry may be formed as shown in Fig. 15. As shown in Fig. 15, the main difference between it and the 14th figure is that the multi-wafer offset stack structure on the upper surface 621 and the lower surface 622 of the wafer holder 62 is composed of the same side and a plurality of strips. The metal wire 640 is connected to the first inner pin group 61A and the second inner pin group. Since the process of forming a multi-wafer offset stacked package structure which is vertically symmetrical is the same as that described above, it will not be described in detail. Finally, please refer to FIG. 6 . In this embodiment, a bus bar 63 再 can be further disposed in the gap between the first inner pin group 6 and the second inner pin group 610B to enable the lead frame of the embodiment. It is also possible to increase the electrical connection point including the electrical point and the grounding contact signal contact by means of the busbar 630, as shown in FIG. Through the above description, the embodiments described in this publication do not limit the number of stacked wafers, and those skilled in the art should be able to fabricate stacked wafers having more than two wafers according to the method of the upper frequency disclosure. Package structure. Meanwhile, in the embodiment of FIGS. 14 and 15 in the case of 200837919, the sheet offset stack structure % can also be replaced with a multi-wafer offset stack structure % or a multi-wafer bias structure due to the multi-wafer shift. The stack structure 30, the multi-wafer offset stack structure 5q, and the home wafer offset stack structure 70, the lead frame _ the metal wire connection after the bonding: and the process of sealing the glue are the same, and therefore will not be described again. In summary, the wafer structure proposed by the present invention can be disposed in the front-end process, and the plurality of pads on the wafer are disposed on one side of the wafer, and the disclosure includes another manner, if The first pad and the second pad are concentrated on a single side of the wafer structure via a suitable wire bond area planning and reconfiguration circuit layer, such that the wafer structure is adapted to pass through the wire bond area Directly carry other wafer structures. Therefore, the stack-type chip package structure formed by stacking the above wafer structures can have a higher degree of seismogenic accumulation than the prior art. It will be apparent that the present invention may have many modifications and variations in light of the above description of the embodiments. It is therefore to be understood that within the scope of the appended claims, the invention may be The above is only a preferred embodiment of the vehicle of the present invention, and is not intended to limit the scope of the claims of the present invention; any equivalent changes or modifications made without departing from the spirit of the present invention should be included in the following. The patent application fee is included. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A, Fig. 1B, Fig. 1C, Fig. 2A is a cross-sectional view of a prior art; another prior art cross-sectional view; another prior art cross-sectional view; a top view of the wafer structure of the present invention; 200837919 2B is a cross-sectional view of the wafer structure of the present invention; FIG. 2C is a cross-sectional view of the multi-wafer offset stack structure of the present invention; FIGS. 3A to 3C are schematic views showing a manufacturing process of the reconfiguration layer of the present invention; 4A to B Figure 5 is a cross-sectional view of a wire bond landing zone in a reconfigurable layer of the present invention. Figure 5A is a cross-sectional view of a multi-wafer offset stack structure having a reconfigured layer of the present invention,

5B is a cross-sectional view showing another embodiment of the multi-wafer offset stack structure having a reconfiguration layer of the present invention; and FIG. 6 is a cross-sectional view showing a multi-wafer offset stack structure having upper and lower symmetry; FIG. Another embodiment of the multi-wafer offset stack structure having the upper and lower symmetry of the present invention is a cross-sectional view of another embodiment of the present invention; another embodiment of the multi-wafer offset stack structure having the upper and lower symmetry of the present invention is a multi-chip having upper and lower symmetry A further embodiment of the offset stack structure. A cross-sectional view of the ninth embodiment is implemented; a multi-wafer offset stack having a 汇 且 and a top symmetry, and a cross-sectional view of another embodiment;

His/the present invention has a cross-sectional view of another embodiment of a multi-wafer offset stack having a horizontally symmetric symmetry of the bus 且, and a multi-wafer offset stacking pattern of the upper and lower symmetrical multi-wafer offset stacks A cross-sectional view of yet another embodiment of the invention having a manifold and having a meandering structure. Figure 13 is a cross-sectional view of the present invention having a stacking structure with a stack of 21 200837919; a fragrant line, a multi-wafer offset stacking structure of the present invention having an upper and lower symmetry; a cross-sectional view of an embodiment; A cross-sectional view of a multi-wafer offset stack of the present invention having a busbar and having upper and lower symmetry. m Fig. 15 is a cross-sectional view showing still another embodiment of the multi-wafer offset stack structure having the upper and lower symmetry of the present invention

[Main component symbol description] 2'3'4: Semiconductor component 5 : Lead frame lead 5a : Lead frame inside lead frame

5b: lead frame outer pin 5c: lead frame platform portion 7 ' 8 N 9 '·electrode 10' U, 12: metal wire 200 (a, b, c, d): wafer 210: wafer active surface 220 · wafer back 230 · Adhesive layer 240 ^ pad 250 _ · wire bond area 260 : wire bond area edge line 3 〇: multi-wafer offset stack structure 31 · wafer body 22 200837919 312a: first pad 312b: second solder Pad 320: wire bonding region 322: wire bonding region edge line 330: first protective layer 332: first opening 340: reconfiguring wiring layer 344: third bonding pad 350: second protective layer 352: second opening 300 : Wafer structure 400: reconfigured wire layer 50: multi-wafer offset stack structure 500 (a, b, c, d): wafer 600: lead frame 610: inner pin 610A: first inner pin group 610B: second Inner pin group 611: inner pin upper surface 612: inner pin upper surface 613: platform portion 614: connection portion 620: wafer holder 621: wafer holder upper surface 622 · · wafer holder lower surface 630: bus bar 200837919 640 (a ~ e): metal wire 650: outer pin 70: multi-wafer offset stack structure 700: sealant

Claims (1)

200837919 卜, the scope of application for patents: I - a multi-wafer offset stacking package structure with upper and lower symmetry, comprising: - a lead frame 'diligent complex number field - the fourth (four) foot group and the second inner pin group and: wafer _ composition, the wafer carrier records a plurality of oppositely arranged between the first__foot group and the inner pin group' and the first inner pin group and the second inner pin group and the wafer holder 2 have An upper surface and a lower surface opposite to the upper surface; - a first-multi-wafer offset stack structure is configured by a plurality of wafers offset from the mother of the two sides - the active side of the wafer is disposed on the side a plurality of Tan 塾; - Γ曰 多 多 多 偏移 偏移 偏移 ' ' ' 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多 多The second (four) Qing under the surface of the electrical material to connect:! After the construction of the Du-Ning-Duoxian piece offset stack 4 structure, material two multi-chip offset stack 4 r such as ^ =, the second (four) and the bearing seat and Outside the editor (10). The seat and the (-)::::: share the same: the guide street _ film rewards the visit structure, which in the section "the wafer structure (four) foot group and the second (four) Qi formation - under the ice The package structure of claim 1, 2, 3 or 4, wherein the first multi-wafer offset stack structure and the second multi-wafer offset stack structure are at least A wafer includes a wafer body having a wire bonding region adjacent to a single side or adjacent side edges of the wafer body, wherein the wafer body has a plurality of bonding wires a first pad in the bonding region and a plurality of second pads outside the bonding region of the bonding wire; a protective layer disposed on the wafer body, wherein the first protective layer has a plurality of first openings, Exposing the first pads and the second pads; the redistribution circuit layer is disposed on the first protection layer, wherein the reconfiguration circuit layer extends from the second pads to the wire bonding Within the area, and the reconfiguration circuit layer has a plurality of connections at the bonding line a third solder fillet in the lands; and a second protective layer overlying the reconfigured wiring layer, wherein the second protective layer has a plurality of second openings to expose the first pads and the Third pad. 6. The package structure of claim 5, wherein the material of the rewiring circuit layer comprises gold, copper, nickel, tungsten tungsten or titanium. 7. The package structure of claim 5, wherein the at least one wafer structure t and the third solder bumps are arranged in at least one column along a single side of the wafer body. 8: The package structure of claim 1, wherein the first multi-wafer offset stack structure and the number of stacked wafers in the second multi-wafer offset stack structure are two wafers. 9·- a multi-wafer offset stacked package structure having upper and lower symmetry, comprising: - a lead frame ' is composed of a plurality of _ _ _ - (4) foot group and the first pin group and: the wafer is contacted, The wafer holder is located between the plurality of opposite rows of the first (four) leg group and the δ 弟 一 inner pin group ′ and the first inner pin group and the second inner pin group and the wafer holder are respectively Having an upper surface and a lower surface opposite to the upper surface. A first multi-wafer offset stack structure is formed by stacking a plurality of wafers offset, and the 26th 200837919 - multi-wafer offset stack #结_ Connected to the upper surface of the wafer holder, and a plurality of solder pads are disposed on each side of the active surface of the wafer; the shift-second multi-chip offset stack structure is composed of a plurality of wafers The offset is stacked, and the first:=stacking structure is fixed to the lower surface of the wafer holder, and the second multi-chip is offset from the stack. The mother of the structure - a plurality of solder pads are disposed on one side of the active surface of the wafer, and the plurality of first metal wires are separated from the plurality of pads of the first multi-chip offset stack structure by the side The first section of the guide county—(4) the wire surface electrical connection of the foot group; the plurality of second metal wires are offset from the other side by the plurality of pads of the second multi-wafer stack structure and the second inner lead of the lead frame The surface of the foot group is electrically connected, and (4): the body of the package, the cladding-multi-wafer offset stack structure, the second multi-wafer offset stack: the structure, the inner-inner pin group, the second The inner pin group and the wafer socket and the exposed lead pin group and the second=including a bus bar are disposed in the plurality of oppositely arranged first inner pin groups and the inner one pin group and the chip Between the seats. The package structure described in item 9 wherein the wafer holder in the lead frame is coplanar with the _-(four) foot group and the second (four) foot group. Wherein the construction in the lead frame. The 51-foot group and the turn-in-pin group form a lower-down (d__set) junction 9 structure, which is an inner bow and a second inner lead group form an upper set and an et) junction. The package structure of claim 9, wherein the bus bar and the wafer carrier 14 are in a common plane assembly and the second inner portion The busbar and the first inner 27 200837919 15. If the application structure of the home appliance is applied, the busbar forms a height difference with the first inner pin group and the second (four) leg group and the wafer holder. 16) The package structure as described in claim 9, 10, 11, 12, η, 14 or 15 wherein the first polymorphic offset stack structure and the second multi-wafer offset stack structure A wafer includes: a wire bonding region adjacent to a wafer body on a single side or adjacent sides of the wafer body, wherein the wafer body has a plurality of a first soldering pad located in the bonding region of the bonding wire and a plurality of second bonding pads located outside the bonding wire bonding region; and the second bonding layer disposed on the wafer body, wherein the first protective layer has a first @口' to expose the first solder fillets and the second solder bumps; ... a reconfigurable light layer 'disposed on the first layer, the towel 4 of the circuit layer from the second Spreading to the wire bond zone _, and the wire layer has a plurality of third pads located in the wire bond area; and the cover layer 'overlays the overlying line layer, The second protective layer/there is an opening to expose the first pads and the third pads. According to the package structure described in Item 13, the material of the re-wiring circuit layer comprises gold, copper, nickel, tungsten tungsten or titanium. The second solder pads are arranged along the single-side of the wafer body along the single-side (10) group and the plurality of parallel second (four)-foot groups and the 28th 200837919 one (four) foot group and the second inner 5/ The end of the foot group, the platform part - (four) __ = ^ = _ and by the - pin group and the second inner pin group are / under the structure, and the first inner lower surface; And - moved to the upper surface - Multi-wafer offset stacking junction offset shouting and the first more _:::::-=:== Move each stack in the stack structure to know how to unload the ugly There are a plurality of pads on one side of the button: a plurality of wires are electrically connected to the upper surface of the first lead group of the first and second groups of the wire frame by the (4) (four) I multi-chip material. And a plurality of second metal wires electrically connecting the plurality of pads of the second multi-chip offset stack structure to the lower surface of the second inner leads of the lead frame by the other side; and a colloid The first multi-wafer offset stack structure, the second multi-wafer offset stack π structure, the δ 弟 内 inner pin group, and the second inner pin are covered and exposed to the outer leads. The package structure of claim 20, wherein at least one of the first multi-wafer offset stack structure and the second multi-wafer offset stack structure comprises: a wafer body having a wire bond The wire bonding region is adjacent to a single side or adjacent side edges of the wafer body, wherein the wafer body has a plurality of first soldering pads located in the bonding wire bonding region and a plurality of the bonding wires a second soldering pad outside the bonding area; a first protective layer disposed on the wafer body, wherein the first protective layer has a plurality of first openings to expose the first bonding pads and the second soldering a reconfigured circuit layer disposed on the first protective layer, wherein the reconfigured wiring layer extends from the second pads to the bond wire bonding region, and the reconfigurable circuit layer has 29 200837919 a third bonding pad located in the bonding area of the bonding wire; and a second protective layer covering the reconfigured wiring layer, wherein the crucible has a plurality of second openings to expose the first bonding pads and the Rail, ^ The package structure according to item 21 of the two ΙΓΓ circumference, wherein the reconfiguration of the wiring layer material to shake include gold, steel, nickel, titanium, tungsten, or titanium. 23. The sealing structure of claim U, wherein the and the three pads are along the (10) body core 24. The package structure as described in claim 2, the stack structure and the The second multi-wafer offset stack structure in the stacked wafer U-chip offset inner chat group and the second inner lead group and the further step configuration - the convergence year wire wood in the brother one 25. In the package structure described in item 21, the inner pin group and the second (four) leg group are formed into a coplanar plane. - the same as - 26. a stack of wafer package structure, including - lead frame 'gamma complex number _ (10) group and a plurality of outer groups having a plurality of parallel first-inner pin groups and a plurality of parallel In the first _ ^ 引 一 内 内 内 与 与 与 与 与 与 与 与 与 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且By a group: two groups each having a top-to-side multi-two-fold stacking of the main__^ surface of the wafer and the first-multi-wafer bias-second multi-wafer offset stacking structure Partially multi-layered (3) axis-on-axis, _ group: =:= 200837919 Each of the active faces of the wafer in the stacked structure is arranged with a plurality of --metal wires from the side And electrically connecting the first plurality of wafer pads to the upper surface of the first inner pin group of the lead frame; Constructing the plurality of second metal wires from the plurality of first metal wires and the side wafer offset stacking structure of the plurality of pads and the lead frame, the second multi-sex connection: and the inner bow The underside of the lame-electrode's cladding the first-multi-wafer offset stack structure, the second multi-wafer offset stack, -. The first inner pin group and the second inner pin expose the outer pin. _ 27." Please (4) 26 items of the Lin package structure, wherein the first stack $ structure and the second multi-wafer offset stack structure at least one of the wafers comprises: - a crystal body 'with a wire bond area, the wire bond The region is adjacent to the single-side or adjacent sides of the chip body, wherein the wafer body has a plurality of first pads located in the bond wire bonding region and a plurality of wires located in the wire bonding region a first soldering layer is disposed on the wafer body, wherein the first protective layer has a plurality of first openings to expose the first pads and the second pads; / ^ - reconfiguring the circuit layer, disposed on the first layer, the reconfigurable circuit layer extending from the second pads to the bonding wire bonding region, and the reconfiguring circuit layer having multiple locations a third bonding pad in the bonding area of the bonding wire; and a second protective layer covering the reconfigured wiring layer, wherein the second protective layer has a plurality of second openings to expose the first bonding pads And the third pads. The package structure described in the patent application § π, wherein the material of the Wei line is gold, copper, nickel, tungsten tungsten or titanium. The package structure of claim 27, wherein the first pads and the third pads of the wafer structures are arranged in at least one row along a single side of the wafer body. The package structure of claim 26, wherein the first multi-wafer offset stack structure and the number of stacked wafers in the second multi-wafer offset stack structure are both wafers. 32