1-331379- * 九、發明說明： 【發明所屬之技術領域】 本發明係有關於多晶片堆叠技術，特別係有關 • 種背對背晶片堆疊構造。 【先前技術】 多晶片堆疊技術能整合多顆半導體晶片並節省 元件的表面接合面積（footprint)，已是—門越來越 的課題。依晶片主動面朝向方向的不相同，晶片堆 • 進一步區別為背對面正向打線之晶片堆疊、面對面 堆疊、背對背之晶片堆疊。一種習知背對背晶片堆 造已揭露於我國發明專利證號第〗243464號「半導 置」。 請參閱第1圖所示，一種習知背對背晶片堆要 100主要包含一基板110、一第—晶片12〇以及〆 晶片130。該第一晶片120係具有複數個凸塊121 φ 覆晶方式設置於該基板110上。該第二晶片13〇之 係利用一平面黏晶層1 6 0黏貼於該第一晶片1 2 〇 面’故可使得該第一晶片120與該第二晶片13〇係 對背方式堆疊。該第二晶片130係具有複數個 131，並藉由複數個銲線140電性連接該第二晶# 之該些銲墊131至該基板110。一封膠艎150係形 該基板110上，以密封該第一晶片12〇、該第二晶片 與該些銲線140。為了符合先進半導體封裝技術之 短小與高可靠度的要求，習知背對背晶片堆疊構造 於一 整個 重要 疊讦 覆晶 疊構 體裝 構造 第二 ，以 背面 之背 以背 銲蟄 13〇 成於 13〇 輕薄 1〇〇 5 1331379. 之晶片堆疊高度有降低的必要，但若單純減少晶片 度，則會影響上方第二晶片1 3 0之打線接合強度。 【發明内容】 本發明之主要目的係在於提供一種背對背晶片 構造，達成降低晶片堆疊高度並加強黏晶強度之功 更不影響對上方晶片之打線接合。 本發明的目的及解決其技術問題是採用以下技 案來實現的。依據本發明，一種背對背晶片堆疊構 要包含一基板、一第一晶片以及一第二晶片。該第 片係設置於該基板上。該第二晶片係疊設於該第一 上並電性連接至該基板。其中，該第一晶片係具有 一背面圖案，該第二晶片係具有一第二背面圖案， 一背面圖案係與該第二背面圖案為凹凸嚅合。 本發明的目的及解決其技術問題還可採用以下 措施進一步實現。 在前述的背對背晶片堆疊構造中，該第一背面 之高度差係可介於該第一晶片之厚度三分之一至 之二。 在前述的背對背晶片堆疊構造中，該第二背面 之高度差係可介於為該第二晶片之厚度三分之一 分之二。 在前述的背對背晶片堆疊構造中，該第一背面 之高度差係可約為該第一晶片之厚度二分之一，而 二背面圖案之高度差係可約為該第二晶片之厚度 之厚 堆疊 效， 術方 造主 一晶 晶片 一第 該第 技術 圖案 三分 圖案 至三 圖案 該第 二分 6 1-331379· 之一° 在前述的背對背晶片堆疊構造中 為覆晶晶片，該第二晶片係可為打線 在前述的背對背晶片堆疊構造中 係可具有凸形截面，該第二背面圖！ 面。 在前述的背對背晶片堆疊構造中 具有複數個銲墊，其係對準於該第二 面邊緣。 在前述的背對背晶片堆疊構造中 與該第二背面圖案係可具有相互對應 在前述的背對背晶片堆疊構造中 鋸齒狀。 在前述的背對背晶片堆疊構造中 個銲線，其係電性連接該第二晶片至 在前述的背對背晶片堆疊構造中 第二晶片係可皆為打線型晶片。 在前述的背對背晶片堆疊構造中 至少一槽孔，以供打線連接該第一晶 在前述的背對背晶片堆疊構造中 晶層，其係非平面黏接該第一晶片之 該第二晶片之該第二背面圖案。 在前述的背對背晶片堆疊構造中 膠體，其係形成於該基板上，以密封 ，該第一晶片係可 型晶片。 ，該第一背面圖案 I係可具有凹形截 ，該第二晶片係可 背面圖案之凹形截 ，該第一背面圖案 之波形截面。 ，上述波形截面係為 ，可另包含有複數 該基板。 ，該第一晶片與該 ，該基板係可具有 片與該基板。 ，可另包含有一黏 該第一背面圖案與 ，可另包含有一封 該第一晶片與該第 7 1*331379· 二晶片。 在前述的背對背晶片堆疊構造中，該第一晶片與該第 二晶片係可具有相同功能與尺寸。 【實施方式】 依據本發明之第一具體實施例，以第2圖與以下說 明内容揭示一種背對背晶片堆叠構造。 請參閱第2圖所示，一種背對背晶片堆疊構造200 主要包含一基板210、一第一晶片以〇以及一第二晶片 • 230。 該基板210係具有一上表面21丨與一相對之下表面 2 1 2，並具有電性傳遞功能，例如印剃電路板、導線架、 陶瓷基板、玻璃基板。在本實施例中’該基板210係為 一記憶卡之多層印刷電路板，在該上表面211與該下表 面212分別設有内接墊與外接觸指（圈未繪出）’而該第 一晶片220與該第二晶片230可皆為快閃記憶體晶片。 其中，該第一晶片220與該第〉晶片23〇背對背堆 •疊並設置於該基板210上，進—步样述如後。該第一晶 片22〇係設置於該基板210之該上表面211。該第二晶 片230係疊設於該第一晶片220上並電性連接至該基板 2 1 0。在本實施例中’該第一晶片22〇係可為覆晶晶片’ 該第二晶片230係可為打線型晶片。在該第一晶片220 之一第一主動面222係設有複數個凸塊223，如金凸 塊、錫鉛凸塊或其它導電凸塊，以供覆晶接合至該基板 210。再者，在該第二晶片230之一第二主動面232係 8 1-331379- 具有複數個銲墊233，該背對背晶片堆叠構造200可另 包含有複數個銲線240，其係電性連接該第二晶片23〇 之銲墊233至該基板210» 此外’該第一晶片220係具有一第—背面圖案221， 其形狀為任意形狀的浮雕。而該第二晶片23〇係具有— 對應之第二背面圖案231’該第一背面圖案221係與該 第二背面圖案23 1為凹凸嚅合。在本實施例中，該第一 背面圖案221係可具有凸形截面，該第二背面圖案231 係可具有凹形截面。而該第二晶片230之該些銲塾233 係可對準於該第二背面圖案231之凹形截面邊緣。 因此’在該第一背面圖案221與該第二背面圖案231 之間係可創造出非平面的黏晶間隙。該背對背晶片堆叠 構造200可另包含有一黏晶層260，其係非平面黏接該 第一晶片220之該第一背面圖案221與該第二晶片23〇 之該第二背面圖案23 1，以增強黏晶強度。 此外，該第一背面圖案22 1之凹凸高度差係可介於 該第一晶>4 220之厚度三分之—s t1-331379- * IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to multi-wafer stacking techniques, and more particularly to a back-to-back wafer stack configuration. [Prior Art] Multi-wafer stacking technology can integrate multiple semiconductor wafers and save surface footprint of components, which is an increasingly problematic topic. Depending on the direction of the active face of the wafer, the wafer stack is further distinguished by wafer stacking, face-to-face stacking, back-to-back wafer stacking. A conventional back-to-back wafer stacking has been disclosed in "Semiconductor" No. 243464 of China Invention Patent No. 243464. Referring to FIG. 1, a conventional back-to-back wafer stack 100 mainly includes a substrate 110, a first wafer 12, and a germanium wafer 130. The first wafer 120 has a plurality of bumps 121 φ on which the substrate 110 is flip-chip mounted. The second wafer 13 is adhered to the first wafer 12 by using a planar die layer 160. Thus, the first wafer 120 and the second wafer 13 can be stacked in a back-to-back manner. The second wafer 130 has a plurality of 131 electrodes, and the pads 131 of the second crystals are electrically connected to the substrate 110 by a plurality of bonding wires 140. An adhesive 150 is formed on the substrate 110 to seal the first wafer 12, the second wafer, and the bonding wires 140. In order to meet the requirements of the short and high reliability of advanced semiconductor packaging technology, the conventional back-to-back wafer stack is constructed in a second important stacking flip-chip assembly structure, and the back surface is back-welded to 13晶片 Lightweight 1〇〇5 1331379. The wafer stack height is reduced, but if the wafer density is simply reduced, it will affect the bonding strength of the upper second wafer 130. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a back-to-back wafer construction that achieves the work of reducing the stack height of the wafer and enhancing the strength of the die bond without affecting the wire bonding of the upper wafer. The object of the present invention and solving the technical problems thereof are achieved by the following techniques. In accordance with the present invention, a back-to-back wafer stack structure includes a substrate, a first wafer, and a second wafer. The first sheet is disposed on the substrate. The second wafer is stacked on the first and electrically connected to the substrate. The first wafer has a back surface pattern, and the second wafer has a second back pattern, and the back pattern is embossed with the second back pattern. The object of the present invention and solving the technical problems thereof can be further achieved by the following measures. In the aforementioned back-to-back wafer stack configuration, the height difference of the first back surface may be between one third and two of the thickness of the first wafer. In the aforementioned back-to-back wafer stack configuration, the height difference of the second back surface may be two thirds of the thickness of the second wafer. In the foregoing back-to-back wafer stack configuration, the height difference of the first back surface may be about one-half of the thickness of the first wafer, and the height difference of the two back patterns may be about the thickness of the second wafer. Stacking effect, a master wafer, a first technical pattern, a third pattern to a third pattern, a second portion, 6 1-331379 · one of the above-mentioned back-to-back wafer stack structure, a flip chip, the second The wafer system can be a wire having a convex cross section in the aforementioned back-to-back wafer stack configuration, the second rear view! surface. In the foregoing back-to-back wafer stack configuration, there are a plurality of pads that are aligned with the second face edge. In the foregoing back-to-back wafer stack configuration, the second back pattern can have a mutual correspondence in the aforementioned back-to-back wafer stack configuration. In the foregoing back-to-back wafer stack configuration, the bonding wires are electrically connected to the second wafer. In the foregoing back-to-back wafer stacking structure, the second wafer system may be a wire bonding type wafer. At least one slot in the foregoing back-to-back wafer stack configuration for wire bonding the first crystal in the foregoing back-to-back wafer stack configuration, the non-planar bonding of the second wafer of the first wafer Two back patterns. In the foregoing back-to-back wafer stack configuration, a colloid is formed on the substrate to seal, the first wafer being a formable wafer. The first back surface pattern I may have a concave cross section, and the second wafer may have a concave cross section of the back surface pattern, and the first back surface pattern has a waveform cross section. The waveform cross section is that the substrate may be further included. The first wafer and the substrate may have a sheet and the substrate. And additionally comprising a first back surface pattern and, further comprising a first wafer and the seventh 1/331379. In the aforementioned back-to-back wafer stack configuration, the first wafer and the second wafer system can have the same function and size. [Embodiment] According to a first embodiment of the present invention, a back-to-back wafer stack configuration is disclosed in the second drawing and the following description. Referring to FIG. 2, a back-to-back wafer stack structure 200 mainly includes a substrate 210, a first wafer, and a second wafer. The substrate 210 has an upper surface 21 丨 and an opposite lower surface 221 and has an electrical transfer function, such as a printed circuit board, a lead frame, a ceramic substrate, and a glass substrate. In the present embodiment, the substrate 210 is a multi-layer printed circuit board of a memory card, and the upper surface 211 and the lower surface 212 are respectively provided with an inner pad and an outer contact finger (not shown). A wafer 220 and the second wafer 230 can both be flash memory chips. The first wafer 220 and the NAND wafer 23 are stacked back to back and disposed on the substrate 210, as described later. The first wafer 22 is disposed on the upper surface 211 of the substrate 210. The second wafer 230 is stacked on the first wafer 220 and electrically connected to the substrate 210. In the present embodiment, the first wafer 22 can be a flip chip. The second wafer 230 can be a wire-type wafer. The first active surface 222 of the first wafer 220 is provided with a plurality of bumps 223, such as gold bumps, tin-lead bumps or other conductive bumps, for flip-chip bonding to the substrate 210. Furthermore, the second active surface 232 of the second wafer 230 is 232-331379- having a plurality of pads 233. The back-to-back wafer stack 200 can further comprise a plurality of bonding wires 240 electrically connected. The second wafer 23 is soldered to the substrate 210. The first wafer 220 has a first-back pattern 221, which is shaped as an embossment of any shape. The second wafer 23 has a corresponding second back pattern 231', and the first back pattern 221 is embossed with the second back pattern 23 1 . In this embodiment, the first back surface pattern 221 may have a convex cross section, and the second back surface pattern 231 may have a concave cross section. The solder pads 233 of the second wafer 230 can be aligned with the concave cross-section edges of the second back surface pattern 231. Therefore, a non-planar adhesive gap can be created between the first back pattern 221 and the second back pattern 231. The back-to-back wafer stack structure 200 may further include a die bonding layer 260 that non-planarly adheres the first back surface pattern 221 of the first wafer 220 and the second back surface pattern 23 1 of the second wafer 23 Enhance the strength of the bond. In addition, the height difference of the first back surface pattern 22 1 may be between the thickness of the first crystal > 4 220 - s t
在本實施例的具體結構中，In the specific structure of this embodiment,
200可另包含有一封膠體250, 9 B31379· 上，以密封該第一晶片220與該第二晶片230。 關於該第一晶片220之該第一背面圊案221的凸形 截面形成方法，已為習知技術，故不再贅述。配合參閱 第3A至3D圖，以下僅說明該第二晶片230之該第二 背面圖案 23 1的凹形截面形成方法。首先，請參閱第 3A圖所示，提供一晶圓10,該晶圓10係具有複數個切 割道1 1，該些切割道1 1係用以定義出複數個第二晶片 230。該晶圓10係更具有複數個銲墊233，其係位於該 些第二晶片230之第二主動面232。 接著，請參閱第3B圖所示，利用一第一切割刀20 切割該晶圓1 0，用以局部減薄該晶圓10之厚度。該第 一切割刀20係為寬幅磨刀，該第一切割刀20切割路徑 係沿著該第二晶片 23 0之背面中央位置且相鄰該些切 割道1 1之間進行，且不切穿該晶圓10，使該些第二晶 片230具有複數個第二背面圖案23 1。 之後，請參閱第3 C圖所示，利用一第二切割刀3 0 沿著該些切割道1 1切穿該晶圓1 0，以使該些第二晶片 230為單體化。最後，請參閱第3D圖所示，該些已單 體化之第二晶片 230係具有凹形截面之第二背面圖案 23 1，即使直接應用在單晶片的打線連接，亦具有良好 的打線支撐。 在第二具體實施例中，揭示另一種背對背晶片堆疊 構造，請參閱第4圖所示，該背對背晶片堆疊構造3 00 主要包含一基板310、一第一晶片320以及一第二晶片 10 1331379* 330〇該基板310係具有一上表面311、一相對 面312以及至少一貫穿該上表面31〗與該下表面 槽孔3 1 3。在本實施例中，該第一晶片32〇與該 片330係可皆為打線型晶片’並背對背堆義在 310之上表面311上。 該第一晶片320係設置於該基板31〇之上表 該第一晶片320係具有複數個第一銲塾323，其 於該第一晶片32〇之一第一主動面322。該背對 鲁 堆疊構造300可另包含有複數個第一銲線341， 過該槽孔313並電性連接該第一晶片32〇之該些 墊323至該基板310» 該第二晶片330係疊設於該第一晶片320上 連接至該基板310。該第二晶片33〇係具有複數 銲墊3 3 3 ’其係形成於該第二晶片33〇之一第二 332。該背對背晶片堆疊構造3〇0可另包含有複 φ 二銲線342，其係電性連接該第二晶片330之該 銲墊333至該基板31〇。 其中’該第一晶片320係具有一第一背面圖f 6亥第一晶片33〇係具有一第二背面圖案331，該 面圖案321係與該第二背面圖案331為凹凸嚙 中’該第一背面圖案321之高度差係可約為該第 320之厚度二分之一’而該第二背面圖案331之 係可約為該第二晶片330之厚度二分之一。該第 圖案321與該第二背面圖案331係可具有相互對 之下表 3 12之 第二晶 該基板 面 3 1 1， 係形成 背晶片 其係通 第一辉 並電性 個第二 主動面 數個第 些第二 ^ 3 2 1» 第一背 合。其 一晶片 高度差 一背面 應之波 11 1331379 形截面。較佳地，上述波形截面係為鋸齒狀，當該第二晶 片330黏晶時有稍許偏移時仍可滑移到正確位置。 因此’該背對背晶片堆疊構造300可另包含有一黏晶 層3 60，其係非平面黏接該第一晶片32〇之該第一背面 圖案321與該第二晶片330之該第二背面圖案331，以 增強黏晶強度。 該背對背晶片堆疊構造300可另包含有一封膠體 3 50’其係形成於該基板31〇之上表面311與該槽孔 3 13’以密封該第一晶片32〇、該第二晶片do與該些 銲線341與342。 該背對背晶片堆疊構造300可另包含有複數個銲球 37〇’其係設置於該基板31〇之該下表面312，以構成 球格陣列封裝（BGA)型態。在本實施例中，該第一晶片 3 2 〇與該第二晶片3 3 0係可皆為動態隨機存取記憶體晶 片’而具有相同功能與尺寸，但亦可為具有不相同功能 之晶片。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實施 例揭露如上’然而並非用以限定本發明，任何熟悉本真 '的技術人員，在不脫離本發明技術方案範圍内，當 jffi k 上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 〜依據本發明的技術實質對以上實施例所作 單修改、哲 J任何簡 "、寺同變化與修飾，均仍屬於本發明技術方 12 1*331379· 範圍内。 【圖式簡單說明】 第1圖：一種習知背對背晶片堆疊構造之截 第2圖：依據本發明之第一具體實施例，一 3 片堆疊構造之截面示意圖。 第3A至3D圖：依據本發明之第一具體實;! 該背對背晶片堆疊構造之第二晶J 面形成方法中一晶圓截面示意圖。 第4圖：依據本發明之第二具體實施例，另-晶片堆疊構造之截面示意圖。 【主要元件符號說明】 10 晶圓 11 切割道 20 第 30 第二切割刀 面示意圖。 重背對背晶 ife例，教示 丨之凹形截 -種背對背 一切割刀 晶層 表面 一主動面 二主動面 100 背對背晶片堆疊構造 110 基板 120 第一晶片 121 凸塊 130 第二晶片 131 銲墊 140 銲線 150 封膠體 160 黏 200 背對背晶片堆疊構造 210 基板 211 上表面 212 下 220 第一晶片 221 第一背面圖案 222 第 223 凸塊 230 第二晶片 231 第二背面圖案 232 第 233 銲墊 13 銲線 250 封膠體 260 黏晶層 背對背晶片堆疊構造 基板 311 上表面 312 下表面 槽孔 第一晶片 321 第一背 面 圖 案 322 第一主動面 第一銲墊 第二晶片 331 第二背 面 圖 案 332 第二主動面 第二銲墊 第一銲線 342 第二銲線 350 封膠體 黏晶層 370 銲球200 may further include a colloid 250, 9 B31379. to seal the first wafer 220 and the second wafer 230. The method of forming the convex cross section of the first back surface pattern 221 of the first wafer 220 is a conventional technique and will not be described again. Referring to Figs. 3A to 3D, only the concave section forming method of the second back pattern 23 1 of the second wafer 230 will be described below. First, referring to Fig. 3A, a wafer 10 is provided having a plurality of dicing streets 1 1 for defining a plurality of second wafers 230. The wafer 10 further includes a plurality of pads 233 located on the second active surface 232 of the second wafers 230. Next, referring to FIG. 3B, the wafer 10 is diced by a first dicing blade 20 for partially thinning the thickness of the wafer 10. The first cutting blade 20 is a wide sharpening blade, and the cutting path of the first cutting blade 20 is along the central position of the back surface of the second wafer 230 and adjacent to the cutting lanes 1 1 , and is not cut. The wafers 10 are worn such that the second wafers 230 have a plurality of second back patterns 23 1 . Thereafter, as shown in FIG. 3C, the second wafer 230 is cut through the wafer 10 by a second dicing blade 30 to make the second wafers 230 singulated. Finally, referring to FIG. 3D, the singulated second wafer 230 has a second back surface pattern 23 having a concave cross section, and has good wire bonding support even if it is directly applied to the wire bonding connection of the single wafer. . In a second embodiment, another back-to-back wafer stack configuration is disclosed. Referring to FIG. 4, the back-to-back wafer stack structure 300 mainly includes a substrate 310, a first wafer 320, and a second wafer 10 1331379*. The substrate 310 has an upper surface 311, an opposite surface 312, and at least one through the upper surface 31 and the lower surface slot 31. In this embodiment, the first wafer 32 and the wafer 330 may both be wire-bonded wafers and stacked back-to-back on the upper surface 311 of the 310. The first wafer 320 is disposed on the substrate 31. The first wafer 320 has a plurality of first pads 323, and is disposed on the first active surface 322 of the first wafer 32. The back-to-back stack structure 300 can further include a plurality of first bonding wires 341, and the pads 323 are electrically connected to the pads 323 of the first wafer 32 to the substrate 310. The first wafer 320 is stacked on the first wafer 320 and connected to the substrate 310. The second wafer 33 has a plurality of pads 3 3 3 ' formed on one of the second wafers 33 332. The back-to-back wafer stack structure 〇0 may further include a complex φ second bond wire 342 electrically connected to the pad 333 of the second wafer 330 to the substrate 31〇. Wherein the first wafer 320 has a first rear view image, the first wafer 33 has a second back surface pattern 331, and the surface pattern 321 is embossed with the second back pattern 331 The height difference of a back pattern 321 may be about one-half of the thickness of the 320th portion and the second back pattern 331 may be about one-half the thickness of the second wafer 330. The first pattern 321 and the second back pattern 331 may have a second crystal of the substrate 312, which is opposite to the surface of the substrate 312, and forms a back wafer, which is electrically connected to the first surface and electrically connected to the second active surface. Several second second ^ 3 2 1» first back. One of the wafers has a height difference, and the back side of the wave should be 11 1331379. Preferably, the waveform cross section is serrated, and the second wafer 330 can be slid to the correct position when there is a slight offset when the second wafer 330 is bonded. Therefore, the back-to-back wafer stack structure 300 may further include a die layer 306 that non-planarly bonds the first back surface pattern 321 of the first wafer 32 and the second back surface pattern 331 of the second wafer 330. To enhance the strength of the bond. The back-to-back wafer stack structure 300 may further include a glue body 350' formed on the upper surface 311 of the substrate 31 and the slot 3 13' to seal the first wafer 32, the second wafer do and the These bonding wires 341 and 342. The back-to-back wafer stack configuration 300 can further include a plurality of solder balls 37A disposed on the lower surface 312 of the substrate 31 to form a ball grid array package (BGA) type. In this embodiment, the first chip 3 2 〇 and the second chip 307 may both be dynamic random access memory chips and have the same function and size, but may also be wafers having different functions. . The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, although the present invention has been disclosed as a preferred embodiment, however, it is not intended to limit the invention. A person skilled in the art can make some modifications or modifications to equivalent embodiments of the technical content disclosed in the above, without departing from the technical solution of the present invention, without departing from the present invention. The technical essence of the above embodiment, the single modification of the above embodiment, the genius of any genre ", the same changes and modifications of the temple, still belong to the technical scope of the present invention 12 1 * 331379 ·. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional back-to-back wafer stack structure. FIG. 2 is a cross-sectional view showing a 3-piece stacked structure according to a first embodiment of the present invention. 3A to 3D are views showing a cross-sectional view of a wafer in a second crystal face forming method of the back-to-back wafer stack structure according to the first embodiment of the present invention; Figure 4 is a cross-sectional view showing another embodiment of the wafer stacking structure in accordance with a second embodiment of the present invention. [Main component symbol description] 10 Wafer 11 Cutting path 20 The 30th second cutting blade schematic. Heavy back-to-back crystal ife example, teaching 凹 concave cut-type back-to-back one dicing wafer layer surface one active surface two active surface 100 back-to-back wafer stacking structure 110 substrate 120 first wafer 121 bump 130 second wafer 131 pad 140 soldering Line 150 Sealant 160 Adhesive 200 Back-to-Back Wafer Stacking Structure 210 Substrate 211 Upper Surface 212 Lower 220 First Wafer 221 First Back Pattern 222 223st Tab 230 Second Wafer 231 Second Back Pattern 232 233 Pad 13 Bond Wire 250 Sealing body 260 adhesive layer back-to-back wafer stacking structure substrate 311 upper surface 312 lower surface slot first wafer 321 first back surface pattern 322 first active surface first pad second wafer 331 second back surface pattern 332 second active surface Second pad first wire 342 second wire 350 sealant layer 370 solder ball