200839983 九、發明說明： 【發明所屬之技術領域】 :發明係有關於一種打線連接型半導體封裝構造， 勒曰、有關於-種能低成本達到防止銲線短路與增加 a曰強度之打線連接型半導體封裝構造。 【先前技術】200839983 IX. Description of the invention: [Technical field to which the invention pertains]: The invention relates to a wire-bonding type semiconductor package structure, which is capable of achieving a wire-bonding type capable of preventing wire bond short-circuiting and increasing a 曰 strength at a low cost. Semiconductor package construction. [Prior Art]
、半導體封裝構造的演變持續朝向輕薄短小的趨勢， 承/技術的改善是希望可以沿用既有的封裝設備製作 更微小的半導體封裝構造，但仍有其極限。一旦既有低 成本的封裝兀件’如銲線或液態黏膠，無法適用新一代 的半導體封裝規格，則須採用新的封袭元件至覆晶凸塊 或黏曰日膠帶等等，甚至更換半導體封裝設備，將使得封 裝成本大幅的提高。 #參閱第1圖所示，早期一種習知的打線連接型半 導體封裝構造100包含一基板110、一液態黏膠12〇、 日日片130、複數個銲線14〇以及一封膠體15〇。該基 板11〇係具有一上表面ln、一下表面ιι2以及複數個 設置於該上表面lu之連接指η3。該液態黏膠12()係 黏接該晶片130之背面132，使其設置於該基板11〇之 該上表面1 1 1。然而在黏晶時，該液態黏膠丨2 〇會有外 擴而污染該些連接指113之問題。因此，該基板110設 計該晶片130之邊緣至該些連接指113須有5〇〇至 600μιη寬度，以防止該液態黏膠12()外擴至污染該連接 指113。藉由該些銲線140係電性連接該晶片13〇之複 6 200839983 數個銲墊1 3 3與該些連接指1 1 3，達到該晶片1 3 〇與該 基板1 1 0之電性互連，其中該些銲墊丨3 3係設於該晶片 1 3 0之一主動面1 3 1。該封膠體1 5 0係密封該晶片1 3 0 與該些銲線140。然而，選用如環氧液膠之液態黏膠120 進行黏晶，具有低成本之優點，但溢膠問題嚴重，須加 大該些連接指1 1 3與該晶片1 3 0之間距，故該基板1 1 0 不符合微小化的要求。再者，習知該些銲線1 4 0係為正 打銲線，銲線之最大弧高係鄰近或位於該晶片130之邊 (、 緣，以避免該些銲線1 4 0誤觸該晶片1 3 0之邊緣，故該 半導體封裝構造100之整體封装厚度難以進一步降 低。若嘗試直接將正打銲線改為逆打銲線（reverse bond)，雖可降低該些銲線140之弧高，但在模流壓力 極容易導致該些銲線140誤觸該晶片130之邊緣，引發 電性短路或漏電流。 請參閱第2圖所示，另一種習知的打線連接型半導 體封裝構造200包含一基板210、一黏晶膠帶220、一 t； 、 晶片230、複數個銲線240以及一封膠體250。該基板 210係具有一上表面211、一下表面212以及複數個連 接指213’其中該些連接指213係設置於該上表面21卜 該晶片230係利用該黏晶膠帶220之黏貼，使得該晶片 230之背面232可設置於該基板210之該上表面211。 由於該黏晶膠帶2 2 0不會有溢膠之問題，故該基板2 1 0 不需預留寬度進而縮小該基板210之使用面積’該些銲 線2 4 0係電性連接該晶片2 3 〇之複數個銲墊2 3 3與該些 7 200839983 連接指213 ’其中該些銲墊233係設於該晶片230之一 主動面23 1。該封膠體250係密封該晶片230與該些銲 線 …：而’膜片狀的黏晶膝帶220的成本與浪費係 達:於液I、點膠，導致封裝成本增加。上述該打線連接 呈半導體封襄構造2〇〇僅能解決溢膠及縮小基板之問 題’無法達到降低整體封裝厚度。 【發明内容】 本發月之主要目的係在於提供一種打線連接型半導 體封裝構xe ’藉由一線支撐攔壩與液態黏膠運用在打線 連接5L半導體封裝的組合關係，限制液態黏膠的擴散污 木:乂使基板之連接指可更加靠近於晶片，能低成本微小 3L ^又。十而不會衫響打線品質，另可增加黏晶強度與支撐 銲線’避免該些銲線因模户廢Λ π冰u镇机壓力或其它外力而碰觸該晶 片之邊緣導致短路。 本發明《二欠-目@係在於提供一種打線連接型半導 體封襄構造，藉由一線支樓摘場與複數個銲線運用在打 線：接！半導體封裝的組合關係，令該些鲜線之最大弧 、 相孚於該線支撐攔壩之高度，以 低成本薄型設計而不會影擎 〜饗打線品質，更可適用於多晶 片堆疊。 本發明之另一目的係在於扭 在於棱供一種打線連接型半導 體封装構造，有效減少基★ ^ # 基板使用面積進而降低成本，並 可降低整體封裝構造之厚♦，女… p 厚度，有利於半導體封裝構造之 尺寸細小。 8 200839983 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種打線連接型半導體封裝 構造主要包含一基板、一液態黏膠、一第一晶片、複數 個鲜線以及一線支撐攔壩。該基板係具有一黏晶區以及 複數個在該躲晶區之外的連接指。該液態黏膠係形成於 該黏晶區。該第一晶片係藉由該液態黏膠設置於該基板 之該黏晶區並具有複數個銲墊。該些銲線係電性連接該 些鮮塾與該些連接指。該線支撐攔壩係設置於該基板上 且在該黏晶區與該些連接指之間，並且該液態黏膠係黏 接該第一晶片、該基板與該線支樓棚壩。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的打線連接型半導體封裝構造中，該線支撐 攔壩係可具有一不低於該第一晶片之高度，以避免該些 銲線壓觸該第一晶片之邊緣。 在前述的打線連接型半導體封裝構造中，該些銲線 係可跨過該線支樓攔壩並可壓觸至該線支撑攔壞。 在前述的打線連接型半導體封裝構造中，該線支撐 攔壩係可選自於介電膠材、再塗施防銲層與被覆有電絕 緣層之金屬物之其中之一。 在前述的打線連接型半導體封襄構造中，該第一晶 片係可具有一主動面、一背面以及複數個在該主動面與 該背面之間之侧面。 在前述的打線連接型半導體封裝構造中，該液態黏 9 200839983 膠係可黏接該第一晶片之背面並沿著該線支撐攔壩黏 接至該第一晶片之至少一側面。 在前述的打線連接型半導體封裝構造中，該液態黏 膠係可具有一溢出高度（fillet height)，其係高於該第一 晶片之該背面但低於該第一晶片之該主動面。 在削述的打線連接型半導體封裳構造中，該線支撐 攔壩與該第一晶片之相鄰側面之間隙係可約相等於該 第一晶片之背面與該基板之間隙。 r 在前述的打線連接型半導體封裝構造中，該些銲塾 係可排列鄰近於該第一晶片之該主動面之邊緣。 在前述的打線連接型半導體封裝構造中，該些銲墊 至該主動面之間距係可小於該線支撐攔塌之寬度^ 在前述的打線連接型半導體封裝構造中，可Λ另包含 有一封膠體，其係密封該第一晶片、兮^ μ △ 曰曰方、该些銲線與該線支 撐攔壩。 在The evolution of semiconductor package construction continues to be light, thin and short. The improvement of the technology is to make it possible to use the existing packaging equipment to make a smaller semiconductor package structure, but there are still limits. Once a low-cost packaged component such as wire or liquid adhesive is not available for the next-generation semiconductor package specification, new squash elements must be used to flip the bump or bond tape, etc., or even replace Semiconductor packaging equipment will greatly increase the cost of packaging. Referring to Fig. 1, an earlier conventional wire bonding type semiconductor package structure 100 includes a substrate 110, a liquid adhesive 12, a solar wafer 130, a plurality of bonding wires 14A, and a gel 15 〇. The substrate 11 has an upper surface ln, a lower surface ι2, and a plurality of connecting fingers η3 disposed on the upper surface lu. The liquid adhesive 12() is adhered to the back surface 132 of the wafer 130 so as to be disposed on the upper surface 112 of the substrate 11. However, in the case of die bonding, the liquid adhesive 丨 2 〇 will expand to contaminate the connecting fingers 113. Therefore, the substrate 110 is designed to have an edge of the wafer 130 to the connecting fingers 113 having a width of 5 600 to 600 μm to prevent the liquid adhesive 12 () from expanding to contaminate the connecting fingers 113. The solder wires 140 are electrically connected to the wafers 13 200839983, and the plurality of pads 1 3 3 and the connecting fingers 1 1 3 are used to reach the electrical properties of the wafers 1 3 〇 and the substrate 1 10 . The interconnecting pads 3 3 are disposed on one of the active faces 133 of the wafer 130. The encapsulant 150 seals the wafer 130 and the bonding wires 140. However, the use of liquid glue 120 such as epoxy glue for die bonding has the advantage of low cost, but the problem of overflowing is serious, and the distance between the connecting fingers 1 1 3 and the wafer 130 must be increased, so the substrate 1 1 0 Does not meet the requirements for miniaturization. Moreover, it is known that the wire bonding wires 140 are positive bonding wires, and the maximum arc height of the bonding wires is adjacent to or located at the edge (and edge of the wafer 130) to prevent the wire bonding wires from being accidentally touched. The edge of the wafer 130 is so that the overall package thickness of the semiconductor package structure 100 is difficult to further reduce. If an attempt is made to directly change the positive bond wire to a reverse bond, the arc of the bond wire 140 can be reduced. High, but the mold flow pressure is extremely easy to cause the soldering wires 140 to accidentally touch the edge of the wafer 130, causing electrical short circuit or leakage current. Please refer to FIG. 2, another conventional wire bonding type semiconductor package structure 200 includes a substrate 210, a die bonding tape 220, a t; a wafer 230, a plurality of bonding wires 240, and a colloid 250. The substrate 210 has an upper surface 211, a lower surface 212, and a plurality of connecting fingers 213' The connection fingers 213 are disposed on the upper surface 21, and the wafer 230 is pasted by the die bonding tape 220, so that the back surface 232 of the wafer 230 can be disposed on the upper surface 211 of the substrate 210. Tape 2 2 0 will not have the problem of overflowing glue, so the base The board 2 1 0 does not need to reserve the width and further reduces the use area of the substrate 210. The solder lines 240 are electrically connected to the plurality of pads 2 3 3 of the wafer 2 3 and the 7 200839983 connection fingers 213 The solder pads 233 are disposed on one of the active surfaces 23 1 of the wafer 230. The sealant 250 seals the wafer 230 and the bonding wires... and the cost of the diaphragm-shaped adhesive knee strap 220 The waste is achieved by the liquid I and the dispensing, which leads to an increase in the packaging cost. The above-mentioned wire bonding is in the form of a semiconductor sealing structure 2, which can only solve the problem of overflowing and shrinking the substrate. The main purpose of this month is to provide a wire-bonding type semiconductor package structure xe 'by the combination of a line support dam and liquid glue used in wire bonding 5L semiconductor package, limiting the diffusion of liquid glue: The connection of the substrate can be closer to the wafer, and the cost can be as small as 3L ^. Ten will not be the quality of the wire, and the bonding strength and the supporting wire can be increased to avoid the wire being smashed by the mold. u town machine pressure or other The force touches the edge of the chip to cause a short circuit. The invention of the present invention provides a wire-bonding type semiconductor sealing structure, which is used in the wire-drawing field and a plurality of bonding wires to be used in the wire bonding: The combination relationship of the packages makes the maximum arc of the fresh lines and the height of the line supporting the dam, and the design is low-cost and thin, and the quality of the line is not affected, and the utility model is more suitable for multi-wafer stacking. The other purpose is to provide a wire-bonding type semiconductor package structure, which can effectively reduce the base area of the substrate and reduce the cost, and can reduce the thickness of the overall package structure, and the thickness of the package can be beneficial to the semiconductor package. The size of the structure is small. 8 200839983 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a wire bonding type semiconductor package structure mainly comprises a substrate, a liquid adhesive, a first wafer, a plurality of fresh wires, and a wire support dam. The substrate has a die attach region and a plurality of connecting fingers outside the doped region. The liquid adhesive is formed in the die bond region. The first wafer is disposed on the die bond region of the substrate by the liquid adhesive and has a plurality of pads. The bonding wires are electrically connected to the fresh squid and the connecting fingers. The wire support dam is disposed on the substrate and between the die bond region and the connecting fingers, and the liquid adhesive adheres to the first wafer, the substrate and the wire shed dam. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the above-described wire bonding type semiconductor package structure, the wire supporting dam can have a height not lower than the height of the first wafer to prevent the bonding wires from pressing against the edge of the first wafer. In the wire bonding type semiconductor package construction described above, the bonding wires may dam over the wire branch and may be pressed against the wire support to be blocked. In the above-described wire bonding type semiconductor package structure, the wire supporting dam may be selected from one of a dielectric material, a solder resist layer, and a metal material coated with an electrical insulating layer. In the above-described wire bonding type semiconductor package structure, the first wafer system may have an active surface, a back surface, and a plurality of sides between the active surface and the back surface. In the wire bonding type semiconductor package structure described above, the liquid adhesive 9200839983 adhesively adheres to the back surface of the first wafer and adheres along the wire supporting dam to at least one side of the first wafer. In the above-described wire bonding type semiconductor package structure, the liquid adhesive may have a fillet height which is higher than the back surface of the first wafer but lower than the active surface of the first wafer. In the wire bonding type semiconductor package structure, the gap between the line supporting dam and the adjacent side of the first wafer may be approximately equal to the gap between the back surface of the first wafer and the substrate. r In the above-described wire bonding type semiconductor package structure, the solder pads may be arranged adjacent to edges of the active surface of the first wafer. In the above-mentioned wire bonding type semiconductor package structure, the distance between the pads to the active surface may be smaller than the width of the wire support collapse. In the wire bonding type semiconductor package structure described above, a gel may be further included. And sealing the first wafer, the 焊^μ 曰曰 square, the bonding wires and the wire supporting the dam. in
前述的打線連接型半導體封 有至少一第二晶片’其係叠設於該第 在前述的打線連接型半導體封裝 片係可設置於該線支樓攔壩上。 裝構造中，可另包含 一晶片之上方。 構造中，該第二 曰曰 在前述的打線連接型半導體封I 片之尺寸係可大於該第一晶片。 構造中，該第The wire bonding type semiconductor is sealed with at least one second wafer, which is stacked on the wire bonding type semiconductor package sheet, and can be disposed on the wire branch dam. The package structure may additionally include a wafer above it. In the configuration, the second 曰曰 may be larger in size than the first wafer in the wire bonding type semiconductor package. In the structure, the first
在前述的打線連接型半導體封裝構造中，該第 片與遺第—晶片之間係可另形成有 曰曰 液態黏膠 在前述的打線連接型半導體封裝構造中，該些鲜線 10 200839983 係可為逆打銲線，每一銲線係具有一連接於對應連接指 之結球端與一連接於對應銲墊之尾端。 依據本發明揭示另一種打線連接型半導體封裝構 造，主要包含一基板、一黏膠、一晶片、複數個銲線以 及一線支撐攔壩。該基板係具有一黏晶區以及複數個在 該黏晶區之外的連接指。該黏膠係形成於該黏晶區。該 晶片係藉由該黏膠設置於該基板之該黏晶區並具有複 數個銲墊。該些銲線係電性連接該些鋅墊與該些連接 〇 指。該線支撐攔壩係設置於該基板上且在該黏晶區與該 些連接指之間。其特徵在於，該些銲線係為逆打銲線且 該線支撐攔壩係具有一不低於該第一晶片之高度，每一 銲線係具有一連接於對應連接指之結球端與一連接於 對應鲜塾之尾端，該些銲線係接觸至該線支撐攔壩以修 正其銲線形狀，以致使該些銲線之最大弧高處係遠離該 第一晶片並概略相等於該線支撐攔壩之高度。 【實施方式】 I 、依據本發明之第一具體實施例，揭示一種打線連接 变半導體封裝構造。S 3圖係為該打線連接型半導體封 裝構之截面示意圖。第4圖係為該打線連接型半導體封 裝構造透視封膠體之局部俯視圖。 #參閱第3圖所示，一種打線連接型半導體封裝構 造300主要句 Β 基板3 1 〇、一液態黏膠3 2 0、一晶片 330複數個銲線340以及一線支樓攔塌3 50。該基板 310係具有一尺 义寸對應於該晶片3 3 〇之黏晶區（圖中未 11 200839983 繪出）以及複數個在該黏晶區之外的連接指3 1 3。該基板 係具有一上表面3 1 1以及一下表面3 1 2。通常該基板係 為具有雙面導通線路之印刷電路板。該液態黏膠320係 形成於該黏晶區。該液態黏膠320係可為一般習知的環 氧樹脂。 通常該晶片330係為一種具有積體電路的半導體基 板，該晶片330係可具有一主動面331、一背面332以 及複數個在該主動面331與該背面332之間之側面 Ο 334。該晶片330並具有複數個銲墊333，可形成於該 主動面331並作為積體電路之外連接電極。更具體而 言，該些銲墊333係可排列鄰近於該晶片33〇之該主動 面331之邊緣。例如，該些銲墊333至該主動面331之 間距係可小於該線支撐攔壩3 50之寬度（如第4圖所 示）。 能藉由該液態黏膠3 2 0黏接該晶片3 3 0之背面3 3 2， ^ 使該晶片3 3 0設置於該基板3 1 〇之該黏晶區。在本實施 J 例中，該液態黏膠320係除了黏接該晶片33〇之背面 332並沿著該線支撐攔壩350黏接至該晶片33〇之至少 一側面3 3 4，以增加黏晶強度。 利用打線技術，該些銲線340係電性連接該些銲塾 3 3 3與該些連接指313。再參閱第3圖，該些銲線34〇 係可為逆打銲線340，每一銲線34〇係具有一連接於對 應連接指3 1 3之結球端3 4 1與一連接於對應銲墊3 3 3之 尾端342。 12 200839983 此外’該線支撐攔壩3 5 0係設置於該基板3 1 0上且 在該黏晶區與該些連接指3 13之間，並且該液態黏膠 320係黏接該晶片33〇、該基板31〇與該線支撐攔壩 350。該線支樓攔壩35〇係可選自於介電膠材 resin)、再塗施防銲層（rec〇atecj s〇ider mask)與被覆有電 絕緣層之金屬物（metal bar c〇ated with electrically insulating layer)之其中之一，以提供電絕緣性支撐銲線 之功效。在具體結構中，該線支撐攔壩3 5〇係可利用習 知黏晶黟帶的廢料部位多層疊合之後再裁切而成。較佳 地’該線支撐攔壩350係可具有一高度H1，其係不低 於該晶片高度H2，故該些銲線34〇係可跨過該線支撐 攔壩350並可壓觸至該線支撐攔壩35〇，不會使該些銲 線3 4 0壓觸該晶片3 3 0之邊緣而導致短路或訊號干擾。 因此’在上述之打線連接型半導體封裝構造300 中，利用該線支撐攔壩350與該液態黏膠320運用在打 線連接型半導體封裝的組合關係，能將低成本的黏晶材 料運用在微型基板尺寸的封裝產品，該基板310之連接 指313可更加靠近於該晶片330而不會被該液態黏膠 3 20擴散污染。此外，可以增加黏晶強度與提供該些銲 線3 40良好支撐性，避免該些銲線340因模流壓力或其 它外力而碰觸該晶片330之邊緣導致短路。 此外，如第3圖之局部放大圖所示，較佳地，該液 態黏膠320係可具有一溢出高度H3(fillet height)，其 係高於該晶片3 3 0之該背面3 3 2但低於該晶片3 3 0之該 13 200839983 主動面331。即該液態黏膠320之溢出高度H3係不超 過該晶片330之晶片高度H2，不會溢流到該晶片330 之該主動面331，故不會影響該些銲線340之線尾端342 與對應銲塾3 3 3之接合強度。在本實施例中，該線支撲 攔壩350與該晶片33〇之相鄰側面334之間隙係可約相 等於該晶片330之背面332與該基板310之間隙，以利 該液態黏膠3 2 0作上升方向之溢膠流動。 該打線連接型半導體封裝構造3 00可另包含有一封 〇 膠體360，其係密封該晶片330、該些銲線340與該線 支撐攔壩3 50，以形成卡片型態或是塊狀。通常，該封 膠體 360 係為環氧模封化合物（Ep0Xy Molding Compound，EMC)，以轉移成形（transfer mold)技術製成 於該基板3 10上。 此外，本發明之另一明顯功效係能適用於薄型封裝 產品、堆疊更多晶片或是堆疊更大尺寸的晶片，其特徵 ^ 在於該線支撐攔壩3 50與該些銲線340的組合關係。如 第3圖所示，該些銲線340由該線支撐攔壩35〇至對應 連接之銲墊333之間的線段概呈水平，令該些銲線34〇 之最大弧局處係遠離該晶片330並概略相等於該線支 撐攔壩3 5 0之局度，以達到低成本薄型設計而不會影響 打線品質，更可適用於多晶片堆疊。 在本發明之第二具體實施例，揭示另一種打線連接 型半導體封裝構造。請參閱第5圖所示，該打線連接型 半導體封裝構造40 0主要包含—基板41〇、液態黏膠421 14 200839983 與422、一第一晶片430、複數個第一銲線441以及一 線支撐攔壩450。 該基板410係具有一上表面411與一相對之下表面 412。在該上表面411上，該基板410係具有一對應於 該第一晶片4 3 0尺寸之黏晶區（圖未繪出）以及複數個在 該黏晶區之外的連接指4 1 3。該液態黏膠42 1則形成於 該黏晶區。 該第一晶片430係可具有一主動面431、一背面432 〇 以及複數個在該主動面431與該背面432之間之侧面 434。該第一晶片430係藉由該液態黏膠421將其背面 43 2設置於該基板410之該黏晶區並具有複數個第一銲 墊43 3。該些第一銲墊433係可排列於該主動面43 1之 周邊。並利用該些第一銲線441電性連接該些第一銲墊 433與該些連接指413。 該線支撐攔壩450係設置於該基板410上且在該黏 t 晶區與該些連接指4 1 3之間，並且該液態黏膠42 1係黏In the above-described wire-bonding type semiconductor package structure, a liquid-filled liquid adhesive may be additionally formed between the first film and the wafer-to-wafer in the wire bonding type semiconductor package structure, and the fresh wire 10 200839983 may be For the reverse bonding wire, each bonding wire has a ball end connected to the corresponding connecting finger and a tail end connected to the corresponding pad. According to the present invention, another wire bonding type semiconductor package structure is disclosed, which mainly comprises a substrate, a glue, a wafer, a plurality of bonding wires, and a wire supporting dam. The substrate has a die bonding region and a plurality of connecting fingers outside the die bonding region. The adhesive is formed in the die bond region. The wafer is disposed on the die bond region of the substrate by the adhesive and has a plurality of pads. The bonding wires are electrically connected to the zinc pads and the connecting fingers. The wire support dam is disposed on the substrate and between the die bond region and the connecting fingers. The wire bonding wire is a reverse bonding wire and the wire supporting dam has a height not lower than the height of the first wafer, and each wire has a ball end connected to the corresponding connecting finger and one Connected to the tail end of the corresponding fresh squid, the bonding wires are in contact with the wire supporting dam to correct the shape of the wire, such that the maximum arc height of the wire is away from the first wafer and is substantially equal to The line supports the height of the dam. [Embodiment] I. According to a first embodiment of the present invention, a wire bonding variable semiconductor package structure is disclosed. The S 3 diagram is a schematic cross-sectional view of the wire bonding type semiconductor package structure. Fig. 4 is a partial plan view showing the see-through sealing body of the wire bonding type semiconductor package structure. # Referring to Fig. 3, a wire-bonding type semiconductor package structure 300 is mainly composed of a substrate 3 1 〇, a liquid adhesive 3 2 0, a wafer 330, a plurality of bonding wires 340, and a first-line branch collapse 3 50. The substrate 310 has a one-dimensional aperture corresponding to the die bond region of the wafer 3 (not depicted in FIG. 11 200839983) and a plurality of connection fingers 3 1 3 outside the die bond region. The substrate has an upper surface 31 1 and a lower surface 3 1 2 . Typically the substrate is a printed circuit board having double-sided conductive lines. The liquid adhesive 320 is formed in the die bond region. The liquid adhesive 320 can be a conventionally known epoxy resin. Typically, the wafer 330 is a semiconductor substrate having an integrated circuit. The wafer 330 can have an active surface 331, a back surface 332, and a plurality of side surfaces 334 between the active surface 331 and the back surface 332. The wafer 330 has a plurality of pads 333 formed on the active surface 331 and connected to the electrodes as an integrated circuit. More specifically, the pads 333 can be arranged adjacent to the edge of the active surface 331 of the wafer 33. For example, the spacing of the pads 333 to the active surface 331 can be less than the width of the wire support dam 350 (as shown in Figure 4). The wafer 3300 can be disposed on the die bond region of the substrate 3 1 by bonding the liquid adhesive 320 to the back surface 3 3 2 of the wafer 330. In the present embodiment, the liquid adhesive 320 is adhered to the back surface 332 of the wafer 33 and adhered to the at least one side 3 3 4 of the wafer 33 along the line supporting dam 350 to increase adhesion. Crystal strength. The bonding wires 340 are electrically connected to the bonding pads 3 3 3 and the connecting fingers 313 by using a wire bonding technique. Referring to FIG. 3 again, the bonding wires 34 can be reverse bonding wires 340. Each bonding wire 34 has a ball joint end 3 4 1 connected to the corresponding connecting finger 3 1 3 and a connection to the corresponding welding. The end 342 of the pad 3 3 3 . 12 200839983 In addition, the line support dam 350 is disposed on the substrate 310 and between the die bond region and the connecting fingers 3 13 , and the liquid adhesive 320 is bonded to the wafer 33〇 The substrate 31 〇 and the line support the dam 350. The line slab dam can be selected from the dielectric resin, the re-coating layer and the metal bar c〇ated. One of them with an electrically insulating layer) to provide electrical insulation to support the wire. In a specific structure, the line supporting dams can be cut by using multiple layers of waste materials of the conventional squeegee belt. Preferably, the wire support dam 350 can have a height H1 that is not lower than the height H2 of the wafer, so that the wire 34 can support the dam 350 across the wire and can be pressed against the wire The wire supports the dam 35 〇, and does not cause the bonding wires 340 to contact the edge of the wafer 300 to cause short circuit or signal interference. Therefore, in the wire bonding type semiconductor package structure 300 described above, the combination of the wire supporting dam 350 and the liquid adhesive 320 in the wire bonding type semiconductor package can be used for the low cost die bonding material on the micro substrate. For a package of dimensions, the connection fingers 313 of the substrate 310 can be closer to the wafer 330 without being contaminated by the liquid adhesive 3 20 . In addition, the bond strength can be increased and the solder wire 340 can be provided with good support to prevent the solder wires 340 from contacting the edge of the wafer 330 due to the mold flow pressure or other external force to cause a short circuit. In addition, as shown in a partially enlarged view of FIG. 3, preferably, the liquid adhesive 320 can have a fillet height H3 which is higher than the back surface of the wafer 3 3 0 but The 13 200839983 active surface 331 is lower than the wafer 330. That is, the overflow height H3 of the liquid adhesive 320 does not exceed the wafer height H2 of the wafer 330, and does not overflow to the active surface 331 of the wafer 330, so that the wire tail end 342 of the bonding wires 340 is not affected. Corresponding to the joint strength of the welding 塾 3 3 3 . In this embodiment, the gap between the line dam 350 and the adjacent side 334 of the wafer 33 can be approximately equal to the gap between the back surface 332 of the wafer 330 and the substrate 310 to facilitate the liquid adhesive 3. 20 0 is the flow of overflow in the ascending direction. The wire bonding type semiconductor package structure 300 may further include a ruthenium 360 which seals the wafer 330, the bonding wires 340 and the wire supporting dam 350 to form a card type or a block shape. Typically, the sealant 360 is an epoxy molding compound (EMC) and is formed on the substrate 3 10 by a transfer molding technique. In addition, another significant effect of the present invention can be applied to a thin package product, stacking more wafers, or stacking larger sized wafers, characterized by the combination of the wire support dam 350 and the bond wires 340. . As shown in FIG. 3, the wire bonds 340 are horizontally leveled from the line supporting the dam 35 to the correspondingly connected pad 333, so that the maximum arc of the wire 34 is away from the line. The wafer 330 is roughly equal to the degree of the line supporting the dam 350 to achieve a low cost thin design without affecting the quality of the wire, and is more suitable for multi-wafer stacking. In a second embodiment of the present invention, another wire bonding type semiconductor package structure is disclosed. Referring to FIG. 5 , the wire bonding type semiconductor package structure 40 0 mainly includes a substrate 41 , a liquid adhesive 421 14 200839983 and 422 , a first wafer 430 , a plurality of first bonding wires 441 , and a line support bar . Dam 450. The substrate 410 has an upper surface 411 and an opposite lower surface 412. On the upper surface 411, the substrate 410 has a die bond region (not shown) corresponding to the size of the first wafer 430 and a plurality of connection fingers 4 1 3 outside the die bond region. The liquid adhesive 42 1 is formed in the die bond region. The first wafer 430 can have an active surface 431, a back surface 432 〇, and a plurality of sides 434 between the active surface 431 and the back surface 432. The first wafer 430 is disposed on the back surface of the substrate 410 by the liquid adhesive 421 and has a plurality of first pads 43 3 . The first pads 433 are arranged at the periphery of the active surface 43 1 . The first bonding pads 433 and the connecting fingers 413 are electrically connected by the first bonding wires 441. The wire support dam 450 is disposed on the substrate 410 between the adhesive region and the connecting fingers 4 1 3 , and the liquid adhesive 42 1 is adhered
Kj 接該第一晶片430、該基板410與該線支擔棚壩450。 因此，該些第一銲線441將跨過該線支撐攔壩450，配 合該線支撐攔壩450係具有一不低於該第一晶片430之 主動面431之高度，故能使該線支撐攔壩450能發揮支 撐銲線的功能，以避免該些第一銲線44 1壓觸該第一晶 片4 3 0之邊緣。 該打線連接型半導體封裝構造40 0可另包含有一封 膠體460，其係至少密封該第一晶片430、該些第一銲 15 200839983 線441與該線支撲攔壩450。當該些第一銲線441 該線支樓搁壩450，部份之該些第一銲線441係可 至該線支撐攔壩450，以維持銲線弧高的最小限定 不會受到形成該封膠體460的模流壓力引發該些 銲線441的下沉或左右位移。 較佳地，該液態黏膠42 1係可黏接該第一晶片 之背面432並沿著該線支撐攔壩45〇黏接至該第一 430之至少一側面434，但較低於該第一晶片43〇 ^ 主動面431。藉此’提供一低成本解決方案來增進 強度並符合基板微小化之要求。 此外，在本實施例中，該打線連接型半導體封 造400可另包含至少一第二晶片470，其係疊設於 一曰曰片430之上方。該第二晶片470係具有複數個 銲墊471，可利用複數個打線形成之第二銲線442 連接該些第二銲墊471與該些連接指413。較佳地 第二晶片470係可設置於該線支撐攔壩450上，故 〇 x 二晶片470之尺寸係可大於該第一晶片430。再者 該第一晶片430與該第二晶片470之間係可另形成 液態黏膠422，以低成本黏接該第二晶片470並具 佳的膠填充特性。 以上所述，僅是本發明的較佳實施例而已，並 本發明作任何形式上的限制，雖然本發明已以較佳 例揭露如上，然而並非用以限定本發明，任何熟悉 業的技術人員，在不脫離本發明技術方案範圍内， 跨過 壓觸 值， 第一 43〇 晶片 之該 黏晶 裝構 該第 第二 電性 ，該 該第 ，在 有一 有較 非對 實施 本專 當可 16 200839983 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 谷，依據本發明的技術實質對以上實施例所作的任何簡 早修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 ’、 【圖式簡單說明】 第1圖··一種習知打線連接型半導體封裝構造之截面示 意圖。 0第2圖：另-種習知打線連接型半導體封裝構造之截面 示意圖。 第3圖：依據本發明之第一具體實施例，一種打線連接 型半導體封裝構造之截面示意圖。 第4圖：依據本發明之第一具體實施例，該打線連接型 半導體封裝構造透視封膠體之局部俯視圖。 第5圖：依據本發明之第二具體實施例，另一種打線連 f 接型半導體封裝構造之截面示意圖。 【主要元件符號說明】 100 打線連接型半導體封裝構造 110 基板 111 上表面 112 下表面 113 連接指 120 液態黏膠 130 晶片 131 主動面 132 背面 133 銲墊 140 銲線 150 封膠體 200 打線連接型半導體封裝構造 210 基板 211 上表面 212 下表面 17 200839983 213 連接指 220黏晶膠帶 230 晶片 231主動面 232 背面 233 銲墊 240銲線 250 封膠體 300 打線連接型半導體封裝構造 3 10 基板 311上表面 312 下表面 313 連接指 320液態黏膠 330 晶片 331主動面 V 332 背面 333 銲墊 334側面 340 銲線 341結球端 342 結尾端 350 線支撐攔壩 360封膠體 400 打線連接型半導體封裝構造 410 基板 4 11上表面 413 連接指 421 液態黏膠 422液態黏膠 430 第一晶片 431主動面 432 背面 433 第一銲塾 4 3 4側面 441 第一銲·線 442第二銲線 450 線支撐攔壩 460封膠體 470 第二晶片 471第二銲墊 HI 線支撐攔壩 南度 Η2 晶片南 H3 溢出高度 18Kj is connected to the first wafer 430, the substrate 410 and the line supporting dam 450. Therefore, the first bonding wires 441 will support the dam 450 across the wire, and the wire supporting dam 450 has a height not lower than the active surface 431 of the first wafer 430, so that the wire can be supported. The dam 450 can function as a support wire to prevent the first wire 44 1 from pressing against the edge of the first wafer 430. The wire bonding type semiconductor package structure 40 may further include a glue 460 which seals at least the first wafer 430, the first solder 15 200839983 line 441 and the wire dam 450. When the first bonding wires 441 are the wire branch dam 450, some of the first bonding wires 441 can support the dam 450 to maintain the minimum limit of the arc height of the bonding wire. The mold flow pressure of the sealant 460 causes the sinking or left and right displacement of the bonding wires 441. Preferably, the liquid adhesive 42 1 is adhered to the back surface 432 of the first wafer and adhered to the at least one side 434 of the first 430 along the line supporting dam 45 ,, but lower than the first A wafer 43 〇 ^ active surface 431. This provides a low-cost solution to increase strength and meet the requirements for substrate miniaturization. In addition, in the present embodiment, the wire bonding type semiconductor package 400 may further include at least one second wafer 470 which is stacked above a die 430. The second wafer 470 has a plurality of pads 471, and the second pads 442 formed by a plurality of wires are connected to the second pads 471 and the connecting fingers 413. Preferably, the second wafer 470 can be disposed on the wire support dam 450, so the 〇 x two wafer 470 can be larger than the first wafer 430. Furthermore, a liquid adhesive 422 can be formed between the first wafer 430 and the second wafer 470 to bond the second wafer 470 at a low cost and has good glue filling characteristics. The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above, but the present invention has been described above by way of a preferred example, and is not intended to limit the present invention. The second electrical property of the first 43 〇 wafer is configured to span the pressure contact value without departing from the technical solution of the present invention, and the second electrical property may be used in a non-practical manner. 16 200839983 The equivalents of the above-described embodiments are used to make some modifications or modifications to equivalent embodiments, but any modifications made to the above embodiments in accordance with the technical spirit of the present invention without departing from the technical solution of the present invention. Equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional wire bonding type semiconductor package structure. 0 Fig. 2 is a schematic cross-sectional view showing another conventional wire-bonding type semiconductor package structure. Figure 3 is a cross-sectional view showing a wire bonding type semiconductor package structure in accordance with a first embodiment of the present invention. Figure 4 is a partial plan view of the wire bonding type semiconductor package structure see-through sealant in accordance with a first embodiment of the present invention. Figure 5 is a cross-sectional view showing another wire-bonding type f-type semiconductor package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 100 wire-bonding type semiconductor package structure 110 substrate 111 upper surface 112 lower surface 113 connection finger 120 liquid adhesive 130 wafer 131 active surface 132 back surface 133 solder pad 140 bonding wire 150 sealing body 200 wire-bonding type semiconductor package Structure 210 Substrate 211 Upper Surface 212 Lower Surface 17 200839983 213 Connecting Finger 220 Bonding Tape 230 Wafer 231 Active Surface 232 Back 233 Pad 240 Bonding Wire 250 Sealing Body 300 Wire Bonding Type Semiconductor Package Structure 3 10 Substrate 311 Upper Surface 312 Lower Surface 313 connection finger 320 liquid adhesive 330 wafer 331 active surface V 332 back 333 solder pad 334 side 340 bond wire 341 ball end 342 end end 350 line support dam 360 sealant 400 wire connection type semiconductor package structure 410 substrate 4 11 upper surface 413 connection finger 421 liquid adhesive 422 liquid adhesive 430 first wafer 431 active surface 432 back 433 first solder 塾 4 3 4 side 441 first solder wire 442 second wire 450 wire support dam 460 sealant 470 Two wafer 471 second solder pad HI line support Dam South Η 2 wafer South H3 overflow height 18