1330463 九、發明說明： 【發明所屬之技術領域】 本案係有關於一種電壓準位移位器（v〇ltage level . shifter)。 w 【先前技術】 傳統的電壓準位移位器為雙相位電壓準位移位器， 具有兩個彼此反相（anti-phased)的輸入端。該種雙相位電 % 壓準位移位器必須同時接收一輸入信號以及該輸入信號 之反相信號，方能將該輸入信號之電壓準位移位。 第1圖圖解此種雙相位電壓準位移位器1〇2，所採 用的一第一電壓源與一第二電壓源分別為Vdd與Vss，並 且具有兩個彼此為反相的輸入端IN與χΐΝ。一輸入信號 • 與其反相信號分別經由上述輸入端IN與：XIN輸入該雙相 位電壓準位移位器1〇2。經由該雙相位電壓準位移位器 102處理後，該輸入信號之電壓準位會由原來的第一準位 參 Vl與第二準位Vh移位至該第一與第二電壓源之電壓準 位（vss與vDD)。舉例說明之，假設該第一準位為〇v、該 第二準位為3V、該第一電壓源VDD之電壓準位為8 5V、 並且該第二電壓源Vss之電壓準位為〇V，則經由該雙相 位電壓準位移位器1 〇2處理後，該輸入信號之電壓準位 會由原來的〇V、3V移位至0V、8.5V。 為了節省晶片輸入端的個數並且降低晶片封I的成 本’本發明將揭露一種新穎的電壓準位移位p，僅♦要 0773-A32580TWF;P2006047;glorious_tien 6 1330463 單一個輸入端即可移位一輸入信號的電壓準位。 【發明内容】 .本發明提供一種新穎的電壓準位移位器（voltage level shifter)。本發明所提供的電壓準位移位器為單相位 電壓準位移位器。傳統的電壓準位移位器需要兩個輸入 端接收一輸入信號與該輸入信號之反相信號。本發明僅 需要單一個輸入端接收一輸入信號，即可移位該輸入信 φ 號的電壓準位。 本發明所提供的電壓準位移位器包括一第一電晶 體、一第一阻抗模組、以及一偏壓產生電路。該第一電 晶體之源極耦接一輸入信號。該輸入信號之電位於一第 二準位與一第二準位兩者間變換。該第一阻抗模組耦接 該第一電晶體之汲極至一第一電壓源。該偏壓產生電路 產生一第一偏壓耦接該第一電晶體之閘極，以偏壓該第 一電晶體。其中，當該輸入信號之電位為該第一準位時， _該第-電晶體導通’使得該第—電晶體之及極所輸出的 電壓趨近該第一準位。當該輸入信號之電位為該第二準 位時，該第一電晶體不導通，並且該第一阻抗模組會令 邊第一電晶體之汲極所輸出的電壓趨近該第一電壓 準位。 ” 為讓本發明之上述和其他㈣、特徵、和優點能更 月顯易It T文特舉出較佳實施例，並配合所附圖式 詳細說明。 0773-A32580TWF;P2O06047;gl〇ri〇uSjien 1330463 【實施方式】 第2圖圖解本發明所提供的電壓準位移位器的一實 • 施例，此種電壓準位移位器為單相位電壓準位移位器。 ，此單相位電壓準位移位器2〇2所採用的一第一電壓源與 一第二電壓源分別為Vdd與Vss。該單相位電壓準位移位 态202僅具有單一個輸入端m。一輸入信號經由上述輸 入端1N輸入該單相位電壓準位移位器202。該輸入信號 • 在一第一準位VL與第二準位VH兩者間變換。該單相位 電壓準位移位器202僅需接收該輸入信號即可移位該輸 入信號之電壓準位。如第2圖所示之實施例，假設該第 一準位為ον、該第二準位為3V、該第一電壓源Vdd為 8.5V、並且該第二電壓源Vss為〇v，則經由該單相位電 .壓準位移位器202處理後，該輸入信號之電壓準位會由 〇V、3V 移位至 〇v、8.5V。 第3圖為本發明的一實施例。一電壓準位移位器3〇〇 φ 包括一第一電晶體、一第一阻抗模組304、以及一偏 壓產生電路302。一輸入信號由一輸入端IN耦接至該第 一電晶體Μ1的源極。該輸入信號之電位於一第一準位 Vl與一第二準位VH兩者間變換。該第一阻抗模組304 搞接5亥第一電晶體之汲極308至一第一電壓源vDD。該 偏壓產生電路302產生一第一偏壓Vbiasl耦接該第一電晶 體之閘極，以偏壓該第一電晶體Μ】。當該輸入信號 之電位為該第一準位VL時，該第一電晶體Ml導通，使 0773-A32580TWF;P2006047;glorious tien δ 1330463 得該第一 t晶體之沒極308所輸出的電壓趨近該第一準 位vL。當該輸入信號之電位為該第二準位Vh時，該第 -電晶體M!不導通，並且該第一阻抗模組3〇4會令該第 一電晶體之汲極308所輸出的電壓趨近該第一電壓源 VDD。如第3圖所示，準位為\與Vh的輸入信號由該輸 入端IN輸入該電壓準位移位器3〇〇後，其準位會移位至 Vl與VDD ’由輸出端〇υτ輸出。 第4圖為第一阻抗模組3 〇4的一實施方式。第4圖 為一 PM0S串聯模組，其中包括複數個以亊聯形式連接 的P型金氧半電晶體。該等p型金氧半電晶體之閘極皆 耦接一第二偏壓，以令該等p型金氧半電晶體恆為導通。 若將第4圖所示之電路應用在第3圖中’則該電路之源 極端點S耦接該第一電壓源vDD，並且該電路之汲極端 點D耦接該第一電晶體之汲極308。 在本發明的另一實施例’該第一電晶體可改用p型 金氧半電晶體。此時所使用的第一阻抗模組可改用複數 個N型金氧半電晶體所串接而成的一 nm〇s串聯模組。 任何一種元件，只要其導通或不導通乃由一輸入信 破控制、並且在導通時會將該輸入信號由該元件的一端 傳導至另一端’即可用來取代該第一電晶體功能。 第5圖為本發明的一實施例。一電壓準位移位器500 所採用的第一電晶體Μι為N型金氧半電晶體、第一阻抗 輪組512為第4圖所示之PM0S串聯模組（閘極端耦接一 第二偏壓Vbias2，以確保該PMOS串聯模組恆為導通）、 °773-A32580TWF;P2006047;gl〇ri〇us tien 9 1330463 並且偏壓產生電路502包括一第二電曰 阻抗模請。該第二_M2二日日在體二：及^ 阻抗模組504串接該第二電 該第- N型金氧半電晶體實現兮第1日二之〉及極。此實施例以 μ第一電晶體Μ，並且岡 f_S串聯模組(閉極端輕接-第三偏壓Vb = PM〇S串聯模組值為導通）實現該第二1ΐ抗模组 ⑽。如圖所示，上述第二阻抗模組5〇4與該第二=體且 Μ2串接於該第一電壓源一電曰日一 斗# ^ 、弟—電昼源vss之間。 广電晶體之間極506㈣壓準位即該第一偏壓 vbiasl ° 以下舉例說明第5圖之實施例。—輸 -準位…。v)與一第二準位(Vh=3v)兩者間變：在並： =壓產生電路5G2所產生的—第—偏壓為I 该弟-電晶體⑷會在該輸入信號為該第—準位化州 時導通’導致該第-電晶體之祕所輸出的信號之 電塵準位趨近VL(0V)。當該輸入信號為該第二準位 (Vh=3V)時’該第-電晶體M】不導通’並且該第一阻抗 模組512會令該第-電晶體之沒極谓所輸出的信號之 電準位趨近VDD(8.5V)。準位為乂與Vh的輸入信號由 該輸入端IN輸入該電壓準位移位器5〇〇後，其準位會移 位至VL與VDD，由輸出端〇υτ輸出。 第5圖之偏壓產生電路5〇2亦可改由任何可以產生 該第一偏壓vbiasl的電路實現。 第6圖為本發明另一實施例。與上述電壓準位移位 0773-A32580TWF;P2006047;glorious_tien 1330463 純，此電壓準位移位器_之第：阻抗模組6〇2 mUf G乃轉接至該電塵準位移位器_之輸入端 tur、接上述第三偏壓Vbias3。該電壓準位移位器600 二;f準位移位器500省電，舉例說明如下。假設上 =準位vL為ov、第二準位^為…、第一電壓源 DD為8.5V、並且第二電壓源Vss為〇v。另外假設第$ =之第三偏肢為GV。比較第5、6圖，當該輸入信號 為遠第一準位Vl(〇V)時’上述第二阻抗模組（504與602) 之閉極端G皆為0V’因此耗電量差不多。但是，當該輸 入信號為該第二準位Vh(3v)時，該第二阻抗模組之 閘極端G為3V，其源極端s與閘極端G的壓差為 8.5^3 5.5V ’較该第二阻抗模組5〇4之源極端s與閘極端 G壓差（8.5-0=8.5V)小。因此，該第二阻抗模組6〇2在該 輸入信號為該第二準位Vh(3V)時耗費較少的電流。此 外，第6圖實施例還有另外一樣優點：可以更加確實地 不導通該第一電晶體Μ〗。在該輸入信號為該第二準位 Vh(3V)時’該第二阻抗模組602之閘極端g為3V，將造 成該第二阻抗模組602之汲極端D電壓低於本來預期的 第一偏壓Vbiasl(3V)，導致該第一電晶體Μι更確實地為 不導通。 第7圖為本發明的另外一種實施例。與第3圖相較， 此電壓準位移位器700更包括至少一反相器7〇2。其輸入 端轉接該第一電晶體Mi之汲極（704)。該反相器702可將 端點704之電壓確實地移位至該第一電壓準位vDD或該 0773-A32580TWF;P2006047;glorious_tien 11 1330463 第二電壓準位Vss。如圖所示，此反相器702可為互補式 金氧半反相器（CMOS inverter)。 第8圖為圖解本發明所揭露的一影像顯示系統之實 施例，該影像顯示系統可為一面板驅動電路804或一電 子裝置800。本發明所揭露的一電壓準位移位器802(其實 施方式詳訴於上述第3-7圖的說明例中）可整合在該面板 驅動電路804中。該面板驅動電路804可用來組成該電 子裝置800的一部分。通常，該電子裝置800包括一面 • 板806與該面板驅動電路804。該面板驅動電路804與該 面板806搞接在一起，用以驅動該面板806顯示影像。 該電子裝置800可為一行動電話、一數位攝影機、一個 人數位助理、一行動電腦、一桌上型電腦、一電視、一 車上型螢幕、或一行動式光碟撥放裝置…等。 本發明雖以較佳實施例揭露如上，然其並非用以限 定本發明的範圍，任何熟習此項技藝者，在不脫離本發 明之精神和範圍内，當可做些許的更動與潤飾，因此本 • 發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 第1圖圖解傳統的雙相位電壓準位移位器； 第2圖圖解本發明之單相位電壓準位移位器； 第3圖為本發明之電壓準位移位器之實施例； 第4圖為一阻抗模組之實施例； 0773-A32580TWF;P2006047;glorious_tien 12 1330463 第5圖為本發明之電壓準位移位器的另一實施例； 第6圖為本發明之電壓準位移位器的另一實施例； 第7圖為本發明之電壓準位移位器的另一實施例； 第8圖圖解本發明之影像顯示系統的一實施例。 【主要元件符號說明】1330463 IX. Description of the invention: [Technical field to which the invention pertains] This case relates to a voltage quasi-positioner (v〇ltage level. shifter). w [Prior Art] The conventional voltage-aligned positioner is a two-phase voltage quasi-displacer with two anti-phased inputs. The dual phase electric % level shifter must simultaneously receive an input signal and an inverted signal of the input signal to accurately shift the voltage of the input signal. Figure 1 illustrates such a dual phase voltage level shifter 1〇2, a first voltage source and a second voltage source are respectively Vdd and Vss, and have two input terminals IN which are opposite to each other. With χΐΝ. An input signal • The inverted signal is input to the two-phase voltage level shifter 1〇2 via the input terminals IN and XIN, respectively. After being processed by the dual-phase voltage quasi-positioner 102, the voltage level of the input signal is shifted from the original first level parameter V1 and the second level Vh to the voltages of the first and second voltage sources. Level (vss and vDD). For example, assume that the first level is 〇v, the second level is 3V, the voltage level of the first voltage source VDD is 85 V, and the voltage level of the second voltage source Vss is 〇V. Then, after the double-phase voltage quasi-displacer 1 〇 2 is processed, the voltage level of the input signal is shifted from the original 〇V, 3V to 0V, 8.5V. In order to save the number of wafer input terminals and reduce the cost of the wafer package I, the present invention will disclose a novel voltage quasi-displacement bit p, which only needs to be 0773-A32580TWF; P2006047; glorious_tien 6 1330463, one input can be shifted by one The voltage level of the input signal. SUMMARY OF THE INVENTION The present invention provides a novel voltage level shifter. The voltage quasi-positioner provided by the present invention is a single phase voltage quasi-positioner. Conventional voltage level shifters require two inputs to receive an input signal and an inverted signal of the input signal. The invention only needs to receive an input signal from a single input terminal, and can shift the voltage level of the input signal φ. The voltage quasi-positioner provided by the present invention comprises a first electromorph, a first impedance module, and a bias generating circuit. The source of the first transistor is coupled to an input signal. The input signal is electrically coupled between a second level and a second level. The first impedance module is coupled to the drain of the first transistor to a first voltage source. The bias generating circuit generates a first bias coupled to the gate of the first transistor to bias the first transistor. Wherein, when the potential of the input signal is the first level, the first transistor is turned on so that the voltage output from the sum of the first transistors approaches the first level. When the potential of the input signal is the second level, the first transistor is not turned on, and the first impedance module causes the voltage outputted by the drain of the first transistor to approach the first voltage level. Bit. The above and other (four), features, and advantages of the present invention will be described in detail with reference to the accompanying drawings in detail. FIG. uSjien 1330463 [Embodiment] FIG. 2 illustrates a practical embodiment of a voltage quasi-positioner provided by the present invention. The voltage quasi-positioner is a single-phase voltage quasi-displacer. A first voltage source and a second voltage source used by the phase voltage quasi-displacer 2 〇 2 are Vdd and Vss, respectively. The single-phase voltage quasi-displacement state 202 has only a single input terminal m. An input signal is input to the single-phase voltage quasi-bit shifter 202 via the input terminal 1N. The input signal is converted between a first level VL and a second level VH. The single-phase voltage level The shifter 202 only needs to receive the input signal to shift the voltage level of the input signal. As in the embodiment shown in FIG. 2, it is assumed that the first level is ον and the second level is 3V. The first voltage source Vdd is 8.5V, and the second voltage source Vss is 〇v, then the single-phase electric pressure level is passed. After the shifter 202 processes, the voltage level of the input signal is shifted from 〇V, 3V to 〇v, 8.5V. Fig. 3 is an embodiment of the invention. A voltage quasi-positioner 3〇〇 φ includes a first transistor, a first impedance module 304, and a bias generating circuit 302. An input signal is coupled to the source of the first transistor 由1 by an input terminal IN. The input signal is electrically The first impedance module 304 is connected to the drain 308 of the first transistor of the first circuit and the first voltage source vDD. The bias voltage is generated. The circuit 302 generates a first bias voltage Vbias1 coupled to the gate of the first transistor to bias the first transistor. When the potential of the input signal is the first level VL, the first The crystal M1 is turned on to make 0773-A32580TWF; P2006047; glorious tien δ 1330463, and the voltage outputted by the pole 308 of the first t crystal approaches the first level vL. When the potential of the input signal is the second level When Vh, the first transistor M! is not turned on, and the first impedance module 3〇4 causes the drain of the first transistor to be 308 The voltage approaches the first voltage source VDD. As shown in Fig. 3, after the input signal of the level \ and Vh is input to the voltage level shifter 3 by the input terminal IN, the level shifts. Bits V1 and VDD' are outputted by the output terminal 〇υτ. Fig. 4 is an embodiment of the first impedance module 3 〇4. Fig. 4 is a PM0S series module including a plurality of connected in a cascading manner. P-type MOS transistors, the gates of the p-type MOS transistors are coupled to a second bias to keep the p-type MOS transistors on. If the circuit shown in FIG. 4 is applied in FIG. 3, then the source terminal S of the circuit is coupled to the first voltage source vDD, and the 汲 extreme point D of the circuit is coupled to the first transistor. Extreme 308. In another embodiment of the present invention, the first transistor can be replaced with a p-type MOS transistor. The first impedance module used at this time can be replaced by a series of nm 〇s series modules in which a plurality of N-type MOS transistors are connected in series. Any of the elements can be used to replace the first transistor function as long as it is turned on or off, controlled by an input signal, and is conducted from one end of the element to the other end when turned on. Figure 5 is an embodiment of the present invention. The first transistor used in a voltage level shifter 500 is an N-type MOS transistor, and the first impedance wheel group 512 is a PMOS series module shown in FIG. 4 (the gate terminal is coupled to a second The bias voltage Vbias2 is ensured that the PMOS series module is always turned on, °773-A32580TWF; P2006047; gl〇ri〇us tien 9 1330463 and the bias generating circuit 502 includes a second electrical impedance mode. The second _M2 is on the second day of the second body: and the impedance module 504 is connected in series with the second electric power. The first-N-type MOS transistor is realized on the first day and the second pole. In this embodiment, the second first anti-module (10) is realized by μ first transistor Μ, and the gang f_S series module (closed extreme light connection - third bias Vb = PM 〇 S series module value is turned on). As shown in the figure, the second impedance module 5〇4 and the second body 且2 are connected in series between the first voltage source, the electric power source, and the electric power source vss. The pole 506 (four) pressure level between the transistors is the first bias voltage vbiasl °. The embodiment of Fig. 5 is exemplified below. - Loss - Level... v) and a second level (Vh = 3v) change between: and: = pressure generated by the voltage generating circuit 5G2 - the first bias is I, the younger - the transistor (4) will be at the input signal - Conducting the state to conduct 'the electric dust level of the signal outputted by the secret of the first transistor is close to VL (0V). When the input signal is the second level (Vh=3V), the 'the first transistor M is not turned on' and the first impedance module 512 causes the signal of the first transistor to be outputted. The power level approaches VDD (8.5V). After the input signal of the level 乂 and Vh is input to the voltage level shifter 5〇〇 by the input terminal IN, the level is shifted to VL and VDD, and outputted by the output terminal 〇υτ. The bias generating circuit 5〇2 of Fig. 5 can also be implemented by any circuit that can generate the first bias voltage vbiasl. Figure 6 is another embodiment of the present invention. With the above voltage quasi-displacement bit 0773-A32580TWF; P2006047; glorious_tien 1330463 pure, the voltage quasi-displacer _ the: impedance module 6〇2 mUf G is transferred to the electric dust quasi-positioner _ The input terminal tur is connected to the third bias voltage Vbias3. The voltage quasi-bit shifter 600 2; f quasi-displacer 500 saves power, as illustrated below. Assume that the upper level vL is ov, the second level is ..., the first voltage source DD is 8.5V, and the second voltage source Vss is 〇v. Also assume that the third limb of the $= is the GV. Comparing Figures 5 and 6, when the input signal is far first level V1 (〇V), the closed extremes G of the second impedance modules (504 and 602) are both 0V', so the power consumption is similar. However, when the input signal is the second level Vh(3v), the gate terminal G of the second impedance module is 3V, and the voltage difference between the source terminal s and the gate terminal G is 8.5^3 5.5V' The source terminal s of the second impedance module 5〇4 is smaller than the gate terminal G (8.5-0=8.5V). Therefore, the second impedance module 6〇2 consumes less current when the input signal is the second level Vh (3V). In addition, the embodiment of Fig. 6 has the additional advantage that the first transistor can be more reliably not turned on. When the input signal is the second level Vh (3V), the gate terminal g of the second impedance module 602 is 3V, which will cause the 汲 extreme D voltage of the second impedance module 602 to be lower than originally expected. A bias voltage Vbiasl (3V) causes the first transistor Μ to be more positively non-conductive. Figure 7 is another embodiment of the present invention. Compared with FIG. 3, the voltage quasi-bit shifter 700 further includes at least one inverter 7〇2. Its input terminal switches the drain of the first transistor Mi (704). The inverter 702 can positively shift the voltage of the terminal 704 to the first voltage level vDD or the 0773-A32580TWF; P2006047; glorious_tien 11 1330463 second voltage level Vss. As shown, this inverter 702 can be a complementary CMOS inverter. FIG. 8 is a diagram illustrating an embodiment of an image display system disclosed in the present invention. The image display system can be a panel drive circuit 804 or an electronic device 800. A voltage level shifter 802 (which is described in detail in the above description of FIGS. 3-7) disclosed in the present invention can be integrated in the panel driving circuit 804. The panel drive circuit 804 can be used to form part of the electronic device 800. Typically, the electronic device 800 includes a side panel 806 and the panel drive circuit 804. The panel driving circuit 804 is coupled to the panel 806 for driving the panel 806 to display an image. The electronic device 800 can be a mobile phone, a digital camera, a number of assistants, a mobile computer, a desktop computer, a television, a car-mounted screen, or a mobile CD player. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection of this invention is defined in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a conventional two-phase voltage quasi-displacer; FIG. 2 illustrates a single-phase voltage quasi-displacer of the present invention; FIG. 3 is a voltage quasi-displacement bit of the present invention. Embodiment of the device; FIG. 4 is an embodiment of an impedance module; 0773-A32580TWF; P2006047; glorious_tien 12 1330463 FIG. 5 is another embodiment of the voltage quasi-positioner of the present invention; Another embodiment of the voltage quasi-displacer of the present invention; Fig. 7 is another embodiment of the voltage quasi-positioner of the present invention; and Fig. 8 illustrates an embodiment of the image display system of the present invention. [Main component symbol description]
302〜偏壓產生電路； 308〜節點； 502〜偏壓電路； 506、508〜節點； 600〜電壓準位移位器； 700〜電壓準位移位器； 704〜節點； 802〜電壓準位移位器； 102〜雙相位電壓準位移位器 202〜單相位電壓準位移位器 300〜電壓準位移位器； 304〜第一阻抗模組； 500〜電壓準位移位器； 504〜第二阻抗模組； 512〜第一阻抗模組； 602〜第二阻抗模組； 702〜反相器； 800〜電子裝置；302~bias generating circuit; 308~node; 502~biasing circuit; 506, 508~node; 600~voltage quasi-bit shifter; 700~voltage quasi-bit shifter; 704~node; 802~voltage Bit shifter; 102~double phase voltage quasi-bit shifter 202~ single phase voltage quasi-bit shifter 300~voltage quasi-displacer; 304~first impedance module; 500~voltage quasi-displacement bit 504~second impedance module; 512~first impedance module; 602~second impedance module; 702~inverter; 800~electronic device;
804〜面板驅動電路； 806〜面板； 0、0、3〜分別為？1\403串聯模組之汲極端、閘極端 源極端； IN〜電壓準位移位器之輸入端，用以輸入一輸入信 號；804~ panel driver circuit; 806~ panel; 0, 0, 3~ respectively? 1\403 series module 汲 extreme, gate extreme source extreme; IN ~ voltage quasi-bit shifter input, used to input an input signal;
Mi〜第一電晶體； M2〜第二電晶體； OUT〜電壓準位移位器之輸出端； XIN〜電壓準位移位器之輸入端，用以輸入一輸入信 0773-A32580TWF;P2006047;glorious_tien 13 1330463 號之反相信號； Vbiasl〜第一偏壓； Vbias2 广 vbias3〜第三偏壓； V〇D~ J VH~第二準位； VL〜第 vss〜第二電壓源。 -第二偏壓； I 一電壓源； 一準位；Mi ~ first transistor; M2 ~ second transistor; OUT ~ voltage quasi-bit shifter output; XIN ~ voltage quasi-bit shifter input, for inputting an input letter 0773-A32580TWF; P2006047; Glorious_tien 13 1330463 inverted signal; Vbiasl ~ first bias; Vbias2 wide vbias3 ~ third bias; V 〇 D ~ J VH ~ second level; VL ~ v vss ~ second voltage source. - a second bias voltage; I a voltage source; a level;
0773-A32580TWF;P2006047;glorious_tien 140773-A32580TWF; P2006047; glorious_tien 14