TWI328356B - Successive approximation adc with binary error tolerance mechanism - Google Patents

Description

1328356 IX. Description of the Invention: [Technical Field] The present invention relates to analog to digital converters (ADCs), and more particularly to a progressive approximation register (SAR) analog to digital converter with binary error tolerance mechanism. [Prior Art] Analog-to-digital converters (ADCs) have a variety of architectures, such as flash, pipelined, and gradual approximation, which are frequently used architectures. Each of these architectures has its own advantages and is often chosen for different application needs. Among them, the progressive approximation ADC consumes lower power, smaller area and lower cost than other architectures. However, this architecture requires more clock cycles to produce output and is therefore less advantageous for high speed operation. Gradual approximation ADCs are mainly divided into two ways: binary approximation and non-binary approximation. Binary approximation ADC technology, such as Hao-CHiao Hong' Guo-Ming Lee αΑ 65-fJ/Conversion-step 0.9-V 200-KS/s Rail-to-Rail 8-bit Successive

Approximation ADC", IEEE J. Solid-State Circuits, vol. 42, Oct. 2007, pp. 2161-2168, whose 1328356 uses a digital to analog converter (DAC) to gradually approximate the sampled signal and according to the comparator The result of the comparison determines whether the next state is a voltage applied upwards or downwards, and the amount of voltage changed each time gradually decreases by a power of two. In this binary search mode, the operation is repeated several times to obtain a corresponding Digital code output. Binary approximation ADC technology is also revealed in Cranenckx' G. van der Plas UA 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-sharing SAR Spring ADC in 90nm Digital CMOS" , ISSCC Dig. Tech. Papers, February 2007, pp. 246-247, the same application

However, the amount of charge is increased or decreased according to the difference in the amount of charge across the comparators, and the amount of charge changed each time is also gradually reduced by a power of two. The operation is repeated several times in this binary search mode until the corresponding digital code output is obtained. The above two methods of binary approximation will be limited in speed. The main reason is that the voltage across the comparator or the Lu charge must be stable to less than 1 /2 LSB (ie, i/2N+1 where N is the resolution of the ADC). ) 'The comparator can perform the comparison action, otherwise it will cause sampling error. Non-binary approximation ADC techniques, such as F. Kuttner "A 12-v l〇-b 20-Msample/s nonbinary successive approximation ADC in 0.13_m CMOS", IEEE Int. 1328356.

Solid-State Circuits Conf. Dig. Tech. Papers » 2002 > PP. 176-m. Unlike the binary approximation method, the non-binary approximation method does not approximate the power of two, but gradually decreases with a power of 185. This method has an error tolerance of approximately 12.7%, so samples can be sampled without a stable signal, which can shorten each clock cycle time; however, additional and complex digital correction mechanisms need to be added. Whether implemented in logic or Xinwei read memory, power and circuit area are required. In view of the shortcomings of the traditional approach to the ADC architecture, it is imperative to propose a new ADC architecture to maintain the traditional advantages of the architecture and avoid its shortcomings. SUMMARY OF THE INVENTION The above and the object of the present invention is to propose a progressive approximation ADC' which uses an error tolerance mechanism and a non-binary approximation method with high speed and binary error correction mechanism. A progressive approximation analog to digital converter (ADC) according to an embodiment of the invention' - an internal digital to analog converter (Mc) comprising a capacitor array having a capacitance value having a binary weight and at least - a compensation capacitor configuration In the binary right: the electric swallows the field. The comparator receives and compares the sample input signal and the DAC round trip. Non 1328356 • The hexadecimal approximation control circuit controls the sampling of the input signal and controls a series of comparisons based on the comparison of the comparators. When the signal or charge of the DAC is not fully known (for example, stable to at least two bits), the control circuit is gradually controlled to control the comparison. The binary error tolerance corrector compensates for the sampling error caused by the comparator. [Embodiment] The first figure shows a schematic diagram of an octet approximation analog-to-digital converter (SARADC). First, an input of the comparator 1 (eg, a non-inverting input) receives the sampled input signal Vin; and an internal digit connected to the other input (eg, the inverting input) to the analog converter (DAC) is heavily Reset is the common mode voltage Vcm. As shown, the DAC consists of a capacitor array (C7 to C0) with a binary specific gravity • (weight). Next, the comparator 1 compares the input signal Vin with the common mode voltage Vcm to determine whether to add or subtract the v/4 voltage to the DAC (where v is the amplitude of the input sK number). When the DAC has stabilized, the next comparison and decision is made. Continue this operation until the input signal is approximated as:

Vcm±V/4±V/8±V/16±V/32±V/64±V/1281V/256 (where V is the amplitude of the input signal) 1328356 I * The second figure shows the binary with the embodiment of the present invention Single-ended progressive approximation ADC with error tolerance mechanism. Although the present embodiment is exemplified by an octet ADC, the present invention is generally applicable to an n-bit ADC. In this embodiment, the progressive approximation ADC includes an internal DAC consisting of a capacitor array (C7 to Clc) 'These capacitors have a non-binary specific gravity: C7=2C6=4C5=4C5c=8C4=16C3=16C3c=32C2 =64Cl =64Clc • The gradual approximation ADC of the second diagram also includes a comparator 20 that receives and compares the sampled input signal Vin and the DAC output. The gradual approximation control logic (SAR) 22 controls the sampling of the input signal Vin, and controls a series of comparisons based on the comparison result of the comparator 20, and finally outputs a corresponding digital output for approximating the input signal Vin. Φ In operation, first, an input terminal (eg, a non-inverting input terminal) of the comparator 20 receives the sample input signal Vin; and an internal digital terminal connected to the other input terminal (eg, the inverting input terminal) to the analog converter ( The DAC) is reset to the common mode voltage Vcm. As shown, the DAC is reset to the common mode voltage Vcm by connecting a switch in the DAC. Next, comparator 20 compares input signal Vin with common mode voltage Vcm to determine whether to add or subtract a V/4 voltage (where V is the amplitude of the input signal) at the DAC. In one embodiment, when the DAC circuit is stable to one bit accuracy (but not yet fully stabilized at 1328356), the control logic circuit (SAR) 22 is gradually approached to the next bit of comparison and decision. Since the DAC signal is not completely stable, it will cause an error of V/4 (V/4*l/2+V/8). Since the remaining voltage change is approximately V/8 (V/16 V/32 V/64 V/128 V/256), ±V / 8 must be added to compensate for this error. Repeat this operation until the least significant bit (LSB). The input signal can be approximated as:

Vcm soil V / 4 soil V / 8 soil V / 8 soil V / 16 soil V / 16 soil V / 32 soil V / 32 soil V / 64 soil • V / 64 soil V / 128 soil V / 128 ± V / 256 Soil V/256 In another embodiment (second figure), when the DAC circuit is stable to two-bit accuracy (rather than the one-bit element described above), the control logic circuit (SAR) 22 is gradually approached and proceeds to the next Comparison and decision of bits. Since the DAC signal is not completely stable, it will cause an error of 3V/16 (V/4*l/22+V/8). Since the remaining voltage change is approximately V/8 (V/16 earth V/32 • soil V/64 earth V/l28 soil V/256), the soil V/16 must be added to compensate for this error. Repeat this operation until the least significant bit (LSB). The input signal can be approximated as: VCm±V/4±V/8±V/16±V/16±V/32±V/64±V/64±V/128 ±Y/256±V/256 Comparing the resampling of the comparator after the DAC voltage has stabilized to a few bits will optimize the gradual approximation DAC. For an f S] 11 1328356 N-bit ADC, assuming that the DAC is stable to the accuracy of the 再 bit resampling, and the interval between the comparator and the start of the DAC is yZU (where), then the solution is The time required for data Ttotal can be approximated as: N-2

Ttotalix^N) - Tsample + (x+y)At.(N + -—) X Sample + NiX + + (Ν~2)·Αί + (~^) β Partially differentiates from X:

Ux,y,N) At- · (yAt) = 0 dx x N· At-7 ·yAt = 0

N-2 2~ / X => N = y( => X «

N-2 N Take the octet ADC as an example. If y and 5 are assumed, the optimized values χ and 2 can be obtained. Comparing the various thresholds shows that the time required for x = 2 is the shortest. x = l-^ Ttotal = Tsample +(1 + 5)Δ/ * (8 + 6) = Tsample + 84Δ/ Χ = 2 —> T^total = ^sample +(2 + 5)Δ/ * (8 + 3) = Tsample + 77At ^ = 3 ^ rto(a/ = Tsamph + (3 + 5) Δ / * (8 + 2) = rji3mpfe + 80Δί χ = 847^=7; —+ (8 + 5)Δί *8 = ;ΓΜ_+104Δ, (corresponding to the ADC of the first figure) According to the above, when X=2, the ADC is optimized, so three compensation capacitors (ie, C5c, C3c, Clc) are used to correct Gradually approximating [S] 12 1328356 « ADC ' as shown in the second figure. In general, for the ^bit adc, the number of required complements can be expressed as [(η_2)/χ], where [ 】 is a Gaussian operation symbol, which takes the integer part of the value. In this implementation, these compensation powers are arranged in the following manner in the non-compensating capacitors (c7, C6, c5, C4, C3, C2, Cl, and Cl). Between: the first compensation capacitor (c5c) is placed after the second capacitor (C5); the second compensation capacitor (c3c) is placed after the next second capacitor (C3); the third compensation capacitor ( Clc) is placed after the second capacitor (C1). The above optimization The method can be applied to ADCs with different resolutions. Furthermore, for larger resolution ADCs, the above optimization performance is better. The second figure illustrates the sampling waveform 31 corresponding to the first figure and corresponds to the second figure. (x=2) sampling waveform 32. The eleven sampling binary values (ie, 10000111110) indicated by parentheses in the drawing represent the output of the comparator. Then, the 11-bit output is gradually approximated by the control logic circuit. After the internal binary error tolerance corrector process of (SAR) 22, the 8-bit digital output of the ADC is generated to compensate for the sampling error. Although the binary error tolerance corrector in this embodiment is located in the gradual approximation control logic circuit (SAR) The interior of 22, however, in other embodiments, may also be located outside of the gradually approaching control logic (SAR) 22. 1328356 For the ADC shown in the first figure, the output can be expressed as:

Out=128 · B1+64 · B2+32 · B3+16 · B4+8 · B5+4 · B6+2 · B7+1 · B8 or

Out=(0+255)/2±64±32±16±8±4±2±l±0.5 where the symbol “+” is determined by the value of Bn being “1” or “〇”, n=l , 2,...,8 ° For the ADC shown in the second figure, the output can be expressed as:

Out=(0+255)/2±64±32±16±16±8±4±4±2±l±l±0.5 or

Out=-21 + 128 · B1+64 · B2+32 · B3+32 · B4+16 · B5+8 · B6+8 · B7+4 · B8+2 · B9+2 · B10+1 · B11 Expressed as the formula shown in the fourth figure. For the example of the third figure, the processing of the output (10000111110) can be as shown in the fifth figure. The sixth figure shows a binary error tolerance corrector of an embodiment of the present invention for converting the 11-bit output (B1 B2 B3...B11) of comparator 20 to the 8-bit output of the ADC. In this embodiment, two inputs (eg, "1" and ; bu) are added using some semi-adders (HA), and three inputs (eg, 1, B9, and B10) are used using some full adders (FA). plus. Each half adder or full adder produces a carry bit c that is fed to the adjacent front 1328356 stage half/full adder and produces a sum bit s fed to the parallel half/full adder. According to the embodiments of the present invention described above, the operation speed of the non-binary progressive approximation ADC will be larger than that of the conventional gradual approximation ADC, because the sampling is performed before the signal is completely stabilized, and a simple binary error tolerance correction mechanism is used to obtain The output of the ADC. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application. [Simple description of the diagram] The first figure shows a schematic diagram of an octet gradual approximation analog-to-number converter (SAR ADC). The second figure shows a single-ended progressive approximation ADC with a binary error tolerance mechanism in accordance with an embodiment of the present invention. The third figure illustrates the sampling waveform corresponding to the first figure and the sampling waveform corresponding to the second figure. The fourth figure shows the operation of binary error tolerance correction. 15 1328356 The fifth figure illustrates the binary error tolerance correction operation of the output of the third figure. The sixth figure shows a binary error tolerance corrector of an embodiment of the present invention. [Description of main component symbols] 10 Comparator 20 Comparator 22 Gradually approximating the control logic circuit 31 Example of sampling waveform in the first figure 32 Example of sampling waveform in the second figure 16

Claims (1)

1328356 X. Patent Application Range: 1. A gradual approximation analog to digital converter (ADC) comprising: a digital to analog converter (DAC); • a comparator, an input receiving a sampled input signal, The other input receives the output of the DAC; a non-binary gradual approximation control circuit that controls the φ sampling of the input signal, and controls a series of comparisons according to the comparison result of the comparator, wherein the gradual approximation control circuit The comparison is performed before the signal or charge of the DAC is not fully stabilized; and a corrector is used to compensate for the error caused by the comparator. 2. If the gradual approximation analog to digital converter described in claim 1 is applied, the gradual approximation control circuit controls the comparison when the signal or charge of the DAC is stabilized to at least one bit accuracy φ. Go on. 3. As in the gradual approximation analog-to-digital converter described in claim 2, when the signal or charge of the DAC is stabilized to the accuracy of the X-bit, the above-mentioned gradual approximation control circuit controls the comparison. . 4. The gradual approximation analog to digital converter of claim 3, wherein the DAC comprises a capacitor array having a capacitance value of a binary 17 1328356 weight, and at least one compensation capacitor is disposed in the binary Among the weights of the capacitors. 5. For a gradual approximation analog-to-digital converter as described in claim 4, for an n-bit ADC, the number of compensation capacitors used by the DAC described above is [(η-2)/χ], where [ ] is a Gaussian arithmetic symbol that takes the integer part of a value. 6. The gradual approximation analog to digital converter of claim 5, wherein the calibrator comprises a plurality of adders for respectively adding the output bits of the comparator. 7. The gradual approximation analog to digital converter of claim 1, wherein the ADC has an η bit resolution. 8. As in the gradual approximation analog-to-digital converter described in claim 7, when the signal or charge of the DAC is stabilized to the accuracy of the X-bit, the above-mentioned gradual approximation control circuit controls the comparison. And for an n-bit ADC, the number of compensation capacitors used by the above DAC is [(η-2)/χ], where [] is a Gaussian operation symbol, which takes the integer part of a value 0 18 1328356 9. The gradual approximation analog to digital converter of claim 8 wherein the ADC has an 8-bit resolution and the DAC comprises a capacitor array having a capacitance value having the following non-binary weights: C7=2C6= 4C5=4C5c=8C4=16C3=16C3c=32C2=64Cl=64Clc 〇10. The gradual approximation analog to digital converter according to claim 9 of the patent application, wherein the output of the gradual approximation control circuit is based on the following Correction calculation to correct: Out=-21 + 128 · B1+64 · B2+32 · B3+32 · B4+16 · B5+8 · B6+8 · B7+4 · B8+2 · B9+2 · B10+ 1 · B11. 11. The gradual approximation analog to digital converter of claim 10, wherein the calibrator comprises a plurality of adders for respectively adding the values of the same weight in the correction operation. 12. The gradual approximation analog to digital converter according to claim 11, wherein the above correction operation converts (B1 B2 B3 ... B11) into (A1 A2 A3 ... A8) according to the following formula: 1110 10 11 19 1328356 Bi B2 B3 B5 B6 B8 B9 Bii + B4 B7 BIO A1 A2 A3 A4 A5 A6 A7 A8. 20