1325633 13364twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體元件及其製造方法，且特 別是有關於一種可與高壓元件及低壓元件相容之可電除可 程式化之唯讀記憶胞(Electrical Erase Program Read Only Memory Cell，EEPROM Cell)與記憶體元件及其製造方 法。 【先前技術】 可電除可程式化之唯讀記憶體具有可寫入、可抹除以 及斷電後仍可保存資料的優點。此外，可電除可程式化之 唯讀記憶體亦為一種非揮發性記憶體（Non-Volatile Memory) ’若能將此元件整合嵌入邏輯(L〇gic)或整合訊號 (Mixed Mode)積體電路中，將使得邏輯或整合訊號積體電 路擁有自我電路調整或修護的強大功能。 圖1A至圖1B是續·示習知一種可電除可程式化之唯 讀s己憶體的製造流程剖面示意圖。請參照圖ία，此可電 除可程式化之唯讀記憶體係先於基底1〇〇上依序穿隧層 102(Tunnel Layer)、多晶矽浮置閘極層（F1〇ating Gate Layer) 104、閘間介電層（inter_Gate Dielectric Layer)106 與 多晶梦控制閘極層（Control Gate Layer)l〇8。然後，請參 照圖1B，定義上述這些膜層，以形成一堆疊式閘極結構 110，並且在此堆疊式閘極結構110兩侧之基底1〇〇中形 成源極區112a與汲極區U2b。 然而，在上述的製程中，由於需要形成兩層的多晶矽 1325633 13364twf.doc/0〇6 層，以分別作為浮置_及㈣_之用 之兩層多晶㈣會與周邊電㈣μ金屬氧化半導體己^ (MOSk_有高度差’因此兩者之製程整合難度較高。 此外由於-般可電除可程^化之唯讀記憶體的操作 電壓無法承受大於12V之電壓，因此也紐㈣於高 與低壓元件共存^> 除此之外，對於單-個可鎌可程式化之唯讀記憶胞 來說’ -般是形成於單-井區巾，以使其能_立操作。 ，是，此將使得此可電除可程式化之唯讀記憶胞無法與 尚壓元件與低壓元件共用相同的井區，因此難以使可電除 可程式化之唯讀記憶胞與高壓元件及低壓元件之製程整合 在一起。 σ 【發明内容】 有鑑於此，本發明的目的就是在提供一種可電除可程 式化之唯讀記憶胞的製造方法，其與周邊電路之元件之閘 極高度相當，因而兩者製程較容易整合在一起。 本發明的另一目的是提供一種可電除可程式化之唯讀 記憶胞，其係為與傳統具有二層多晶矽層之記憶體不相同 之結構。 本發明的再一目的是提供一種記憶體元件的製造方 法，以解決習知之可電除可程式化之唯讀記憶胞無法與高 壓元件及低壓元件的製程整合的問題。 本發明的又一目的是提供一種記憶體元件，以解決習 知之可電除可程式化之唯讀記憶胞無法與高壓元件及低壓 1325633 13364twf.doc/006 元件並存的問題。 本發明提出一種可電除可程式化之唯讀記憶胞的製造 方法’此方法係先於基底的表面上分別形成穿隧層以及間 間介電層，並且於閘間介電層下方之基底中形成摻雜區， 以作為控制閘極之用。接著，於閘間介電層與穿隧層上形 成浮置閘極。之後’於下方形成有穿隧層之浮置閘極兩側 的基底中形成源極區與汲極區。 本發明提出一種可電除可程式化之唯讀記憶胞，此可 電除可程式化之唯讀記憶胞係由基底、閘間介電層、穿隧 層、摻雜區、浮置閘極、源極區與汲極區所構成。其中， 閘間介電層以及穿隧層係分別配置在基底之表面上。此 • 外’摻雜區係配置在閘間介電層底下之基底中，且此摻雜 區係作為控制閘極之用。另外，浮置閘極係配置在穿隧層 以及閘間介電層上。此外，源極區與汲極區係配置在下方 配置有穿隧層之浮置閘極兩側的基底中。 β本發明提出一種記憶體元件的製造方法，此方法係先 提供基底，此基底具有記憶胞區與周邊電路區，且周邊電 路區包括有高壓元件區與低壓元件區。之後，在記憶胞區 之基底的表面上分別形成穿隧層以及閘間介電層，並且在 周邊電路區中之高壓元件區與低壓元件區之基底表面上分 另此成第閑介電層與第二閉介電層，且於閑間介電層下 方之基底中形成摻雜區，以作為控制閘極之用。然後，在 Α憶胞區中之閘間介電層與穿隧層上形成浮置閘極，並且 在周邊電路區之第一閘介電層與第二閘介電層上分別形成 7 13364twf.doc/006 第-閘極與第二雖^繼之，在記憶胞區中之下方形成有 穿，層之洋置閘極兩侧的基底中形成第—源極區與第一及 ，區並且在周邊電路區巾之第—酿_丨縣底中形成 第二源極區及第二没極區，且於第二閘極兩側的基底中形 成第二源極區及第三汲極區。 本發明提出一種記憶體元件，此記憶體元件係由基 底、至少一記憶胞、至少一高壓元件與至少一低壓元件所 構成其中’基底具有記憶胞區與周邊電路區，且此周邊 電路區包括有高壓元件區與低壓元件區。料，記憶胞係 西α己置在S己憶胞區中，且其係由閘間介電層、穿隧層、摻雜 區、浮置閘極、第一源極區與第一汲極區所構成。其中， 閘間介電層以及穿㈣係分㈣置在基底之表面上。此 外，摻雜區係配置在閘間介電層底下之基底中，且此掺雜 區係作為控制閘極之用。另外，浮置閘極係配置在穿隧層 以及閘間介電層上。此外，第一源極區與第一汲極區係配 下方配置有穿隧層之浮置閘極兩侧的基底中。另外， Ν壓元件係配置在高壓元件區中，且其係由第一閘介電 曰第閘極、第一源極區與第二汲極區所構成。其中， 第閘介電層係配置在高壓元件區之基底表面。此外，第 一閘極係配置在第一閘介電層上。另外，第二源極區與第 二及極區係配置在第一閘極兩側的基底中。此外，低壓元 件係配置在低壓元件區中，且其係由第二閘介電層、第二 閘極、第三源極區與第三汲極區所構成。其中，第二閘介 電層係配置在低壓元件區之基底表面。另外，第二閘極係 1325633 13364twf.doc/006 配置在第二閘介電層上。此外，第三源極區與第三汲極區 係配置在第—閘極兩側的基底中。 由於本發明之可電除可程式化之唯讀記憶胞之控制閘 極係以摻雜區之形式配置於基底中，其係為一種與傳統具 有一層夕晶石夕層之記憶胞不相同的結構。而且本發明之記 憶胞可以與高壓元件及低壓元件並存，且其製程可以整合 在一起。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 一在上述内容及下述内容中所出現之「高壓元件」係表 不用於相對高壓操作之元件，而所出現之「低壓元件」係 表示用於相對低壓操作之元件。 4圖2A至圖2D是繪示依照本發明一較佳實施例的一 種尤憶體元件之製造流程剖面圖，其中此記憶體元件包括 位於β己憶胞區之可電除可程式化之唯讀記紐，以及位於 周邊電路區之高壓元件與低壓元件。此外，圖3是圖2Α 至圖2D之位於記憶胞區的可電除可程式化之唯讀記憶胞 的上視不意圖，且由1_1’剖面所得之剖面示意圖係如圖2Α 至圖2D之位於記憶胞區202之左邊結構所示；由π·π， 剖面所得之剖面示意圖係如右邊結構所示。 清同時參照圖2Α與圖3，本發明之記憶體元件的製 造方法係先提供基底200 ,此基底2〇〇具有記憶胞區2〇2 1325633 13364twf.doc/0〇6 與周邊電路區204，且周邊電路區2〇4包括有高壓元件區 206與低壓元件區208。 在一較佳實施例中，此高壓元件區206更包括n型高 壓元件區21〇&與15型高壓元件區21〇b，且低壓元件區2〇8 更包括η型低壓元件區以以與卩型低壓元件區21沘。 此外，在另一較佳實施例中，上述這些區域例如是利 ，兀件隔離區214來定義的，且這些元件隔離區214例如 是藉由區域氧化(LOCOS)製程、淺溝渠隔離結構製程或是 其他合適之製程，而形成之。 之後，在記憶胞區202中之基底200的表面上分別形 ^穿隧層以及閘間介電層，並且在周邊電路區204中之高 壓兀件區206與低壓元件區208之基底200表面上分別形 成閘介電層，且於閘間介電層下方之基底200中形成摻雜 區’以作為㈣雜之用。關於上這麵層及摻雜區形成 方法，在一較佳實施例中，例如是採取下述之圖2A至圖 2C之步驟進行。 請繼續參照® 2A，於基底上形齡電材料層 216。其中，介電材料層216的材質例如是氧化矽或是其 他δ適之材質，其形成方法例如是進行熱氧化製程或是其 他合適之製程，而所形成的厚度例如是300埃至50〇埃。 在一較佳實例中，在形成介電材料層216之前，更包 括在記憶胞區202及周邊電路區204之基底_中形成 型井區218與η型井區220。其中’井區218、220的形 成方法例如是進行離子植人製程H位於周邊電路區 1325633 13364twf.doc/006 204之p型井區218係形成於n型高壓元件區21加及n 型低壓元件區212a之基底200中，而η型井區22〇係形 成於Ρ型高壓元件區210b及ρ型低壓元件區21沘之基底 200 中。 土 _ 接著，於記憶胞區202之井區220中形成n型摻雜區 222，以作為控制閘極之用，其形成方法例如是進行離子 植入製程。在一較佳實施例中，在形成η型摻雜區時， 更可於ρ型高壓元件區210b之元件隔離區214之下方的 基底200中形成另一 n型摻雜區223，以作為通道阻絕 (Channel Stop)之用。 此外，在另一較佳實施例中，在n型摻雜區222形成 之後’更可於η型南壓元件區21〇a之ρ型井區218中形 成摻雜區224，以調整欲作為通道區之摻質濃度，進而調 整高壓元件之啟始電壓。另外，在又一較佳實施例中，在 η型摻雜區222形成之後，更可於p型高壓元件區21〇b 之η型井區220中形成摻雜區226 ’以調整欲作為通道區 之摻質濃度，進而調整高壓元件之啟始電壓。 然後，請參照圖2Β，移除位於記憶胞區2〇2之位於 Ρ型井區218上的介電材料層216，並且移除位於低壓元 件區208之基底200表面的介電材料層216，以使部分的 基底200表面暴露出來。其中，移除部分介電材料層 的方法例如是進行乾式蝕刻製程、濕式蝕刻製程或是其他 合適之製程。而且，保留下來之介電材料層216 ,在位於 記憶胞區202的部分係作為閘間介電層228之用，並且在 1325633 13364twf.doc/006 位於高壓元件區206的部分係作為閘介電層23〇之用。 在一較佳實施例中，在移除部分的介電材料層216之 前’更可先於η型高壓元件區210a之元件隔離區214之 下方的基底200中形成作為通道阻絕之用 此外，在另-較佳實施例中，在移除部分的 之刖，更可先於η型低壓元件區212a及記憶胞區2〇2中 形成作為通道阻絕以及抗接面穿擊(Ami_Punch Thr〇ugh) 之用的摻雜區（未繪示）。 另外，在又一較佳實施例中，在移除部分的介電材料 籲 層216之前，更可先於記憶胞區2〇2之p型井區218中形 成摻雜區236，並且於周邊電路區2〇4之n型低壓元件區 212a的ρ型井區218中形成摻雜區238，且於ρ型低壓元 件區212b的η型井區220中形成摻雜區240，以調整欲 作為通道區之摻質濃度，進而調整記憶體元件與低壓元件 的啟始電壓。 繼之’於基底200上形成另一層介電材料層242 ^其 中，介電材料層242的材質例如是氧化矽或是其他合適之 材質，其形成方法例如是進行熱氧化製程或是其他合適之 鲁 製程，而所形成之厚度例如是60埃至80埃。此時，閘介 電層230與閘間介電層228厚度亦會變厚。 然後’請參照圖2C ’移除位於低壓元件區208之介 電材料層242 ’以使部分的基底200表面暴露出來，且所 保留下來之位於記憶胞區202中的介電材料層242係作為 穿隧層244之用。其中，移除部分介電材料層242的方法 12 1325633 13364twf.doc/006 例如疋進行乾式钱刻製程、濕式侧製程或是其他 製程。 之後’於基底200上形成又一層介電材料層（未繪示）， 且所形成之介電材料層’在位於低麼元件區2〇8的部 作為閘介電層246之用。其中，此介電材料層的材質例如 是氧化石夕或是其他合適之材質，其形成方法例如是進行熱 氧化製程或是其他合適之製程，而所形成之厚度例如是^ 埃至70埃。此時，閉介電層23〇、開間介電層228 随層244厚度亦會變厚。詳細的說明是，記憶胞區2〇2之 閘間介電層228的厚度是大於穿隨層244的厚度，其中閘 間介電層228的厚度例如是介於3〇〇埃至5〇〇 穿隨層244的厚度例如是介於95埃至1〇〇埃之間^外 高I元件區206之間介電層23〇的厚度例如是大於低壓元 件區208之閘介電層246的厚度，如此於高麗元件區 所形成之元件係可承受較高之電壓。其中，閑介電層⑽ 的厚度例如是介於45G埃至5GG埃之間，關介電層246 的厚度例如是介於6〇埃至70埃之間。 然後，在記憶胞區202中之閘間介電層228與穿隧層 244上形成浮置閘極248，並且在周邊電路區辦中之閘 介電層230與閘介電層246分別形成閘極25〇與252。其 中，浮置閘極248與閘極250、252的材質例如是、多晶石厂、 f雜多晶石夕、金屬砂化物或是其他合適之導電材料，而金 屬石夕化物例如是石夕化鎢。此外，浮置閘極248與間極25〇、 252的形成方法例如是進行習知的閘極製程。 13 1325633 13364twf.doc/006 在一較佳實施例中’在浮置閘極248與閘極250、252 形成之後，更包括於η型高壓元件區210a與p型高壓元 件區210b的閘極250兩側的基底200中，分別形成n型 深摻雜區254與ρ型深摻雜區256，以提高高壓元件的崩 潰電壓。 此外，在另一較佳實施例中，在浮置閘極248與閘極 250、252形成之後，更包括於記憶胞區2〇2之穿隧層244 下方之Ρ型井區218的摻雜區236中，形成η型深摻雜區 257，以提高記憶體元件之源極端的崩潰電壓。 繼之，請參照圖2D，在記憶胞區202中之下方形成 有穿隧層244之浮置閘極248兩側的基底200中形成 源極區258a與汲極區258b，並且在n型高壓元件區21〇a 中之閘極250兩侧的深摻雜區254中形成n型源極區26加 與没極區260b，且在n型低壓元件區212a中之閘極252 兩側的掺雜區238中形成㈣源極區2必與沒極區2必。 而且’在P 高壓元件區鳩中之閘極25() _的深# 雜區256中形成p型源極區26如與汲極區麟 在 P型低壓元件區勘中之間極252兩側的推雜區24〇f 形成P型源極區266a與沒極區鳩。其中 瓣區的形成方式例如是進行ρ型摻質之離子;= 與η型摻質之離子植人製程。 針植入製程 在-較佳實施例中，在形成η型源極區與汲極 更c括於記憶胞區2G2之浮置_ 2 ， 13364twf.d〇c/〇〇6 制問Si部份，以增加控侧極的導電性。 佳: 換質静τ措此調整這絲極區與汲極區的 浮置心248 法例如是藉由形成於 ，、’極250、252側壁上之間隙壁270為罩 入製π㈣(PGeke⑽子植人製程或是習知之離子植1325633 13364twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a memory element and a method of manufacturing the same, and more particularly to an electrical device compatible with a high voltage component and a low voltage component In addition to a programmable Erase Program Read Only Memory Cell (EEPROM Cell) and a memory element, and a method of manufacturing the same. [Prior Art] The programmable read-only memory has the advantages of being writable, erasable, and capable of saving data after power-off. In addition, the programmable read-only memory is also a non-volatile memory (Non-Volatile Memory) 'If this component can be integrated into the logic (L〇gic) or integrated signal (Mixed Mode) integrated body In the circuit, the logic or integrated signal integrated circuit has the powerful function of self-circuit adjustment or repair. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1B are schematic cross-sectional views showing the manufacturing process of an electrically erasable and programmable read-only suffix. Referring to FIG. ία, the readable read-only memory system can be sequentially preceded by a tunnel layer 102, a polysilicon floating gate layer (104), and a polymorphic floating gate layer (104). The inter_Gate Dielectric Layer 106 and the Poly Gate Control Gate Layer l〇8. Then, referring to FIG. 1B, the above-mentioned film layers are defined to form a stacked gate structure 110, and a source region 112a and a drain region U2b are formed in the substrate 1〇〇 on both sides of the stacked gate structure 110. . However, in the above process, it is necessary to form two layers of polysilicon 1325633 13364twf.doc/0〇6 layers to be used as floating _ and (4) _ for two layers of polycrystalline (four) and peripheral electric (tetra) μ metal oxide semiconductor. ^^(MOSk_ has a height difference', so the process integration of the two is more difficult. In addition, since the operating voltage of the readable memory can not withstand the voltage greater than 12V, it is also a new (four) Coexistence of high and low voltage components ^> In addition, for a single readable programmable memory cell, it is formed in a single-well zone to enable it to operate. Yes, this will make it possible to eliminate the programmable read-only memory cells and share the same well area with the low voltage components and the low voltage components. Therefore, it is difficult to make the programmable read-only memory cells and high voltage components and low voltage. The process of the components is integrated. σ [ SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for manufacturing a readable read-only memory cell that is equivalent to the gate height of components of peripheral circuits. Therefore, the two processes are more compatible Integrating together. Another object of the present invention is to provide an electrically erasable and programmable readable memory cell which is different from a conventional memory having a two-layer polysilicon layer. A further object of the present invention is A method of fabricating a memory device is provided to solve the problem that the conventional readable read-only memory cell cannot be integrated with the process of the high voltage component and the low voltage component. It is still another object of the present invention to provide a memory component. The invention solves the problem that the conventional readable read-only memory cell cannot coexist with the high voltage component and the low voltage 1325633 13364 twf.doc/006 component. The invention provides a method for manufacturing the readable read-only memory cell 'This method forms a tunneling layer and an inter-dielectric layer respectively on the surface of the substrate, and forms a doping region in the substrate below the inter-gate dielectric layer for use as a control gate. Next, the gate is used. A floating gate is formed on the dielectric layer and the tunneling layer. Then, a source region and a drain region are formed in the substrate on both sides of the floating gate on which the tunneling layer is formed. A readable read-only memory cell that can be electrically de-programmed, which can be used to erase a programmable read-only memory cell from a substrate, a gate dielectric layer, a tunneling layer, a doped region, a floating gate, a source a pole region and a drain region are formed, wherein the gate dielectric layer and the tunneling layer are respectively disposed on the surface of the substrate. The outer 'doped region is disposed in the substrate under the gate dielectric layer, and The doped region is used as a control gate. In addition, the floating gate is disposed on the tunneling layer and the inter-gate dielectric layer. Further, the source region and the drain region are disposed below the tunnel layer. The substrate on both sides of the floating gate. The present invention provides a method for fabricating a memory device. The method provides a substrate having a memory cell region and a peripheral circuit region, and the peripheral circuit region includes a high voltage device region. With low voltage component area. Thereafter, a tunneling layer and an inter-gate dielectric layer are respectively formed on the surface of the substrate of the memory cell region, and the first dielectric layer is formed on the surface of the high voltage device region and the low voltage device region in the peripheral circuit region. A doped region is formed in the substrate under the second dielectric layer and under the dummy dielectric layer for use as a control gate. Then, a floating gate is formed on the dielectric layer and the tunneling layer in the gate region of the memory cell, and 7 13364 twf is formed on the first gate dielectric layer and the second gate dielectric layer in the peripheral circuit region, respectively. Doc/006 The first-gate and the second, respectively, are formed under the memory cell region, and the first-source region and the first region are formed in the substrate on both sides of the gate electrode. Forming a second source region and a second gate region in a bottom portion of the peripheral circuit region, and forming a second source region and a third drain region in the substrate on both sides of the second gate . The present invention provides a memory device that is composed of a substrate, at least one memory cell, at least one high voltage component, and at least one low voltage component, wherein the substrate has a memory cell region and a peripheral circuit region, and the peripheral circuit region includes There are high voltage component regions and low voltage component regions. The memory cell Western α has been placed in the S memory cell, and is composed of a gate dielectric layer, a tunneling layer, a doped region, a floating gate, a first source region and a first drain. The composition of the district. Wherein, the inter-gate dielectric layer and the wearing (four) part (4) are placed on the surface of the substrate. In addition, the doped regions are disposed in the substrate under the inter-gate dielectric layer, and the doped regions serve as control gates. In addition, the floating gate is disposed on the tunneling layer and the inter-gate dielectric layer. In addition, the first source region and the first drain region are disposed in a substrate disposed on both sides of the floating gate of the tunneling layer. Further, the rolling element is disposed in the high voltage element region, and is composed of the first gate dielectric gate, the first source region, and the second drain region. Wherein, the first gate dielectric layer is disposed on a surface of the substrate of the high voltage device region. In addition, the first gate is disposed on the first gate dielectric layer. In addition, the second source region and the second and polar regions are disposed in the substrate on both sides of the first gate. Further, the low voltage component is disposed in the low voltage device region and is composed of the second gate dielectric layer, the second gate, the third source region, and the third drain region. Wherein, the second gate dielectric layer is disposed on the surface of the substrate of the low voltage component region. In addition, the second gate system 1325633 13364twf.doc/006 is disposed on the second gate dielectric layer. Further, the third source region and the third drain region are disposed in the substrate on both sides of the first gate. Since the control gate of the electrically readable programmable read-only memory cell of the present invention is disposed in the substrate in the form of a doped region, it is different from the conventional memory cell having a layer of oligolithic layer. structure. Moreover, the memory cells of the present invention can coexist with high voltage components and low voltage components, and the processes can be integrated. The above and other objects, features, and advantages of the present invention will be apparent from [Embodiment] A "high-voltage element" appearing in the above and the following contents is not used for a relatively high-voltage operation element, and the "low-voltage element" appearing means an element for relatively low-voltage operation. 4A to 2D are cross-sectional views showing a manufacturing process of a memory component in accordance with a preferred embodiment of the present invention, wherein the memory component includes an electrically erasable and programmable only one located in the β-remembered cell region. Reading notes, as well as high voltage components and low voltage components located in the peripheral circuit area. In addition, FIG. 3 is a top view of the electrically readable programmable read only memory cell located in the memory cell region of FIG. 2A to FIG. 2D, and the cross-sectional view obtained by the 1_1′ profile is as shown in FIG. 2A to FIG. 2D. The structure on the left side of the memory cell region 202 is shown; the cross-sectional view obtained from the π·π, cross-section is as shown in the right structure. Referring to FIG. 2A and FIG. 3, the method for fabricating the memory device of the present invention first provides a substrate 200 having a memory cell region 2〇2 1325633 13364twf.doc/0〇6 and a peripheral circuit region 204, And the peripheral circuit area 2〇4 includes a high voltage element region 206 and a low voltage element region 208. In a preferred embodiment, the high voltage device region 206 further includes an n-type high voltage device region 21〇& and a 15-type high voltage device region 21〇b, and the low voltage device region 2〇8 further includes an n-type low voltage device region to With the 卩-type low-voltage component area 21沘. Moreover, in another preferred embodiment, the regions are defined, for example, by a barrier isolation region 214, and the component isolation regions 214 are, for example, by a region oxidation (LOCOS) process, a shallow trench isolation structure process, or It is formed by other suitable processes. Thereafter, a tunneling layer and an inter-gate dielectric layer are formed on the surface of the substrate 200 in the memory cell region 202, respectively, and on the surface of the substrate 200 of the high voltage component region 206 and the low voltage device region 208 in the peripheral circuit region 204. A gate dielectric layer is formed separately, and a doped region 'is formed in the substrate 200 under the inter-gate dielectric layer for (4) miscellaneous use. Regarding the upper surface layer and the doping region forming method, in a preferred embodiment, for example, the steps of Figs. 2A to 2C described below are employed. Continue to refer to ® 2A to form a layer 216 of ageing electrical material on the substrate. The material of the dielectric material layer 216 is, for example, yttrium oxide or other δ suitable material, and the forming method is, for example, performing a thermal oxidation process or another suitable process, and the formed thickness is, for example, 300 angstroms to 50 angstroms. . In a preferred embodiment, prior to forming the dielectric material layer 216, a well region 218 and an n-well region 220 are formed in the substrate _ of the memory cell region 202 and the peripheral circuit region 204. The method for forming the well regions 218 and 220 is, for example, an ion implantation process H. The p-type well region 218 located in the peripheral circuit region 1325633 13364 twf.doc/006 204 is formed in the n-type high voltage device region 21 plus the n-type low voltage component. In the substrate 200 of the region 212a, the n-type well region 22 is formed in the substrate 200 of the Ρ-type high-voltage element region 210b and the p-type low-voltage device region 21沘. Soil _ Next, an n-type doped region 222 is formed in the well region 220 of the memory cell region 202 for use as a control gate, which is formed, for example, by an ion implantation process. In a preferred embodiment, another n-type doping region 223 is formed in the substrate 200 below the element isolation region 214 of the p-type high voltage device region 210b as a channel when the n-type doping region is formed. Block Stop. In addition, in another preferred embodiment, after the formation of the n-type doping region 222, a doping region 224 is formed in the p-type well region 218 of the n-type south-voltage device region 21A to adjust The dopant concentration of the channel region, in turn, adjusts the starting voltage of the high voltage component. In addition, in another preferred embodiment, after the formation of the n-type doping region 222, the doping region 226' may be formed in the n-type well region 220 of the p-type high voltage device region 21〇b to adjust the channel to be used. The dopant concentration of the region, in turn, adjusts the starting voltage of the high voltage component. Then, referring to FIG. 2A, the dielectric material layer 216 located on the germanium well region 218 in the memory cell region 2〇2 is removed, and the dielectric material layer 216 on the surface of the substrate 200 of the low voltage device region 208 is removed. To expose a portion of the surface of the substrate 200. The method of removing a portion of the dielectric material layer is, for example, a dry etching process, a wet etching process, or other suitable process. Moreover, the remaining dielectric material layer 216 is used as the inter-gate dielectric layer 228 in the portion located in the memory cell region 202, and is located as the gate dielectric at 1325633 13364 twf.doc/006 located in the high voltage device region 206. Layer 23 is used. In a preferred embodiment, before the removal of a portion of the dielectric material layer 216, it may be formed as a channel barrier prior to the substrate 200 below the element isolation region 214 of the n-type high voltage device region 210a. In another preferred embodiment, after the removed portion, it may be formed in the n-type low-voltage device region 212a and the memory cell region 2〇2 as channel blocking and anti-contact punching (Ami_Punch Thr〇ugh). Doped regions (not shown). In addition, in another preferred embodiment, the doped region 236 may be formed in the p-type well region 218 of the memory cell region 2 before the portion of the dielectric material layer 216 is removed. A doped region 238 is formed in the p-type well region 218 of the n-type low-voltage device region 212a of the circuit region 2〇4, and a doped region 240 is formed in the n-type well region 220 of the p-type low-voltage device region 212b for adjustment The dopant concentration of the channel region, thereby adjusting the starting voltage of the memory component and the low voltage component. Next, another layer of dielectric material 242 is formed on the substrate 200. The material of the dielectric material layer 242 is, for example, yttrium oxide or other suitable material, and the formation method is, for example, a thermal oxidation process or other suitable. Lu process, and the thickness formed is, for example, 60 angstroms to 80 angstroms. At this time, the thickness of the gate dielectric layer 230 and the inter-gate dielectric layer 228 also becomes thick. Then, please refer to FIG. 2C to remove the dielectric material layer 242' located in the low voltage device region 208 to expose a portion of the surface of the substrate 200, and the remaining dielectric material layer 242 remaining in the memory cell region 202 serves as Used for tunneling layer 244. Wherein, the method of removing a portion of the dielectric material layer 242 12 1325633 13364 twf.doc/006, for example, performs a dry etching process, a wet side process, or other processes. Thereafter, a further layer of dielectric material (not shown) is formed on the substrate 200, and the formed dielectric material layer ' is used as the gate dielectric layer 246 at the portion of the low device region 2〇8. The material of the dielectric material layer is, for example, oxidized stone or other suitable material, and is formed by, for example, a thermal oxidation process or another suitable process, and the thickness is, for example, angstroms to 70 angstroms. At this time, the closed dielectric layer 23 and the open dielectric layer 228 also become thicker with the thickness of the layer 244. In detail, the thickness of the inter-gate dielectric layer 228 of the memory cell region 2 is greater than the thickness of the pass-through layer 244, wherein the thickness of the inter-gate dielectric layer 228 is, for example, 3 〇〇 to 5 〇〇. The thickness of the pass-by layer 244 is, for example, between 95 angstroms and 1 angstrom. The thickness of the dielectric layer 23 之间 between the outer high I-element regions 206 is, for example, greater than the thickness of the gate dielectric layer 246 of the low-voltage device region 208. Thus, the components formed in the Korean component area can withstand higher voltages. The thickness of the dielectric layer (10) is, for example, between 45 G and 5 GG, and the thickness of the dielectric layer 246 is, for example, between 6 Å and 70 Å. Then, a floating gate 248 is formed on the inter-gate dielectric layer 228 and the tunneling layer 244 in the memory cell region 202, and the gate dielectric layer 230 and the gate dielectric layer 246 are respectively formed in the peripheral circuit region. Extreme 25〇 and 252. The material of the floating gate 248 and the gates 250 and 252 is, for example, a polycrystalline stone factory, a f-heteropolycrystalline stone, a metal sand compound or other suitable conductive material, and the metal stone compound is, for example, a stone eve. Tungsten. Further, the method of forming the floating gate 248 and the interpoles 25A, 252 is, for example, a conventional gate process. 13 1325633 13364twf.doc/006 In a preferred embodiment, after the floating gate 248 and the gates 250, 252 are formed, the gate 250 is further included in the n-type high voltage device region 210a and the p-type high voltage device region 210b. In the substrate 200 on both sides, an n-type deep doped region 254 and a p-type deep doped region 256 are formed, respectively, to increase the breakdown voltage of the high voltage device. In addition, in another preferred embodiment, after the floating gate 248 and the gates 250, 252 are formed, the doping of the germanium well region 218 is further included below the tunneling layer 244 of the memory cell region 2〇2. In region 236, an n-type deep doped region 257 is formed to increase the breakdown voltage at the source terminal of the memory device. Then, referring to FIG. 2D, a source region 258a and a drain region 258b are formed in the substrate 200 on both sides of the floating gate 248 of the tunneling layer 244 formed under the memory cell region 202, and the n-type high voltage is formed. An n-type source region 26 is applied to the deep doped region 254 on both sides of the gate 250 in the element region 21a, and a non-polar region 260b is formed, and the doping on both sides of the gate 252 in the n-type low-voltage device region 212a is formed. The formation of the (4) source region 2 in the impurity region 238 must be coincident with the non-polar region 2. Moreover, the p-type source region 26 is formed in the deep region 256 of the gate 25() _ in the P high-voltage device region, such as the pole 252 between the P-type low-voltage component region and the P-type low-voltage component region. The doping region 24〇f forms a P-type source region 266a and a non-polar region. The formation of the valve region is, for example, an ion carrying a p-type dopant; and an ion implantation process with an n-type dopant. The needle implantation process is in the preferred embodiment, in which the n-type source region and the drain are formed, and the floating portion of the memory cell region 2G2 is _ 2, 13364 twf.d〇c/〇〇6. To increase the conductivity of the control side pole. Preferably: the method of adjusting the floating core 248 of the filament region and the drain region is, for example, by inserting the spacer 270 formed on the sidewalls of the poles 250 and 252 into a π (four) (PGeke (10) sub- Implantation process or conventional ion implantation
繼之，這上述這些源極區與汲極區形成之後，更可以 =區與没極區進行回火製程，並且接續進行相關 、、’程。關於内連線製程係為熟習該項技術者所週 知，於此不再贅述。Then, after the above-mentioned source regions and the drain regions are formed, the tempering process can be performed in the =region and the immersion region, and the correlation, the process is continued. The interconnect process is well known to those skilled in the art and will not be described here.
以下係針對利用上述方法所得之結構加以說明。請同 時參照圖2D與圖3,本發明之記憶體元件係由基底2〇〇、 至少-記憶胞、至少-高壓元件與至少一低壓^件所構 成。其中，基底200具有記憶胞區2〇2與周邊電路區2〇4， 且此周邊電路區2〇4包括有高壓元件區2〇6與低壓元件區 208 ’而且這些區域係藉由元件隔離區214而彼此隔離。 在一較佳實施例中，在此高壓元件區2〇6中更包括有 η型向壓元件區210a與ρ型高壓元件區21〇b，且在低壓 兀件區208中更包括有n型低壓元件區212a與p型低壓 元件區212b。此外，在另一較佳實施例中，基底2〇〇中 更包括配置有多數個p型井區218與n型井區220。其中， 15 1325633 97-10-03 位於周邊電路區204之p型井區218係配置高壓元 件區210a及n型低壓元件區212a之基底2〇〇中，而11型 井區220係配置於p型高壓元件區21〇b&n型低壓元件區 212b之基底200中。 另外，記憶胞係配置在記憶胞區2〇2中，且其係由閘 間介電層228、穿隧層244、摻雜區222、浮置閘極248、 源極區258a與汲極區258b所構成。其中，閘間介電層228 以，穿隨層244係分別配置在記憶胞區2〇2中之基底· ^面上，且閘間介電層228的厚度大於穿隨層2料的厚 ^，且此閘間介電層228的厚度例如是介於獨埃至· =之間，而穿隨層244的厚度例如是介於95埃至⑽埃之 型井Ho 222係配置在關介電層228底下之η 且且此推雜區222係作為控制閘極之用，而 匕4雜區222的摻質型態例如是n型。 電声3上浮置閉極248係配置在穿隨層24切及閉間介 配;古办，而源極區258&與汲極區258b係配置在下方 配置^層244之浮置閘極248兩側的基底2(^了方 ，實施例中，此記憶胞更包括—濃換㈣ 從中2〇2之浮置間極側邊的摻雜區 控制閉極=^=卜2控制閘極—部份，以增加 胞更包括—36卜配；實施例中’此記憶 h 236，配置在Ρ型并區918 士 區258a與汲極區25% ，且源極 b係配置於其中，以作為調整通道區 16 1325633 13364twf.doc/006 之摻質濃度’進而調整記憶體元件的啟始電壓之用。另外， 在又較佳實例中，此記憶胞更包括一深摻雜區,配 置在穿隧層244下方之摻雜區236中，且源極區258a係 配置於此深摻雜區257中，以作為提高記憶體元件之源極 端的崩潰電壓之用。 另外，高壓元件係配置在高壓元件區2〇6中，且其係 由閘介電層230、閘極250、源極區260a、264a與汲極區 260b、264b所構成。其中，閘介電層23〇係配置在高壓 元件區206之基底200表面，而閘極250係配置在閘介電 層230上。 此外，源極區260a與汲極區260b係配置在n型高壓 元件區210a之閘極250兩側的基底200中。其中，源極 區260a與汲極區260b的摻質型態係為！！型。另外，源極 區264a與汲極區264b係配置在p型高壓元件區21〇b之 閘極250兩側的基底200中，其中源極區264a與汲極區 264b的摻質型態係為p型。 在一較佳實施例中’此高壓元件更包括摻雜區224、 226 ’分別配置在p型井區218與η型井區220中，且源 極區260a與汲極區260b及源極區264a與没極區264b分 別配置於其中，以作為調整通道區之摻質濃度，進而調整 尚壓元件的啟始電壓之用。另外’此高壓元件更包括深摻 雜區254、256 ’分別配置在閘極250兩側之p型井區218 與η型井區220中，且源極區260a與汲極區260b及源極 區264a與沒極區264b分別配置於其中，以作為提高高壓 17 1325633 97-10-03 元件的崩潰電壓之用。另外，此高壓元件更包括摻雜區 232、223 ’分別配置在p型井區218與]^型井區220之^ 件隔離區214下方的基底200中，以作為通道阻絕之用。 另外，低壓元件係配置在低壓元件區208中，且其係 由閘介電層246、閘極252、源極區262a、266a與汲極區 262b、266b所構成。其中，閘介電層246係配置在低壓元 件區208之基底200表面，而且位於高壓元件區2〇6之閘 介電層230的厚度大於位於低壓元件區2〇8之閘介電層 246的厚度，如此於高壓元件區2〇6所形成之元件可承受 車父南之電壓。其中，閘介電層230的厚度例如是介於450 埃至500埃之間’而閘介電層246的厚度例如是介於60 埃至70埃之間。 此外，閘極252係配置在閘介電層246上。另外，源 極區262a與没極區262b係配置在n型低壓元件區212a 之閘極252兩側的基底2〇〇中。其中，源極區262a與汲極 區262b的掺質型態係為η型。此外，源極區266a與沒極 區266b係配置在p型低壓元件區212b之閘極252兩側的 基底200中’其中源極區266a與汲極區266b的摻質型態 係為p型。 在一較佳實施例中’此低壓元件更包括掺雜區238、 240，分別配置在P型井區218與η型井區220中，且源極 區262a與汲極區262b及源極區266a與汲極區266b分別 配置於其中’以作為調整通道區之摻質濃度，進而調整低 壓元件的啟始電壓之用。 18 1325633 13364twf.doc/006 值得一提的是，雖然在上述實施例中係以記憶體及其 製程來說明本發明，但此記憶體元件中的可電除可程式化 之唯讀記憶胞(如圖4所示）’亦可以與其他種周邊電路之 元件整合在一起。換言之，本發明並未限定此可電除可程 式化之唯讀s己憶胞必須與本發明之周邊電路區之高壓元件 或低壓元件之製程一併進行。 因此，本發明之單獨針對可電除可程式化之唯讀記憶 胞的製粒例如是先於基底2〇〇的表面上分別形成穿隧層 244以及閘間介電層228，並且於閘間介電層228下方之 籲 基底200中形成摻雜區222’以作為控制閘極之用。接著， 於閘間介電層228與穿隨層244上形成浮置閘極248。之 後，於下方形成有穿隧層244之浮置閘極248兩側的基底 200中形成源極區258a與汲極區258b。而利用上述方法 所知·之了電除可程式化之唯讀記憶胞係由基底2〇〇、閘間 介電層228、穿隧層244、摻雜區222、浮置閘極248、源 極區258a與汲極區258b所構成。其中，閘間介電層228 以及穿隧層244係分別配置在基底之表面上。此外， 摻雜區222係配置在閘間介電層228底下之基底2〇〇中，· 且此摻雜區222係作為控制閘極之用。另外，浮置閘極248 係配置在穿隧層244以及閘間介電層228上。此外，源極 區258a與汲極區258b係配置在下方配置有穿隧層244之 浮置閘極248兩侧的基底2〇〇中。 綜上所述，本發明至少具有下述優點： 1.由於本發明之可電除可程式化之唯讀記憶胞形成於 19 1325633 13364twf.doc/006 p ’且控制閘極係以摻雜區之形式形 成於基γ ϋ此料為摘記憶胞結構。 2·由於本發明之可電除可程式化 置閉極形成於基底上，而控制閉極係以摻雜區 之元件之製輔合較輕易。 有早間極 3.本㈣之可電除可程式化之唯讀域胞，由於所 成之閘間介電層較厚，且源極區係形成於深摻雜區中。因 此’本發明之可電除可程式狀唯讀記憶胞可以與高壓元 件及低壓元件整合在—起。換言之，本發明之可電除可程 式化之唯讀記憶胞可以在1〇v至2〇v操作電壓中操作， 因而能與高壓元件整合在—起，財發明之可電除可程式 化之唯讀記憶胞亦可以在3V至6V操作電壓中操作，因 而也能與低壓元件整合在一起。 ' 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1B是習知的一種可電除可程式化之唯讀 §己憶體的製造流程剖面示意圖。 圖2A至圖2D是依照本發明之一較佳實施例的一種 記憶體元件之製造流程剖面示意圖。 圖3疋圖2A至圖2D之位於記憶胞區的可電除可程 1325633 13364twf.doc/006 式化之唯讀記憶胞的上視示意圖，且由’剖面所得之剖 面示意圖係如圖2A至圖2D之位於記憶胞區202之左邊 結構所示；由ΙΙ-ΙΓ剖面所得之剖面示意圖係如右邊結構 所示。 圖4是依照本發明之一較佳實施例的一種可電除可程 式化之唯讀記憶胞之剖面示意圖。 【主要元件符號說明】 100、200 :基底 102、244 :穿隧介電層 104、248 :浮置閘極(層） 106、228 :閘間介電層 108、222 ·控制閘極(層） 110 :堆疊式閘極結構 112a、258a、260a、262a、264a、266a :源極區 112b、258b、260b、262b、264b、266b :汲極區 202 :記憶胞區 204 :周邊電路區 206、210a、212b :高壓元件區 208、212a、212b :低壓元件區 214 :元件隔離區 216、242 :介電材料層 218、220 :井區 222、223、224、226、232、236、238、240、254、256、 257、268 :摻雜區 21 1325633 13364twf.doc/006 230、246 :閘介電層 250、252 :閘極 270 :間隙壁The following is a description of the structure obtained by the above method. Referring to Figures 2D and 3, the memory device of the present invention is constructed of a substrate 2, at least a memory cell, at least a high voltage device, and at least one low voltage component. The substrate 200 has a memory cell region 2〇2 and a peripheral circuit region 2〇4, and the peripheral circuit region 2〇4 includes a high voltage device region 2〇6 and a low voltage device region 208′ and these regions are separated by an element isolation region. 214 and isolated from each other. In a preferred embodiment, the high voltage element region 2〇6 further includes an n-type piezoelectric element region 210a and a p-type high voltage device region 21〇b, and further includes an n-type in the low-voltage component region 208. The low voltage element region 212a and the p-type low voltage element region 212b. Moreover, in another preferred embodiment, the substrate 2A further includes a plurality of p-type well regions 218 and n-type well regions 220. Wherein, 15 1325633 97-10-03 is located in the p-type well region 218 of the peripheral circuit region 204, and is disposed in the base 2〇〇 of the high-voltage element region 210a and the n-type low-voltage device region 212a, and the 11-type well region 220 is disposed in the p The high voltage element region 21〇b&n type low voltage device region 212b is in the substrate 200. In addition, the memory cell is disposed in the memory cell 2〇2, and is composed of the inter-gate dielectric layer 228, the tunneling layer 244, the doping region 222, the floating gate 248, the source region 258a, and the drain region. 258b is composed. Wherein, the inter-gate dielectric layer 228 is disposed on the substrate surface of the memory cell region 2〇2, and the thickness of the inter-gate dielectric layer 228 is greater than the thickness of the intervening layer 2 material. And the thickness of the inter-gate dielectric layer 228 is, for example, between Å and Å, and the thickness of the traversing layer 244 is, for example, 95 Å to (10 Å). η under layer 228 and this doping region 222 serves as a control gate, and the dopant type of 匕4 region 222 is, for example, n-type. The electro-acoustic 3 floating-closed pole 248 is arranged in the wear-through layer 24 to cut and close; the source region 258 & and the drain region 258b are arranged below the floating gate 248 of the layer 244 The base 2 on both sides (in the embodiment, the memory cell further includes - the thick exchange (4) from the doping region of the floating side of the 2〇2 to control the closed pole = ^ = 2 control gate - In part, the increase of the cell includes -36 b; in the embodiment, the memory h 236 is disposed in the 292-zone 258a and the bungee zone 25%, and the source b-system is disposed therein. Adjusting the dopant concentration of the channel region 16 1325633 13364twf.doc/006 to adjust the starting voltage of the memory device. In addition, in a preferred embodiment, the memory cell further includes a deep doped region disposed in the The doped region 236 under the tunnel layer 244, and the source region 258a is disposed in the deep doped region 257 for use as a breakdown voltage for increasing the source terminal of the memory device. In addition, the high voltage component is disposed at a high voltage. In the device region 2〇6, which is composed of the gate dielectric layer 230, the gate 250, the source regions 260a and 264a, and the drain regions 260b and 264b. The gate dielectric layer 23 is disposed on the surface of the substrate 200 of the high voltage device region 206, and the gate 250 is disposed on the gate dielectric layer 230. Further, the source region 260a and the drain region 260b are disposed at n. The high voltage element region 210a is in the substrate 200 on both sides of the gate 250. The source region 260a and the drain region 260b have a doping type of !! type. In addition, the source region 264a and the drain region 264b are The substrate 200 is disposed on both sides of the gate 250 of the p-type high voltage device region 21〇b, wherein the dopant type of the source region 264a and the drain region 264b is p-type. In a preferred embodiment The high voltage component further includes doped regions 224, 226' respectively disposed in the p-type well region 218 and the n-type well region 220, and the source region 260a and the drain region 260b and the source region 264a and the non-polar region 264b are respectively disposed on Wherein, as the adjustment of the dopant concentration of the channel region, the starting voltage of the voltage component is further adjusted. In addition, the high voltage component further includes a p-type of deep doped regions 254, 256' respectively disposed on both sides of the gate 250. In the well region 218 and the n-type well region 220, and the source region 260a and the drain region 260b and the source region 264a and the non-polar region 264b respectively In order to increase the breakdown voltage of the high voltage 17 1325633 97-10-03 component, the high voltage component further includes doped regions 232, 223 ' respectively disposed in the p-type well region 218 and the ^-well region 220 The substrate 200 under the isolation region 214 is used as a channel barrier. In addition, the low voltage component is disposed in the low voltage component region 208, and is provided by the gate dielectric layer 246, the gate 252, and the source region 262a. 266a and bungee regions 262b, 266b. The gate dielectric layer 246 is disposed on the surface of the substrate 200 of the low voltage device region 208, and the gate dielectric layer 230 located in the high voltage device region 2〇6 is thicker than the gate dielectric layer 246 located in the low voltage device region 2〇8. The thickness, such that the element formed in the high voltage element region 2〇6 can withstand the voltage of the south of the vehicle. The thickness of the gate dielectric layer 230 is, for example, between 450 angstroms and 500 angstroms' and the thickness of the gate dielectric layer 246 is, for example, between 60 angstroms and 70 angstroms. Further, a gate 252 is disposed on the gate dielectric layer 246. Further, the source region 262a and the non-polar region 262b are disposed in the substrate 2's on both sides of the gate 252 of the n-type low-voltage device region 212a. The doping type of the source region 262a and the drain region 262b is n-type. In addition, the source region 266a and the non-polar region 266b are disposed in the substrate 200 on both sides of the gate 252 of the p-type low voltage device region 212b. The dopant state of the source region 266a and the drain region 266b is p-type. . In a preferred embodiment, the low voltage component further includes doped regions 238, 240 disposed in the P-well region 218 and the n-well region 220, respectively, and the source region 262a and the drain region 262b and the source region. 266a and the bungee region 266b are respectively disposed in the 'in order to adjust the dopant concentration of the channel region, thereby adjusting the starting voltage of the low voltage component. 18 1325633 13364twf.doc/006 It is worth mentioning that although the invention is described in terms of memory and its process in the above embodiments, the programmable read-only memory cell in the memory component can be electrically separated ( As shown in Figure 4) ' can also be integrated with other peripheral circuit components. In other words, the present invention does not limit the process of erasing the read-only memory of the high-voltage component or the low-voltage component of the peripheral circuit region of the present invention. Therefore, the granulation of the present invention for electrically erasable programmable read only memory cells, for example, forms a tunneling layer 244 and a gate dielectric layer 228 on the surface of the substrate 2, respectively, and is in the gate. A doped region 222' is formed in the underlying substrate 200 below the dielectric layer 228 for use as a control gate. Next, a floating gate 248 is formed on the inter-gate dielectric layer 228 and the via layer 244. Thereafter, a source region 258a and a drain region 258b are formed in the substrate 200 on both sides of the floating gate 248 where the tunneling layer 244 is formed. The readable read-only memory cell system, which is known by the above method, is composed of a substrate 2, a gate dielectric layer 228, a tunneling layer 244, a doped region 222, a floating gate 248, and a source. The pole region 258a and the drain region 258b are formed. The inter-gate dielectric layer 228 and the tunneling layer 244 are respectively disposed on the surface of the substrate. In addition, the doped region 222 is disposed in the substrate 2 under the inter-gate dielectric layer 228, and the doped region 222 is used as a control gate. In addition, the floating gate 248 is disposed on the tunneling layer 244 and the inter-gate dielectric layer 228. Further, the source region 258a and the drain region 258b are disposed in the substrate 2 on both sides of the floating gate 248 where the tunneling layer 244 is disposed. In summary, the present invention has at least the following advantages: 1. Since the electrically readable programmable read only memory cell of the present invention is formed at 19 1325633 13364 twf.doc / 006 p ' and the control gate is doped region The form is formed on the base γ ϋ, which is a memory cell structure. 2. Since the electrically de-programmable shut-off pole of the present invention is formed on the substrate, it is relatively easy to control the closed-end system by the components of the doped region. There is a morning pole 3. This (4) can be electrically divided by the programmable read-only domain cell, because the dielectric layer formed by the gate is thicker, and the source region is formed in the deep doped region. Therefore, the electrically erasable and programmable read-only memory cell of the present invention can be integrated with a high voltage component and a low voltage component. In other words, the electrically readable and readable read-only memory cell of the present invention can be operated in an operating voltage of 1 〇v to 2 〇v, so that it can be integrated with the high-voltage component, and the programmable invention can be electrically de-programmed. The read-only memory cell can also operate from a 3V to 6V operating voltage and can therefore be integrated with low voltage components. Although the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1B are schematic cross-sectional views showing a manufacturing process of a conventional read-only readable memory. 2A through 2D are cross-sectional views showing a manufacturing process of a memory device in accordance with a preferred embodiment of the present invention. Fig. 3 is a top view of the readable read-only memory cell of the memory cell region of Fig. 2A to Fig. 2D, and the cross-sectional view obtained by the 'section is as shown in Fig. 2A to 2D is shown in the left structure of the memory cell region 202; the cross-sectional view obtained from the ΙΙ-ΙΓ profile is shown in the right structure. 4 is a cross-sectional view of an electrically erasable readable read only memory cell in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100, 200: substrate 102, 244: tunneling dielectric layer 104, 248: floating gate (layer) 106, 228: inter-gate dielectric layer 108, 222 · control gate (layer) 110: stacked gate structures 112a, 258a, 260a, 262a, 264a, 266a: source regions 112b, 258b, 260b, 262b, 264b, 266b: drain regions 202: memory cells 204: peripheral circuit regions 206, 210a 212b: high voltage component regions 208, 212a, 212b: low voltage component region 214: component isolation regions 216, 242: dielectric material layers 218, 220: well regions 222, 223, 224, 226, 232, 236, 238, 240, 254, 256, 257, 268: doped region 21 1325633 13364twf.doc / 006 230, 246: gate dielectric layer 250, 252: gate 270: spacer
22twenty two