TWI325627B - - Google Patents
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- TWI325627B TWI325627B TW095105417A TW95105417A TWI325627B TW I325627 B TWI325627 B TW I325627B TW 095105417 A TW095105417 A TW 095105417A TW 95105417 A TW95105417 A TW 95105417A TW I325627 B TWI325627 B TW I325627B
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- H10W20/023—
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九、發明說明: 【發明所屬之技術領域】 本發明係與半導體裳置之製造方 用於且古母、s Φ k 去有關,其係可良好利 用於八有貝通電極之薄型半導體 r,„ 卞等體裝置之製造上者。 【先剛技術】 近年來,伴隨著以電腦、通 料穷古M·〜 訊機裔為主之電子機器的小 孓化及问性旎化,在半導體 及古、# +办 、方面,小型化、高密度化 及同速化成為一項需求。基 眚们剂s® ’以所謂3次元晶片來 實見小型及向密度化之半導體 —。。 I 已經被研發出來;而 6亥3 -人兀日日片係把複數個半導體日 卞等髖日日片進打疊層而成者。在 把複數個晶片進行重疊的方 揭示之方法。 时法方面,譬如有專利文獻丨所 在此#考圖7,針對先前技術之半導體裝置之製造步 驟作說月。圖7⑷〜⑴係先前技術之半導體裝置 驟之剖面圖。 ^ 首先’在基板5G之表面側形成電路元件部5丨,獲得如圖 ()斤不之結構。接著’在基板50之表面側塗佈光阻,形 成光阻層;藉由將此層進行圖案A,形成具有開口部52a 之遮罩層52。接著’使用遮罩層52,藉由反應式離子蝕刻 (yRIE)等’把電路元件部51及由石mu所構成之基板5〇進 卜^形成距基板表面不足丨〇〇 μηι之非貫通孔53,獲得 如圖7(b)所示之結構。接著,在非貫通孔53之内壁面形成 、·邑緣膜54 ’獲得如圖7(c)所示之結構。接著,在絕緣膜上 形成作為電解電鐘之陰極的種晶層55,將之作為陰極,以 I08745.doc 1325627 金屬56進行填埋非貫通孔53之内部,獲得如圖7(d)所示之 結構。接著’把金屬56藉由化學機械研磨(CMP),去除非 貝通孔53以外之多餘的金屬,獲得如圖7(e)所示之結構。 接著’在基板50之電路元件部51側,介以由兩面膠帶等所 構成之黏著層57,把支持體58貼合後,把基板50之背面進 行研削,使填充於非貫通孔53之金屬56露出於基板之背面 側,獲得如圖7(f)所示之結構。接著,把基板5〇之背面進IX. Description of the Invention: [Technical Field] The present invention relates to the manufacture of semiconductor skirts and is related to the ancient mother and s Φ k , which can be well utilized for the thin semiconductor r of the octa-Beton electrode. „ 制造 卞 卞 。 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 And the ancient, #+ office, aspects, miniaturization, high density and speeding have become a demand. Based on the so-called three-dimensional wafers, we can see small and dense semiconductors. It has been developed; and the 6-Hai 3-People's Day film series is a combination of a plurality of semiconductor sundial and other hip-day films. The method of overlapping a plurality of wafers is disclosed. In the aspect of the invention, for example, there is a patent document for the manufacturing process of the prior art semiconductor device. Fig. 7 (4) to (1) are sectional views of the prior art semiconductor device. ^ First 'on the surface of the substrate 5G The side forms the circuit component portion 5丨, The structure is as shown in Fig. 2. Then, a photoresist is applied on the surface side of the substrate 50 to form a photoresist layer; by patterning the layer A, a mask layer 52 having an opening portion 52a is formed. By using the mask layer 52, the circuit element portion 51 and the substrate 5 composed of the stone mu are formed by reactive ion etching (yRIE) or the like to form a non-through hole 53 which is less than 基板μηι from the surface of the substrate. The structure shown in Fig. 7(b) is obtained. Then, the inner wall surface of the non-through hole 53 is formed, and the edge film 54' is obtained as shown in Fig. 7(c). Then, it is formed on the insulating film. The seed layer 55 of the cathode of the electrolysis clock is used as a cathode, and the inside of the non-through hole 53 is filled with I08745.doc 1325627 metal 56 to obtain a structure as shown in Fig. 7(d). The excess metal other than the non-beton hole 53 is removed by chemical mechanical polishing (CMP) to obtain a structure as shown in Fig. 7(e). Next, 'on the side of the circuit element portion 51 of the substrate 50, the double-sided tape is interposed. After the adhesive layer 57 is formed, the support body 58 is bonded together, and the back surface of the substrate 50 is ground to fill In the non-through hole 5653 of the metal substrate is exposed on the back surface side, is obtained as shown in FIG 7 (f) of the structure shown in FIG. Next, the back surface of the substrate into 5〇
仃選擇性蝕刻,獲得如圖7(g)所示之結構。接著,藉由化 子氣相"L積法(CVD),在基板50之背面堆疊SiN、Si〇2等之 絕緣膜59 ’獲得如圖7(h)所示之結構。#著,使用cMp 法除去絕緣膜59,使貫通電極之金屬56露出,獲得如圖 (0所不之結構。接著,除去支持基板58及黏著層57,獲 得如圖7(j)所示之結構。 藉由上述步驟,可製造具有貫通電極之半導體裝置。 專利文獻1:日本特開平10_223833號公報 (發明所欲解決之問題) 在上述製造方法方面,传彳p # I% p 你把非貫通孔藉由電解電鍍填充 金屬後,把S i基板薄化,使今麗+ ^ 士 1 使金屬路出於基板背側,藉由此 方式’形成貫通電極;然而, …、 在使用此一方法的的情形, S把金屬填充於非貫通巩 際,電鍍液難以供應到非貫通 孔的底部,且受電解電鍍時 吁斤產生之氫氣等的影響,金屬 ,4 ^ ^ ^ 生孔洞。再者,為了達成完全 填充,有必要採取使用添加 一 •土 Λ L,,. 剛之複雜、尚難度之電鍍方 法,如此也會使電鍍時間 门菱長。結果,導致處理成本增 108745.doc 1325627 多,此為一項問題。 本發明係有鑒於上述問題而研發,本發明之目的為:提 種半導體裝置之製造方法,㈣可藉由簡易方法,確 實填充導電體’形成貫通電極者。 【發明内容】 本發明之半導體裝置之製造方法的特徵為具備如下步 騾:在把第一支持體安裝於基板表面側的狀態下,把基= • 從其背面側進行薄化,把第一支持體從基板卸下,並I把 具有開口部之第二支持體安裝於基板背面側,在第二支持 體安裳之前或之後,在基板形成與第二支持體開口部連接 • 之貫通孔,在貫通孔内部形成絕緣膜,在基板之貫通孔内 部填充導電體。 (發明之效果) 在本發明中,由於係在以第一支持體支持基板的狀態 下,把基板進行薄化,故可防止薄化時之基板的破損。 • X ’在本發明中,係在藉由具有開口部之第二支持體支持 基板的狀態下,在與此開口部連接之基板貫通孔進行填充 導電體:因此’在進行藉由電解電鑛法的填充肖,電錄液 在貫通孔内順暢移動,使貫通孔之填充容易進行,且容易 .· 去除電解電鍍之際所產生的氫氣等。 【實施方式】 本發明之半導體裝置之製造方法的特徵為具備如下步 驟:在把第-支持體安裝於基板表面側的狀態下,把基板 從其背面側進行薄化,把第一支持體從基板卸下,並且把 I08745.doc 1325627 具有開口部之第二支持體安裝於基板背面側,在第二支持 體安裝之前或之後,在基板形成與第二支持體開口部連接 之貫通孔,在貫通孔内部形成絕緣膜,在基板之貫通孔内 部填充導電體。 本發明可利用下列所示各種型態實施。 1.第一實施型態仃 Selective etching to obtain a structure as shown in Fig. 7(g). Next, a structure shown in Fig. 7(h) is obtained by stacking an insulating film 59' of SiN, Si〇2 or the like on the back surface of the substrate 50 by a chemical vapor phase "L product method (CVD). #着, The insulating film 59 is removed by the cMp method, and the metal 56 of the through electrode is exposed to obtain a structure as shown in Fig. 10. Next, the support substrate 58 and the adhesive layer 57 are removed, and as shown in Fig. 7(j), According to the above-mentioned steps, a semiconductor device having a through electrode can be manufactured. Patent Document 1: Japanese Laid-Open Patent Publication No. Hei No. Hei. No. Hei. No. Hei. After the through hole is filled with metal by electrolytic plating, the Si substrate is thinned, so that the metal path is made of the back side of the substrate, and the through electrode is formed in this way; however, ... In the case of the method, S fills the metal in the non-through-penetration, and the plating solution is difficult to supply to the bottom of the non-through hole, and is affected by the hydrogen generated by the electrolytic plating, metal, 4 ^ ^ ^ hole. In order to achieve complete filling, it is necessary to adopt the plating method that adds the complexity of the soil, and the difficulty of plating. This will also make the plating time longer. As a result, the processing cost will increase by 108,745.doc 1325627 This is a problem. The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device, and (4) a method of reliably filling a conductor to form a through electrode by a simple method. The method of manufacturing a semiconductor device according to the present invention is characterized in that, in a state in which the first support is mounted on the surface side of the substrate, the base is made thinner from the back side, and the first support is provided. The second support having the opening is attached to the back surface side of the substrate, and the through hole of the second support opening is formed in the substrate before or after the second support is installed. An insulating film is formed in the inside of the through-hole, and a conductor is filled in the through-hole of the substrate. (Effect of the Invention) In the present invention, since the substrate is thinned while the substrate is supported by the first support, it can be prevented. In the present invention, in the state in which the substrate is supported by the second support having the opening, the base is connected to the opening. The through-hole is filled with the conductor: Therefore, the electro-recording liquid is smoothly moved in the through-hole by the filling of the electrolytic ore method, and the filling of the through-hole is facilitated, and it is easy to remove the electrolytic plating. [Embodiment] The method of manufacturing a semiconductor device according to the present invention is characterized in that the substrate is thinned from the back side thereof while the first support is mounted on the surface side of the substrate. A support is detached from the substrate, and a second support having an opening portion of I08745.doc 1325627 is mounted on the back side of the substrate, and the substrate is formed to be connected to the opening of the second support before or after the second support is mounted. The through hole forms an insulating film inside the through hole, and the inside of the through hole of the substrate is filled with a conductor. The invention can be practiced in various forms as shown below. 1. The first embodiment
本發明之第一實施型態之半導體裝置之製造方法的特徵 為具備如下步驟:把第一支持體安裝於基板表面側,把基 板從其背面側進行薄化,把第一支持體從基板卸下,把具 有開口部之第二支持體安裝於基板背面側,在基板表面形 成第一絕緣膜,在基板形成與第二支持體開口部連接之貫 通孔,在基板之貫通孔内部形成第二絕緣膜,在基板之貫 通孔内部填充導電體。 t 3於本實施型4之步驟,並非必須按照所記載之順序 實^適當變更順序之實施型態、或複數個步驟同時進行 之實施型態,亦屬於本發明之範圍之内。 ^1.第—支持體安裝步驟 一步驟係把第—支持體安裝於基板表面側。在第—支 —方面其材料、厚度及形狀並無特殊限制,但以具有 女裝於基板上可支持基板程度之剛性者為佳。第一支持體 :::以半導體(石夕等)、樹脂、玻璃等各種材料形成。第 孫以且^外形並無特殊限制,但為了可確實支持基板, A板# *、基板同程度或比基板更大外形(面積)者為佳。 由石夕基板等之半導體等所構成,其厚度以〜700 I08745.docA method of manufacturing a semiconductor device according to a first embodiment of the present invention is characterized in that the first support is mounted on the surface of the substrate, the substrate is thinned from the back side, and the first support is unloaded from the substrate. Next, the second support having the opening is mounted on the back surface side of the substrate, a first insulating film is formed on the surface of the substrate, and a through hole connected to the opening of the second support is formed in the substrate, and a second hole is formed in the through hole of the substrate. The insulating film fills the inside of the through hole of the substrate with a conductor. It is also within the scope of the present invention to t3 in the step of the present embodiment 4, and it is not necessary to change the order of the embodiment in the order described, or the embodiment in which the plurality of steps are simultaneously performed. ^1. First - Support Installation Step One step is to mount the first support on the substrate surface side. The material, thickness and shape of the first branch are not particularly limited, but it is preferable to have a degree of rigidity in which the base plate can support the substrate on the substrate. First support ::: It is formed of various materials such as semiconductor (Shi Xi et al), resin, and glass. The shape of the second sun is not particularly limited, but in order to reliably support the substrate, the A plate #*, the substrate is of the same degree or larger than the substrate (area). It is made up of semiconductors such as Shishi substrate, and its thickness is ~700 I08745.doc
" 8 - 1325627 μτη程度為佳。 !一支持體之對基板的安裝’係介以黏著層等來進行。 黏著層可由紫外線硬化性溆芏為 现“… 劑、熱硬化性黏著劑、雙面 上。❹靜電力等安裝於基板 第一支持體之對基板的安裝,可藉由在兩者之對抗面 全體設置接觸層、或藉由僅在—部份(譬如,中心 近旁)設置接觸層來進行均可。只要基板是藉由第Γ支持 體所支持,則採取其他任何方法進行安裝均可。又,通常 在安裝第一支持體之前,在基板表面先形成電路元件部。 電路元件部一般係由電晶體、- 庫-極體、電阻、電容器、感 料導體7^件、及把半導體元件之間作電性連接之配 線等所構成。電路元件部之形成方法並無特殊限制, 由一般之半導體製程來形成。 θ 卜2.基板薄化步驟 此步驟係把基板從其背面側進行薄化。基板薄化之方法 並無特殊限制, 削、化學研二:二:下方法來實施:機械研 電漿蝕刻或氣體蝕刻'乃至組合上述各者 :種以上之方法。又’為了製作薄型半導體裝置,基板之 肩化’係以使基板厚度成為30, μηι為佳。即使薄 上述厚度,由於基板在薄化之際受到第一支持體, 故不易破損。 ^ 1-3.第一支持體卸下步驟 下此:=把第-支持體從基板卸下。第-支持體的卸 在基板薄化之後進行。又,在把第-支持體安裝於 I08745.doc 丄乂5627 :板時,如有使用黏著層’則在此步驟中亦將點著層去 1-4·第二支持體安裝步驟 此步驟係把具有開σ部之第二支持體安裝於基板背面 安、帛-支持體之面的相反側之面)側。第二支持體的 係以在卸下第—支持體後進行為佳。因為,如在卸 Ζ第-支持體之前進行安裝第二支持體,則在卸下第 =際,第二支持體有可能脫落 '然而,如把第二支持 :基板時所使用之黏著劑、雙面膠帶的 财,在卸下第-支持體之際使第二支持體 此一來,亦可在卸H持體^ ^如 裝。 〜則仆乐一支持體的安 第二支持體亦可使用與第一支捭 物m枝 Ί支持㈣樣之材料與外形之 ”於二:可使用與第一支持體相同的方法, 裝:基板上。但第二支持體之材料、外 門口,… 持體不同。第二支持體係具有開口部。 開口Μ使用料作機械方式 刻技術等形成亦可。 切由先子微影及姓 】-5.第一絕緣膜形成步驟 在二驟极表面形成第一絕緣膜。第-絕緣膜可以 在忒田轭可中一般所使用之材料與方 切膜或氫化㈣等所構成。此:情:絕第緣膜 把===:::Γ。再者,第-絕— 衣㈣料樹脂作旋轉塗佈方式形成,亦可 108745.doc 1325627 藉由把聚醯亞胺等進行電沉積方式形成❺ it由在基板貝通孔形成步驟之前,士 J 在基板表面形成第一 絕緣膜,可防止基板表面遭污¥。# _ 這可木第一絕緣膜形成步驟亦 可在基板貫通孔形成步驟之後進彳 〜说琨仃,此一情形,亦可盥 二絕緣膜形成步驟同時進行。此1形,以-次步驟Ϊ可 在基板表面與基板貫通孔内部兩方形成絕緣膜故可減少 步驟數。又,如為無需第一絕緣 %犋的it形,則可不用實施 此一步驟。 6.基板貫通孔形成步驟 此步驟係在基板形成與第二支持體開口部連接之貫通 孔。基板之貫通孔的大小並無特殊限制,但以比第二支持 體開口部小為佳。此一情形,作兔7 —说条a ' 月仏係為了在導電體填充步驟使 電錄液在貫通孔内部順暢移動。貫通孔之橫斷面(與基板 表面平行之面)的形狀’可形成為正方形、長方形或圓形 等。貫通孔亦可藉由如下方式形成:在基板表面側或背面 側(亦即’第二支持體上)形成光阻圖案,把此光阻圖案作 為蝕刻遮罩’把基板進行蝕刻。再者,貫通孔亦可藉由如 下方式形成:把具有開口部之第二支持體作為遮罩,把基 板進行㈣。如把第二支持體作為遮罩,則無需使用用 形成光阻圖案的遮罩;此外,還有如下優點:無需把光阻 圖案與第二支持體開口部進行校準。 基板貫通孔的形成,可在第二支持體安裝之前或之後進 行。如為在第二支持體安裝之前形成基板貫通孔的情形, 則在安裝第二支持體之際,應對基板貫通孔進行第二支持 108745.doc" 8 - 1325627 μτη degree is better. The mounting of a support to the substrate is performed by an adhesive layer or the like. The adhesive layer can be made of ultraviolet curing sputum, such as "agent, thermosetting adhesive, double-sided, ❹ electrostatic force, etc., mounted on the substrate of the first support of the substrate, and can be used in the opposing surface of the substrate. All of the contact layers may be provided, or may be provided by merely providing a contact layer in a portion (for example, near the center). As long as the substrate is supported by the second support, any other method may be used for mounting. Generally, before mounting the first support, the circuit component portion is first formed on the surface of the substrate. The circuit component portion is generally composed of a transistor, a library, a resistor, a capacitor, a sensing conductor, and a semiconductor component. The circuit element portion is formed by wiring or the like. The method of forming the circuit element portion is not particularly limited, and is formed by a general semiconductor process. θ 2 2. Substrate thinning step This step is to thin the substrate from the back side thereof. There is no special limitation on the method of thinning the substrate, and the second method is as follows: the following method is used: mechanical grinding plasma etching or gas etching, or even combining the above methods: more than one method. 'To make a thin semiconductor device, the shoulder of the substrate' is such that the thickness of the substrate is 30, μηι. Even if the thickness is thin, the substrate is subjected to the first support when it is thinned, so it is not easily broken. ^ 1-3 The first support removal step is as follows: = the first support is removed from the substrate. The unloading of the first support is performed after the substrate is thinned. Further, the first support is mounted on I08745.doc 5627: When the board is used, if the adhesive layer is used, then the layer will be layered in this step. 1-4. Second support mounting step This step is to mount the second support having the open σ portion on the back surface of the substrate. , the side of the opposite side of the surface of the support body. The second support body is preferably carried out after the first support is removed. Because the second support body is installed before the first support body is removed. When the second support is removed, the second support may fall off. However, if the second support: the adhesive used in the substrate, the double-sided tape is used, the first support is removed. The second support body can also be unloaded in the H holding body ^ ^ such as loading. ~ Servant one support Ann Ί second supports may also be used with the weed was first branch comp m branches of the support material and (iv) the shape of "in two: a first support member may be used with the same method, apparatus: on a substrate. However, the material of the second support, the outer door, ... are different. The second support system has an opening. The opening Μ can be formed by using a material as a mechanical method or the like. Cutting by the first son lithography and surname 】-5. First insulating film forming step A first insulating film is formed on the surface of the second electrode. The first insulating film can be composed of a material generally used in the yoke yoke and a square film or hydrogenation (tetra). This: Love: the absolute edge film Put ===:::Γ. Furthermore, the first-coating (four) material resin is formed by spin coating, or 108745.doc 1325627 is formed by electrodeposition of polytheneimide or the like by 电 it is formed by the step of forming the via hole in the substrate. J The first insulating film is formed on the surface of the substrate to prevent the substrate surface from being contaminated. # _ This wood first insulating film forming step can also be performed after the substrate through-hole forming step, in which case the second insulating film forming step can be simultaneously performed. In this 1-shape, an insulating film can be formed on both the surface of the substrate and the inside of the through-hole of the substrate in a step-by-step manner, so that the number of steps can be reduced. Further, if the IT shape without the first insulation % 无需 is required, this step may not be performed. 6. Substrate through hole forming step This step forms a through hole in which the substrate is connected to the opening of the second support. The size of the through hole of the substrate is not particularly limited, but is preferably smaller than the opening of the second support. In this case, the rabbit 7-speaker a' month is used to smoothly move the electro-recording liquid inside the through-hole in the electric conductor filling step. The shape of the cross section of the through hole (the surface parallel to the surface of the substrate) can be formed into a square, a rectangle or a circle. The through hole may be formed by forming a photoresist pattern on the surface side or the back side of the substrate (i.e., on the second support), and etching the substrate by using the photoresist pattern as an etch mask. Further, the through hole may be formed by using a second support having an opening as a mask to carry out the substrate (4). If the second support is used as a mask, it is not necessary to use a mask for forming a photoresist pattern; in addition, there is an advantage that it is not necessary to align the photoresist pattern with the opening of the second support. The formation of the substrate through-holes can be performed before or after the second support is mounted. If the substrate through-hole is formed before the second support is mounted, the second support of the substrate through-hole should be performed when the second support is mounted.
二支持體開口與基板貫通孔連接。 此步驟係在基板之貫通孔内部形成第二 、緣膜可以在玆蚩益蝰* > ....The two support openings are connected to the substrate through holes. This step is to form a second, rim film inside the through hole of the substrate.
二絕緣膜。第二絕 中一般所使用之材料與方法形成。第 絕緣膜相同或不同之材料、方法、膜 厚形成。 1-8.導電體填充步驟 φ 此步驟係在基板之貫通孔内部形成導電體。導電體之對 基板貫通孔内部的填充方法,並無特殊限制,亦可用CM 法、濺鍍法等來實施。但導電體的填充係以採取如下方法 • $佳:在貫通孔内部形成導電體種晶層,利用此種晶層, - 藉由電解電鍍法把導電體進行填充。因為’在本發明中, 電鍍液在貫通孔内部順暢流動’使貫通孔的填充容易進 行,且容易去除電解電鍍之際所產生的氫氣等。此一情 形,導電體係以銅或含銅之合金所構成為佳,但如為電解 泰 電鍍法可進行填充者,則亦可使用其他金屬等。再者,在 導電體填充之後,通常係藉由CMP法等把位於貫通孔以外 部份之導電體(譬如,基板表面上之導電體)去除。導電體 種晶層係以如下者為佳:可用CVD法、濺鍍法等形成,且 厚度為單原子層之厚度〜200 ηιη。因為,如具有此程度之 厚度’可充份發揮作為電解電鍍之種晶層的功能。又,導 電體種晶層係以介以阻障層形成於貫通孔内部為佳。阻障 層係指’具有防止導電體原子擴散到基板等的功能之層。 藉由形成阻障層,可防止基板等遭受來自導電體原子的污 iOS745.doc J2 1325627 可用CVD法、賤錄 染。阻障層係由TiN或TaN等所構成 法等來形成。 1-9.第二支持體卸下步驟 本發明之方法可更且偌如势 ^ ^ , 更^備把第二支持體從基板卸下之步 驟0如為介以黏菩居加楚__ 一支持體安裝於基板的情形,則 在此步驟亦把黏著層去除。又, 即馮第一支持體並不造成 干擾的情形,則不卸下亦可。Two insulating film. The second intermediate is generally formed using materials and methods. The first insulating film is formed of the same or different materials, methods, and film thicknesses. 1-8. Conductor Filling Step φ This step forms a conductor inside the through hole of the substrate. The method of filling the inside of the substrate through-hole is not particularly limited, and may be carried out by a CM method, a sputtering method, or the like. However, the filling of the conductor is carried out as follows: • Good: a conductor seed layer is formed inside the through hole, and the conductor is filled with the conductor by electrolytic plating. In the present invention, the plating solution flows smoothly inside the through hole, and the filling of the through holes is facilitated, and hydrogen gas or the like generated during electrolytic plating is easily removed. In this case, the conductive system is preferably composed of copper or a copper-containing alloy. However, if the electroplating method can be used for filling, other metals can be used. Further, after the electric conductor is filled, the electric conductor (e.g., the electric conductor on the surface of the substrate) located outside the through hole is usually removed by a CMP method or the like. The conductor seed layer is preferably formed by a CVD method, a sputtering method, or the like, and has a thickness of a single atomic layer of ~200 ηιη. This is because, if it has such a thickness, it can fully function as a seed layer for electrolytic plating. Further, it is preferable that the conductor seed layer is formed in the through hole through the barrier layer. The barrier layer means a layer having a function of preventing diffusion of a conductor atom to a substrate or the like. By forming the barrier layer, it is possible to prevent the substrate or the like from being contaminated by the atoms of the conductor. iOS 745.doc J2 1325627 can be logged by CVD or ruthenium. The barrier layer is formed by a method such as TiN or TaN. 1-9. Second Support Removal Step The method of the present invention can be more and more advantageous, and the step of removing the second support from the substrate is as follows: In the case where a support is mounted on the substrate, the adhesive layer is also removed at this step. Further, if the von first support does not cause interference, it may not be removed.
2.第二實施型態 本發明之第二實施型錐:^主遵_贼壯$ 只她尘九、之+導體裝置之製造方法的特徵 為具備如下步驟:把篦—古姓挪—抽& u 寺體女裝於基板表面側,把基 板從其背面側進行薄化,把第-支持體從基板卸下,把具 有開口部之第二支持體安裝於基板背面側,而該開口部係 比形成於基板之貫通孔更大者;在基板表面形成第一絕緣 臈:在基板形成與第二支持體開口部連接之貫通孔,在基 板背面形成溝槽’在基板之溝槽及貫通孔内部形成第二絕 緣膜,在基板之溝槽及貫通孔内部填充導電體。 針對第一實施型態所作之說明,只要不違反其旨趣,則 亦適用於本實施型態。 本實施型態與第一實施型態的相異之處在於,第二支持 體具有比形成於基板之貫通孔更大的開口部,且具備在基 板背面形成溝槽之步驟。雖然,基板背面之溝槽係以使用 第二支持體作為遮罩來形成為佳,但亦可以如下方式:在 基板背面形成光阻圖案,使用此光阻圖案為遮罩來形成。 此外’藉由在形成於基板之溝槽及貫通孔内部進行填充導 108745.doc 13 1325627 電體,可製造具有溝槽配線及貫通電極之半導體製造裝 置。 ’ 3.第三實施型態 本發明之第三實施蜇態之半導體裝置的特徵為:在基板 表面形成電路元件部,形成貫通基板與電路元件部之貫通 孔在貫通孔之基板與電路元件部之側部、電路元件部之 表面形成絕緣膜,在貫通孔之内部填充導電體,具有從基 板背面到電路元件部表面之導體層。 針對上述實施型態所作之說明’只要不違反其旨趣,則 亦適用於本實施型態。本半導體裝置可使用上述半導體裝 置之製造方法進行製造。本發明之半導體裝置由於在基板 表面具有絕緣膜,故可保護電路元件部。 以下’針對本發明之實施例作具體說明。 第一實施例 圖1係第一實施例之半導體裝置之製造步驟之剖面圖。 以下’參考圖1,針對本實施例作說明。 h第—支持體安裝步驟 首先,在基板10上形成具有特定功能之電路元件部n。 接著’介以由黏著劑所構成之黏著層i7a,把第一支持體 18安裝在已獲得之基板的表面(形成有電路元件部Η之面) 側,獲得如圖1(a)所示之結構。第一支持體18係直徑8吋、 厚300 700 μΓη程度(理想為5〇〇 μιΏ)之矽板,且具有與基板 同大小第支持體〗8之對基板10的安裝,可藉由如 下方式進行·譬如把聚醯亞胺樹脂之黏著劑以】〇〇 之厚 J0S745.doc •14- 1325627 度塗佈於基板1 〇,介以此黏著劑,把第一支持體丨8按壓於 基板’在該狀態下作3 1 (TC、3 0分的熱處理,使黏著劑硬 化。又’在黏著劑方面,亦可使用UV硬化型黏著劑,此 一情形,係以100〜200 μπι之厚度塗佈於基板1〇,介以此黏 著劑’把第一支持體18按壓於基板,加熱到1〇〇〜15〇<>c, 在該狀態下進行UV照射,使黏著劑硬化。又,亦可以雙 面膠帶取代黏著劑。 2. 基板薄化步驟 接著’在第一支持體18已安裝的狀態,使基板1〇之背面 側後退’獲得如圖i (b)所示之結構。在此,基板丨〇之後 退,係使用機械研削、化學研磨、電漿蝕刻或氣體蝕刻等 加工技術來進行。在處理條件方面,譬如,採取機械研削 的情形’粗研削係使用#300〜200程度之砥石,在研削後, 最終修飾研削係使用#2〇〇〇程度之砥石進行研削。紙石之 方疋轉數设為2000〜3000 rpm/min。後退後之基板1〇之厚度 係以3 0〜1 〇〇 pm為佳。 3. 第一支持體卸下步驟 接著,把在電路元件部u表面之第一支持體18卸下。支 持體18之卸下,係藉由如下方式進行:在單乙醇、二甲基 甲醯胺之剝離液中以溫度約12(rc浸泡基板,把黏著層丄化 除去。 4. 第一支持體卸下步驟 接著,在所獲得之基板的背面側,介以由黏著劑所構成 之黏著層17b,進行安裝具有開口部2〇a之第二支持體。 108745.doc 15 1325627 第二支持體20之直徑、厚度、材料及對基板的安裝方法, 係與第一支持體18相同。第二支持體2〇具有開口部2〇& ; 開口部2〇&之直徑為10, μΓΠ程度,其係比在後步驟形成 於基板10之貝通孔更大。第二支持體之外觀係如圖5(c)所 示般’具有多個開口部。 5 ·第一絕緣膜形成步驟 接著,在基板ίο之表面側形成厚1〇〇〜5〇〇〇 nm之第一絕 φ ’緣膜19 ’獲得如圖叫所示之結構。第-絕緣膜由石夕氧 化膜或氮化矽膜等所構成,譬如係以電漿CVD法所形成。 如為矽氧化膜的情形,係以如下條件形成:氣體:TE〇s • _ 叫/〇2 65〇cc、壓力:8·5 Torr、P〇wer : 8〇〇 w、温 度:50〜100°C。又,第—絕緣膜19亦可藉由把聚醯亞胺、 環氧樹脂等樹脂,以1000〜5000 rpm/min的速度,進行旋 轉塗佈,形成100〜5000 nm之厚度。又,第一絕緣膜19亦 可為疊層型絕緣膜,其係由矽氧化膜及氮化矽膜依照此順 • 序進行疊層而成者。疊層型絕緣膜之厚度為100〜5000 nm 其中氮化砂膜之膜厚為20〜500 ηηι程度。 在本實施例中,第一絕緣膜19係形成於基板10之表面 側。如先前技術般,在基板背面亦即,已實施基板薄化之 面形成絕緣膜的情形(參考圖7(h)),因在薄化後之加工面 無法平坦,故絕緣膜無法均一形成。但如本實施例般,在 基板表面側形成絕緣膜,則絕緣膜容易均—形成。 又’與先前技術不同’在本實施例中,係在銅填充步驟 之前,進行形成絕緣膜。基於此因,具有如下優點:絕緣 108745.doc 1325627 膜形成裝置無遭鋼污染之虞,無需進行裝置的專用化。 6.基板貫通孔形成步驟 接著,在基板10之表面側之第一絕緣膜19上,進行塗佈 光阻’形成光阻層;藉由把此層圖案化,形成具有開口部 仏之遮罩層12,而開口部⑵係與形成於基板】。之貫通孔 對應者。接著’利用遮罩層12,藉由反應式離子飯刻 _)等方法’把第—絕緣膜19、電路元件部u、基板 、及黏著層17b依序進行㈣,在基板1G形成貫通孔 13,獲得如圖1(d)所示之結構。貫通孔13由於與第二支持 體20之開口部20a連接(譬如,由於兩者之中心為一致),因 此貫通孔13不會因支持體2〇而阻塞。在RIE的條件方面, 如第一絕緣膜19為氮化矽膜的情形係以CF4/〇2系氣體,基 板10之矽係以SF0/〇2系氣體進行蝕刻(使用氣體: 150CC/O2 50〜l〇〇CC、壓力:1〇〇〜3〇〇 mT〇rr ' Rf p。爾: 100〜500 wp電路元件部u之矽氧化膜及黏著層i7b係以 CF4/〇2系氣體進行蝕刻。 蝕刻時係以不使支持體18剝離的溫度,亦即,以〜1㈧ c進行處理為佳。在貫通孔13的大小方面,正方形之— 邊、或圓形之直徑、或長方形之長邊為500 μιη以下、或 100 μηι以下、最好在5〇 μηι以下,乃至卜1〇 μιη程度亦可。 7·第二絕緣膜形成步驟 接著,在去除遮罩層12後,在貫通孔π内部(亦即,在 貫通孔之側壁)形成第二絕緣膜14。獲得如圖1(勾所示之結 構。言如,貫通孔1 3之一邊為10 μηι的情形,第二絕绫膜 108745.doc 17 1325627 14之厚度係形成為100〜200 nm程度。第二絕緣膜14係以電 漿CVD法形成,其條件為,溫度:4〇〇它、氣體:TE〇s 680 mg/02 650cc、壓力:8.5 T〇rr、p〇wer : 8〇〇 w、沉積 速率:100〜200 nm/min。使用電漿CVD法的理由為:即使 膜厚較薄,但涵蓋範圍大、膜質亦佳。如貫通孔13之一邊 為1〇〇 μιη,則第二絕緣膜14係以2〜3 μιη程度之厚度形成。 如貫通孔13之尺寸較大,則其表面積增大,故寄生電容亦 φ 變大。基於此因,故加大膜厚,以降低寄生電容。再者, 第二絕緣膜Μ亦可以如下方式形成:藉由在15〇。〇程度之 聚醯亞胺溶液中,以矽基板為電極,施加電壓,在基板表 • 面析出聚醯亞胺(亦即,藉由把聚醯亞胺進行電沉積)。 8.銅填充步驟 8-1.阻障層及銅種晶層形成步驟 接著,從基板ίο之表面側,在基板10表面及貫通孔13内 部,介以阻障層,形成銅種晶層15,獲得如圖i(f)所示之 • 結構。阻障層係由TiN層層等所構成,厚度為5〜15〇 nm,但以形成為1〇 nm為佳。銅種晶層。之厚度係介於單 原子層之厚度到2〇〇 nm,但以形成為1〇〇 nm為佳。兩者係 以CVD法或淹鍍法等形成。如使用cvd法的情形,彻層 係使Τ!(Ν((:2Η5)2)4與贿3或仏進行反應,在15〇m溫度成 長而成。銅種晶層1 5係以Cu(hfac)(tmvs)為原料以溫度 15〇°C 形成。 & 8-2.鍍銅步驟 接著’利用銅種晶層15,藉由電解電鍍法,在貫通孔Η 108745.doc -18· 1325627 内填=銅16,獲得如圖1(g)所示之結構。由於第二支持體 2〇在貫通孔13的部份有開口部2〇a,故電鑛液在貫通孔^ 内順暢流通。基於此因,可清除氣氣泡,且以良好效率引 起:應種之擴散,故可抑制孔洞的產生,使完全填充變得 可能;而上述氫氣泡係藉由電性分解所產生,而附著於貫 通孔13内之表面者。具去 炎 每 ^冉者,為了貫現完全填充,防止造成 參差不齊,故鍍銅以進行到基板表面上之厚度達5〜i〇 程度為佳。在此,就鍍銅的條件而t,係以CuS〇4 · 5H2〇、H2S〇dC1•為電錄液,在溫度饥實施電解電鑛法 而進行。 8-3XMP步驟 接著,藉由CMP法,把第一絕緣膜19上之銅16去除,僅 在貫通孔13内殘留銅16,獲得如圖1(h)所示之結構。在本 實施例中’銅16係在第-絕緣膜19上形成,由於第一絕緣 膜19通常比基板背面平坦,故藉由CMp法之銅“的去除, 較容易進行。 9.第二支持體卸下步驟 接著,把半導體基板10背面之第二支持體2〇卸下,獲得 如圖l(i)所示之結構。第二支持體2〇的卸下係藉由如下方 式進行:纟單乙醇、二甲基甲酿胺之剝離液中以溫度約 12〇°C浸泡基板,把黏著層17b除去。 藉由以上步驟,製作具有貫通電極之半導體裝置。 第二實施例 圖2係第二實施例之半導體裝置之製造步驟之剖面圖。 J08745.doc •19· 丄奶627 以下,參考圖2,針對本實施例作說明。 1 ·第支持體安裝步驟 :先,糟由與第一實施例同樣的方法,在基板ι〇之表面 側安裝第一支持體18,獲得如圖2(a)所示之結構。 2 ·基板薄化步驟 接著’藉由與第—實施例同樣的方法, 化’獲得”2(b)料之結構。 4 3. 第一支持體卸下步驟 首先,藉由與第一實施例同樣的方法,把第一支持體“ 從基板卸下。 4. 第二支持體安裝步驟 接著,藉由與第一實施例同樣的方法,在基板1〇之背面 側安裝第二支持體21。 +在本實施例中,$ 了在後步驟在基板^ 〇形成貫通孔1 3, 第-支持體21係被當作遮罩使用,故其具有與形成於基板 10之貫通孔13相同大小的開口部21a。 5·第一絕緣膜形成步驟 接著,藉由與第一實施例同樣的方法,在基板1〇之表面 側形成第一絕緣膜19,獲得如圖2(c)所示之結構。 6·基板貫通孔形成步驟 接著以第一支持體21作為遮罩,藉由反應式離子姓刻 (RIE)等方法,把黏著層17b、基板1〇、電路元件部、及 第一絕緣膜19依序進行蝕刻,在基板〗〇形成貫通孔〗3,獲 传如圖2(d)所示之結構。蝕刻之條件係與第一實施例相 I08745.doc 1325627 同。又,在此步驟中,第二支持體21亦被以基板1〇厚度 (30〜100 μηι程度)+過度蝕刻量,進行蝕刻,而使厚度減 小’但如殘留可在其後之步驟進行處理之程度的厚度的 话,此一減少並不構成問題(必要時,應使用已考慮減少 量之厚度的支持體)。 7. 第二絕緣膜形成步驟 接著,藉由與第一實施例同樣的方法,在貫通孔丨3内部 形成第二絕緣膜14,獲得如圖2(e)所示之結構。 8. 銅填充步驟 接著,藉由與第一實施例同樣的方法,介以阻障層,形 成銅種晶層15(圖2(f)),藉由電解電鍍法,在貫通孔^内 部填充銅16(圖2(g)),藉由CMP法除去不要之銅(圖2(h))。 9. 第一支持體却下步驟 接著,藉由與第一實施例同樣的方法,把第二支持體以 卸下,獲得如圖2 (i)所示之結構。 在本結構之半導體裝置之製造方法上,以第二支持體^ 為遮罩,可在基板上形成貫通電極圖#,因此可減少遮罩 片,及光阻數量,故可達成縮短TAT(TurnAr〇undTime從 接單到交貨為止的時間)及降低成本。 第三實施例 圖3係第三實施例之半導體裝詈 、 干守姐衣直之製造步驟之剖面圖。 、下參考圖3,針對本實施例作說明。 L第一支持體安裝步驟 首先’藉由與第—實施例同樣的方法,在基板H)之表面 108745.doc 1325627 側安裝第—支持體18,獲得如圖3(a)所示之結構 2 ·基板薄化步驟 進行基板10之薄 把第一支持體i 8 接著,藉由與第一實施例同樣的方法 化’獲得如圖3(b)所示之結構。 3·第一支持體卸下步驟 接著’藉由與第一實施例同樣的方法 從基板卸下。2. Second Embodiment The second embodiment of the present invention is characterized in that the method of manufacturing the conductor device is characterized by having the following steps: & u Temple body on the substrate surface side, thinning the substrate from the back side, removing the first support from the substrate, and mounting the second support having the opening on the back side of the substrate, and the opening The portion is larger than the through hole formed in the substrate; the first insulating layer is formed on the surface of the substrate: a through hole is formed in the substrate to be connected to the opening of the second support, and a groove is formed on the back surface of the substrate A second insulating film is formed inside the through hole, and a conductor is filled in the trench and the through hole of the substrate. The description of the first embodiment is also applicable to the present embodiment as long as it does not violate its purpose. The present embodiment is different from the first embodiment in that the second support has a larger opening than the through hole formed in the substrate, and has a step of forming a groove on the back surface of the substrate. Although it is preferable that the groove on the back surface of the substrate is formed using a second support as a mask, a photoresist pattern may be formed on the back surface of the substrate, and the photoresist pattern may be formed as a mask. Further, a semiconductor manufacturing apparatus having a trench wiring and a through electrode can be manufactured by filling the inside of the trench formed in the substrate and the via hole with a dielectric of 108745.doc 13 1325627. 3. Third Embodiment A semiconductor device according to a third embodiment of the present invention is characterized in that a circuit element portion is formed on a surface of a substrate, and a through hole penetrating through the substrate and the circuit element portion is formed in the substrate and the circuit element portion of the through hole. An insulating film is formed on the surface of the side portion and the circuit element portion, and a conductor is filled in the through hole to have a conductor layer from the back surface of the substrate to the surface of the circuit element portion. The description of the above embodiment is also applicable to the present embodiment as long as it does not violate its purpose. The semiconductor device can be manufactured by using the above-described method of manufacturing a semiconductor device. Since the semiconductor device of the present invention has an insulating film on the surface of the substrate, the circuit element portion can be protected. The following 'specific examples are set forth for the present invention. First Embodiment Fig. 1 is a cross-sectional view showing a manufacturing step of a semiconductor device of a first embodiment. The following description will be made with reference to Fig. 1 for the present embodiment. h-Supporting body mounting step First, a circuit component portion n having a specific function is formed on the substrate 10. Then, the first support 18 is attached to the surface of the obtained substrate (the surface on which the circuit component portion is formed) by the adhesive layer i7a composed of an adhesive, and is obtained as shown in Fig. 1(a). structure. The first support body 18 is a ruthenium plate having a diameter of 8 吋 and a thickness of 300 700 μΓη (preferably 5 〇〇μιΏ), and has a substrate 10 of the same size as the substrate, and can be mounted by the following method. For example, if the adhesive of the polyimide resin is applied to the substrate 1 by the thickness of J0S745.doc • 14-1325627, the first support 丨8 is pressed against the substrate by the adhesive. In this state, 3 1 (TC, 30 ° heat treatment, the adhesive is hardened. Also - in the adhesive, UV curing adhesive can also be used, in this case, coated with a thickness of 100 ~ 200 μπι The substrate 1 is placed on the substrate, and the first support 18 is pressed against the substrate by the adhesive, and heated to 1 〇〇 to 15 〇 <> c, and UV irradiation is performed in this state to harden the adhesive. Alternatively, the adhesive may be replaced by a double-sided tape. 2. The substrate thinning step is followed by 'retracting the back side of the substrate 1' in a state where the first support 18 is mounted' to obtain a structure as shown in Fig. i(b). Here, the substrate is retracted by mechanical grinding, chemical grinding, plasma etching or In terms of processing conditions, for example, in the case of mechanical grinding, the rough grinding system uses a #300 to 200 degree vermiculite, and after grinding, the final modified grinding system uses #2〇〇〇 degree of meteorite. Grinding is carried out. The number of revolutions of the paper stone is set to 2000 to 3000 rpm/min. The thickness of the substrate 1 after retraction is preferably 30 to 1 pm. 3. First support removal step Next, The first support 18 on the surface of the circuit component portion u is removed. The removal of the support 18 is carried out by using a temperature of about 12 in a stripping solution of monoethanol and dimethylformamide. The substrate is immersed to remove the adhesive layer. 4. First support removal step Next, on the back side of the obtained substrate, an adhesive layer 17b composed of an adhesive is applied to have an opening 2〇a The second support body is 108745.doc 15 1325627 The diameter, thickness, material and mounting method of the second support body 20 are the same as those of the first support body 18. The second support body 2 has an opening portion 2〇&;; opening 2〇& diameter 10, μΓΠ The degree is larger than the beacon hole formed in the substrate 10 in the subsequent step. The appearance of the second support is 'having a plurality of openings as shown in Fig. 5(c). 5 · First insulating film forming step Next, a first insulating φ 'edge film 19' having a thickness of 1 〇〇 5 5 nm is formed on the surface side of the substrate ίο to obtain a structure as shown in the figure. The first insulating film is formed by a ruthenium oxide film or nitrided. The ruthenium film or the like is formed by, for example, a plasma CVD method. In the case of a ruthenium oxide film, it is formed under the following conditions: gas: TE〇s • _ call / 〇 2 65 〇 cc, pressure: 8.5 Torr, P〇wer: 8〇〇w, temperature: 50~100 °C. Further, the first insulating film 19 may be spin-coated at a speed of 1000 to 5000 rpm/min by a resin such as polyimide or epoxy resin to form a thickness of 100 to 5000 nm. Further, the first insulating film 19 may be a laminated insulating film which is formed by laminating a tantalum oxide film and a tantalum nitride film in accordance with this order. The thickness of the laminated insulating film is 100 to 5000 nm, and the film thickness of the nitrided film is 20 to 500 ηηι. In the present embodiment, the first insulating film 19 is formed on the surface side of the substrate 10. As in the prior art, in the case where the insulating film is formed on the back surface of the substrate, that is, the surface on which the substrate has been thinned (refer to Fig. 7 (h)), since the processed surface after thinning cannot be flat, the insulating film cannot be uniformly formed. However, as in the present embodiment, an insulating film is formed on the surface side of the substrate, and the insulating film is easily formed uniformly. Further, unlike the prior art, in the present embodiment, an insulating film is formed before the copper filling step. For this reason, it has the following advantages: Insulation 108745.doc 1325627 The film forming apparatus is free from contamination by steel and does not require specialization of the apparatus. 6. Substrate through hole forming step Next, a photoresist layer is formed on the first insulating film 19 on the surface side of the substrate 10 to form a photoresist layer; by patterning the layer, a mask having an opening portion is formed. The layer 12 and the opening (2) are formed on the substrate. Corresponding hole. Then, the first insulating film 19, the circuit element portion u, the substrate, and the adhesive layer 17b are sequentially formed by the method of "using the mask layer 12 by a reactive ion ray" or the like, and the through holes 13 are formed in the substrate 1G. , the structure shown in Figure 1 (d) is obtained. Since the through hole 13 is connected to the opening 20a of the second support 20 (for example, since the centers of the two are identical), the through hole 13 is not blocked by the support 2〇. In terms of the conditions of the RIE, for example, the case where the first insulating film 19 is a tantalum nitride film is a CF4/〇2 gas, and the tantalum of the substrate 10 is etched with an SF0/〇2 gas (gas: 150CC/O2 50). ~l〇〇CC, pressure: 1〇〇~3〇〇mT〇rr ' Rf p.: 100~500 wp circuit element part u 矽 oxide film and adhesion layer i7b is etched with CF4/〇2 gas The etching is performed at a temperature that does not cause the support 18 to be peeled off, that is, it is preferably treated with 〜1 (eight) c. In terms of the size of the through hole 13, the square-side, or the diameter of the circle, or the long side of the rectangle It is 500 μηη or less, or 100 μηι or less, preferably 5 〇μηι or less, or even 1 〇μιη. 7. Second insulating film forming step Next, after removing the mask layer 12, inside the through hole π (that is, the second insulating film 14 is formed on the side wall of the through hole.) The structure shown in Fig. 1 is obtained. For example, if one side of the through hole 13 is 10 μηι, the second insulating film 108745. The thickness of doc 17 1325627 14 is formed to the extent of 100 to 200 nm. The second insulating film 14 is formed by plasma CVD. The conditions are: temperature: 4 〇〇 it, gas: TE〇s 680 mg/02 650 cc, pressure: 8.5 T〇rr, p〇wer: 8〇〇w, deposition rate: 100~200 nm/min. The reason for the plasma CVD method is that even if the film thickness is thin, the coverage is large and the film quality is good. If one side of the through hole 13 is 1 μm, the second insulating film 14 is thick to the extent of 2 to 3 μm. When the size of the through hole 13 is large, the surface area is increased, so that the parasitic capacitance is also increased by φ. Therefore, the film thickness is increased to reduce the parasitic capacitance. Further, the second insulating film can also be used. Formed by: applying a voltage to the surface of the substrate by using a ruthenium substrate as an electrode in a 15 〇 之 之 之 醯 溶液 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 析 析 析 析 析 析 析 析 析Electrodeposition is performed. 8. Copper filling step 8-1. Barrier layer and copper seed layer forming step Next, a barrier layer is formed on the surface of the substrate 10 and the inside of the through hole 13 from the surface side of the substrate ίο The copper seed layer 15 is obtained as shown in Fig. i(f). The barrier layer is composed of a TiN layer or the like, and the thickness is It is 5 to 15 〇 nm, but is preferably formed to be 1 〇 nm. The copper seed layer is thicker than the thickness of the monoatomic layer to 2 〇〇 nm, but preferably formed to be 1 〇〇 nm. It is formed by a CVD method or a flooding method, etc. If the cvd method is used, the layer is made to react with 贿((:2Η5)2)4 and bribe 3 or 仏, and grows at a temperature of 15 〇m. The copper seed layer 15 is formed by using Cu(hfac)(tmvs) as a raw material at a temperature of 15 °C. & 8-2. Copper plating step Next, using the copper seed layer 15, by electrolytic plating, fill the through hole Η 108745.doc -18· 1325627 = copper 16, as shown in Figure 1 (g) The structure. Since the second support 2 has an opening 2〇a in the portion of the through hole 13, the electric ore liquid flows smoothly through the through hole. Based on this, the air bubbles can be removed and caused by good efficiency: the diffusion of the seed should be inhibited, so that the generation of holes can be suppressed, and complete filling becomes possible; and the hydrogen bubbles are generated by electrical decomposition and adhered to The surface in the through hole 13 is the surface. For de-inflammation, in order to achieve complete filling and prevent jagged, it is preferable to plate copper to a thickness of 5 to i 到 on the surface of the substrate. Here, in the case of copper plating, t is performed by using CuS〇4·5H2〇 and H2S〇dC1• as an electro-recording liquid, and performing electrolytic electrowinning at a temperature of hunger. 8-3XMP Step Next, the copper 16 on the first insulating film 19 is removed by the CMP method, and only the copper 16 remains in the through hole 13, and a structure as shown in Fig. 1(h) is obtained. In the present embodiment, 'the copper 16 is formed on the first insulating film 19, and since the first insulating film 19 is generally flatter than the back surface of the substrate, the removal of the copper by the CMp method is easier. 9. Second support Body Removal Step Next, the second support 2 on the back surface of the semiconductor substrate 10 is removed to obtain a structure as shown in Fig. 1(i). The removal of the second support 2 is performed by: The substrate was immersed in a stripping solution of monoethanol and dimethylamine in a temperature of about 12 ° C to remove the adhesive layer 17b. By the above steps, a semiconductor device having a through electrode was fabricated. A cross-sectional view showing the manufacturing steps of the semiconductor device of the second embodiment. J08745.doc • 19· 丄 milk 627 Hereinafter, the present embodiment will be described with reference to Fig. 2. 1 · Supporting body mounting steps: first, the first and the first In the same manner as in the embodiment, the first support 18 is mounted on the surface side of the substrate ι to obtain a structure as shown in Fig. 2(a). 2. The substrate thinning step is followed by the same method as in the first embodiment. , 'Acquired' 2 (b) structure of the material. 4 3. First support removal step First, the first support is "detached from the substrate by the same method as the first embodiment. 4. The second support mounting step is followed by the first implementation In the same manner, the second support 21 is attached to the back side of the substrate 1. In the present embodiment, the through hole 13 is formed in the substrate in the subsequent step, and the first support 21 is regarded as Since the mask is used, it has the same opening 21a as the through hole 13 formed in the substrate 10. 5. First insulating film forming step Next, on the surface of the substrate 1 by the same method as the first embodiment The first insulating film 19 is formed on the side to obtain a structure as shown in FIG. 2(c). 6. The substrate through-hole forming step is followed by the first support 21 as a mask, by a reactive ion characterization method (RIE) or the like. The adhesive layer 17b, the substrate 1A, the circuit element portion, and the first insulating film 19 are sequentially etched, and a through hole 3 is formed in the substrate, and the structure shown in FIG. 2(d) is obtained. The conditions are the same as in the first embodiment, I08745.doc 1325627. Also, in this step, the second The holder 21 is also etched by the thickness of the substrate 1 (30 to 100 μm) + excessive etching amount to reduce the thickness, but if the thickness can be reduced in the subsequent step, this one The reduction does not pose a problem (if necessary, a support having a reduced thickness is considered) 7. The second insulating film forming step is then formed inside the through hole 3 by the same method as the first embodiment. The second insulating film 14 is obtained as shown in Fig. 2(e). 8. Copper filling step Next, a copper seed layer 15 is formed by a barrier layer in the same manner as in the first embodiment (Fig. 2(f)), copper 16 is filled in the through hole ^ by electrolytic plating (Fig. 2 (g)), and unnecessary copper is removed by CMP (Fig. 2 (h)). 9. First support But in the next step, the second support is removed by the same method as in the first embodiment, and the structure shown in FIG. 2(i) is obtained. In the manufacturing method of the semiconductor device of the present structure, the second The support body is a mask, and a through electrode pattern # can be formed on the substrate, thereby reducing the mask sheet and the photoresist Therefore, it is possible to achieve a shortened TAT (TurnAr〇undTime from order to delivery) and a reduction in cost. Third Embodiment FIG. 3 is a cross section of a semiconductor device and a manufacturing step of the third embodiment. FIG. 3 is a description of the present embodiment. The L first support mounting step firstly installs the first support on the surface 108745.doc 1325627 side of the substrate H) by the same method as the first embodiment. The body 18 is obtained as shown in Fig. 3 (a). The substrate thinning step is performed to perform thinning of the substrate 10 on the first support i 8 . Next, by the same method as in the first embodiment, the image is obtained as shown in Fig. 3. (b) The structure shown. 3. First Support Removal Step Next, the substrate is detached from the substrate by the same method as the first embodiment.
4. 第二支持體安裝步驟 接著,藉由與第一實施例同樣的方法,在基板1〇之背面 側安裝第二支持體22。 在本實施例中,為了在後步驟在基板1〇形成溝槽^,第 二支持體22係被當作遮罩使用’故其具有與形成之溝槽η 相同大小的開口部22a。 5. 第一絕緣膜形成步驟4. Second support mounting step Next, the second support 22 is attached to the back side of the substrate 1 by the same method as the first embodiment. In the present embodiment, in order to form the groove ^ in the substrate 1 in the subsequent step, the second support 22 is used as a mask so that it has the opening 22a of the same size as the groove n formed. 5. First insulating film forming step
接著,藉由與第一實施例同樣的方法,在基板1〇之表面 側形成第一絕緣膜19,獲得如圖3(c)所示之結構。 6. 基板貫通孔形成步驟 接著,藉由與第一實施例同樣的方法,在基板1〇形成貫 通孔13,獲得如圖3(d)所示之結構。 7. 溝槽形成步驟 接著,以第二支持體22為遮罩,藉由從背面側把基板進 行蝕刻,在基板背面形成溝槽23,獲得如圖3(e)所示之結 構。又,溝槽之形成亦可採取如下方式:使用具有比形成 之溝槽更大之開口部的第二支持體,以光微影技術,在基 108745.doc •22· 1325627 板^面形成光阻圖案,利用此光阻圖案為遮罩,形成溝槽。 8. 第二絕緣膜形成步驟 接著’藉由與第—實施例同樣的方法,在溝槽23及貫通 孔13内部形成第二絕緣膜14,獲得如圖耶所示之結構。 9. 銅填充步驟 接著’藉由與第-實施例同樣的方法,介以阻障,,形Then, by the same method as in the first embodiment, the first insulating film 19 is formed on the surface side of the substrate 1 to obtain a structure as shown in Fig. 3(c). 6. Substrate through hole forming step Next, by forming a through hole 13 in the substrate 1 by the same method as in the first embodiment, a structure as shown in Fig. 3(d) is obtained. 7. Groove forming step Next, the second support 22 is used as a mask, and the substrate is etched from the back side to form a trench 23 on the back surface of the substrate, thereby obtaining a structure as shown in Fig. 3(e). Further, the trench may be formed by using a second support having a larger opening than the formed trench to form light on the surface of the substrate by light lithography. The resist pattern is formed by using the photoresist pattern as a mask to form a trench. 8. Second insulating film forming step Next, the second insulating film 14 is formed inside the trench 23 and the through hole 13 by the same method as in the first embodiment, and the structure shown in Fig. 9 is obtained. 9. Copper filling step Next, by the same method as the first embodiment, the barrier is formed,
成鋼種晶層15(圖3(g)),藉由電解電鑛法,在貫通㈣内 f填充銅16(圖3(h)),藉由CMP法除去不要之銅(圖3⑴)。 背面側之CMP係以施加不使第二支持體22剝離程度之壓力 (譬如,20 kPa以下)來進行。 1〇·第一支持體卸下步驟 把第二支持體22 可同時形成溝槽 接著,藉由輿第—實施例同樣的方法 卸下’獲得如圖3(j)所示之結構。 根據本結構之半導體裝置之製造方法 配線與貫通電極。 第四實施例 、圖4係第四實施例之半導體裝置之製造步驟之剖面圖。 以下,參考圖4,針對本實施例作說明。 本貫施例係與第—實施例類似,但如下之點$同:在基 板10上所形成之電路元件部丨丨包含配線層Ua,且配線= "a係與形成貫通孔13之部位呈鄰接設置。配線層…通; 係與電路元件部1丨中之各種電路元件呈電性連接。 第支持體女裝步驟〜第一絕緣膜形成步驟 首先,藉由與第—實施例同樣的方法,進行從第—支持 108745.doc -23· 1325627 體安裝步驟到第一絕緣膜形成步驟,獲得如圓4(a)所示之 結構。如上所述,在本實施例中,電路元件部丨丨係包含配 線層11 a ^ 2.基板貫通孔形成步驟 接著,在基板10之表面側之第一絕緣臈19上塗佈光阻形 成光阻層,藉由將此層進行圖案化,形成具有開口部na 之遮罩層12。在本實施例中,如圖4(b)所示般,係使開口 部12a之大小比形成於基板1〇之貫通孔13更大。 接著,利用遮罩層12,藉由反應式離子蝕刻(rie)等方 法,把第一絕緣膜〗9、電路元件部u、基板1〇、及黏著層 17b依序進行蝕刻,在基板1〇形成貫通孔13,獲得如圖4(b) 所示之結構^述㈣係在使配線層lu成為阻止層的條 件下進行。基於此因’貫通孔13之大小係依照配線層m 之配置來決定;貫通孔13之大小係比遮罩層以開口部 12 a為小。 3. 第二絕緣膜形成步驟 /著,藉由與第一實施例同樣的方法,在貫通孔Η内部 形成第二絶緣膜14,獲得如圖4(c)所示之結構。 4. 銅填充步驟 接著’藉由與第一實施例同樣的方法,介以阻障層,形 成銅種晶層15(圖4⑷),藉由電解電鍍法,在貫通孔㈣ 部填充銅16(圖4(e)),藉由CMP法除去不要之銅(圖卿。 5. 第二支持體卸下步驟 接著,藉由與第一實施例同樣的方法,才巴第二支持體Η 108745.doc • 24 - 1325627 卸下,獲得如圖4(g)所示之結構。 根據本實施例,可簡易製作具有貫通電極的半導體褒 置,而該貫通電極係與配線層l】a呈電性連接者。 (在上述貫施例使用之支持體及在上述各實施例所獲得之 基板的形狀) 圖5係顯示元件晶圓(形成有貫通孔之基板)以與第二支 持體20、2〗的形狀。圖5(a)係顯示元件晶圓24;圖5(b)係 該元件之單片放大後之元件晶片24a,其具有貫通孔^之 圖案。圖5⑷係顯示第二支持體2()、21。圖5⑷係與元件 晶片24a對應之部份26的放大圖,其具有與貫通孔乃之圖 案對應的開口部27。>為第i實施例所使用之第二支持體 的情形,由於開口部27㈣為用於在基板上形成貫通孔乃 之遮罩,故使其大小與貫通孔25相同。第一實施例之第二 支持體之開口部27的大小係以比貫通孔25大數_為佳。 又,在第一實施例所使用之第二支持體之開口部27的圖案 方面亦可使用·如圖5⑷所示般,把貫通孔25作一體包 覆之開口部28般的圖案。再者,如形狀合乎以下條件:第 一支持體在保持晶圓支持功能的同時’不會妨礙電解電鍍 時之電鍍液的供應’則圖案亦可使用例示以外之圖案。 (使用在上述實施例所獲得之半導體裝置的疊層型 裝置) 圖6係;^層型半導體襄置,其係使用在實施例i〜4所獲得 Z、有貝通電極之半導體裝置者。圖6(b)為此裝置之底面 (a)為(b)中之1-1剖面圖。此裝置係在中介層3 1上具 108745.doc •25· 1325627 備.半導體裝置32,其係具有在實施例3所獲得之貫通電 極32a及溝槽配線(寬1〇〜2〇〇 μιη)321)者;及半導體裝置 33,其係具有在實施例丨、2或4所獲得之貫通電極者。 半導體裝置33係疊層有4個。中介層31在背面係具備凸塊 球(直徑30〜2〇〇 μΓη)35,在内部係具有中介層内貫通電極 (直徑 1 〇〜100 μιη)3 1 a。 各半導體裝置32、33之貫通電極32a、33a係互呈電性連 接;此外,溝槽配線32b、中介層内貫通電極31a及凸塊球 35亦互呈電性連接。因此,藉由形成圖6所示之結構,可 獲得如下疊層型半導體裝置:不使用配線用引線等,全部 各層之半導體裝置與中介層31背面之凸塊球呈電性連接。 【圖式簡單說明】 圖Ua)〜(i)係本發明之第一實施例之半導體裝置之製造 步驟之剖面圖。 圖2(a)〜(i)係本發明之第二實施例之半導體裝置之製造 步驟之剖面圖。 圖3(a)〜(j)係本發明之第三實施例之半導體裝置之製造 步驟之剖面圖。 圖4(a)〜(g)係本發明之第四實施例之半導體裝置之製造 步驟之剖面圖。 圖5(a)〜(e)係本發明實施例之元件晶圓與第二支持體的 形狀之平面圖。 圖6(a)、(b)係顯示使用從實施例1〜4所獲得之半導體裝 置的豐層型半導體裝置;(a)為剖面圖、(b)為底面圖。 108745.doc • 26- 1325627The steel seed layer 15 (Fig. 3(g)) is filled with copper 16 (Fig. 3(h)) in the through (4) by electrolytic electrowinning, and the unnecessary copper is removed by the CMP method (Fig. 3(1)). The CMP on the back side is performed by applying a pressure (for example, 20 kPa or less) to the extent that the second support 22 is not peeled off. 1〇·First Support Removal Step The second support 22 can be simultaneously formed with a groove. Next, the structure shown in Fig. 3(j) is obtained by the same method as in the first embodiment. A method of manufacturing a semiconductor device according to the present invention is a wiring and a through electrode. Fourth Embodiment FIG. 4 is a cross-sectional view showing a manufacturing step of a semiconductor device of a fourth embodiment. Hereinafter, the present embodiment will be described with reference to FIG. 4. The present embodiment is similar to the first embodiment, but the following points are the same: the circuit component portion formed on the substrate 10 includes the wiring layer Ua, and the wiring = "a system and the portion where the through hole 13 is formed Adjacent settings. The wiring layer is electrically connected to various circuit elements in the circuit component portion 1A. The first support film forming step to the first insulating film forming step is first performed by the same method as the first embodiment, from the first support 108745.doc -23· 1325627 body mounting step to the first insulating film forming step. The structure shown as circle 4 (a). As described above, in the present embodiment, the circuit element portion includes the wiring layer 11a. 2. The substrate through hole forming step. Next, the photoresist is formed on the first insulating layer 19 on the surface side of the substrate 10. The resist layer is patterned by this layer to form a mask layer 12 having an opening portion na. In the present embodiment, as shown in Fig. 4 (b), the size of the opening portion 12a is made larger than that of the through hole 13 formed in the substrate 1A. Next, the first insulating film 9, the circuit element portion u, the substrate 1A, and the adhesive layer 17b are sequentially etched by the reactive layer etching (RIE) or the like by the mask layer 12, on the substrate 1 The through hole 13 is formed, and the structure (4) shown in FIG. 4(b) is obtained under the condition that the wiring layer lu serves as a stopper layer. Based on this, the size of the through hole 13 is determined in accordance with the arrangement of the wiring layer m; the size of the through hole 13 is smaller than the opening of the mask layer 12a. 3. Second insulating film forming step The second insulating film 14 is formed inside the through via by the same method as the first embodiment, and a structure as shown in Fig. 4(c) is obtained. 4. Copper Filling Step Next, by the same method as the first embodiment, a copper seed layer 15 is formed by interposing a barrier layer (Fig. 4 (4)), and copper (16) is filled in the through hole (4) by electrolytic plating ( Fig. 4(e)), the unnecessary copper is removed by the CMP method (Fig. 5. The second support removal step is followed by the same method as the first embodiment, the second support body 108745. Doc • 24 - 1325627 is removed to obtain the structure shown in Fig. 4(g). According to the present embodiment, the semiconductor device having the through electrode can be easily fabricated, and the through electrode is electrically connected to the wiring layer (The shape of the substrate used in the above embodiments and the substrate obtained in each of the above embodiments) FIG. 5 shows the element wafer (substrate formed with the through holes) and the second support 20, 2 Figure 5 (a) shows the component wafer 24; Figure 5 (b) shows the monolithically enlarged component wafer 24a of the component, which has a pattern of through holes ^. Figure 5 (4) shows the second support 2(), 21. Fig. 5(4) is an enlarged view of a portion 26 corresponding to the element wafer 24a, which has a pattern pair with the through hole In the case of the second support used in the first embodiment, the opening portion 27 (four) is a mask for forming a through hole in the substrate, so that the size is the same as that of the through hole 25. The size of the opening portion 27 of the second support of the embodiment is preferably larger than the number of the through holes 25. Further, the pattern of the opening portion 27 of the second support used in the first embodiment can also be used. As shown in Fig. 5 (4), the through hole 25 is a pattern similar to the opening portion 28 which is integrally covered. Further, the shape satisfies the following conditions: the first support does not hinder the electrolysis while maintaining the wafer supporting function. The pattern of the plating solution at the time of plating can be used as a pattern other than the pattern. (The stacked type device using the semiconductor device obtained in the above embodiment) Fig. 6 is a layered semiconductor device used in The semiconductor device having the Z-beat electrode obtained in Embodiments i to 4 is shown in Figure 6(b). The bottom surface (a) of the device is the 1-1 cross-sectional view in (b). The device is in the interposer 3 1 is equipped with 108745.doc • 25· 1325627. The semiconductor device 32 has The through electrode 32a and the trench wiring (width 1 〇 to 2 〇〇 μη) 321 obtained in the third embodiment; and the semiconductor device 33 having the through electrode obtained in the embodiment 丨, 2 or 4. . Four semiconductor devices 33 are stacked. The interposer 31 is provided with a bump ball (diameter 30 to 2 〇〇 μΓη) 35 on the back side, and has a through electrode (diameter 1 〇 to 100 μm) 3 1 a in the interposer. The through electrodes 32a and 33a of the semiconductor devices 32 and 33 are electrically connected to each other, and the trench wiring 32b, the interposer through electrode 31a, and the bump ball 35 are electrically connected to each other. Therefore, by forming the structure shown in Fig. 6, a laminated semiconductor device in which all of the semiconductor devices of the respective layers and the bump balls on the back surface of the interposer 31 are electrically connected can be obtained without using wiring leads or the like. BRIEF DESCRIPTION OF THE DRAWINGS Figures Ua) to (i) are cross-sectional views showing a manufacturing step of a semiconductor device according to a first embodiment of the present invention. 2(a) to (i) are cross-sectional views showing a manufacturing step of a semiconductor device according to a second embodiment of the present invention. Fig. 3 (a) to (j) are cross-sectional views showing a manufacturing step of a semiconductor device according to a third embodiment of the present invention. 4(a) to 4(g) are cross-sectional views showing a manufacturing step of a semiconductor device according to a fourth embodiment of the present invention. 5(a) to 5(e) are plan views showing the shapes of the element wafer and the second support of the embodiment of the present invention. Fig. 6 (a) and (b) show a layered semiconductor device using the semiconductor devices obtained in the first to fourth embodiments; (a) is a cross-sectional view, and (b) is a bottom view. 108745.doc • 26- 1325627
圖7(a)〜⑴係先前技術 【主要元件符號說明】 之半導體裝置之製造步驟之剖面圖 10 ' 50 半導體基板 11、51 電路元件部 11a 金屬配線層 12、52 光阻 13、53 貫通孔 14 第二絕緣膜 15、55 種晶層 16 ' 56 導電體 17a、17b、57 黏著層 18 第一支持體 19 第一絕緣膜 20 ' 21 、 22 第二支持體 20a、21a、22a 第二支持體開口部 23 溝槽 24 元件晶圓 24a 元件晶片 25 元件晶圓之貫通孔 26 在支持體上與元件晶片對應的 份 27 ' 28 第二支持體之開口部 54 ' 59 絕緣骐 58 支持體 ο 部 108745.doc ·27·7(a) to (1) are cross-sectional views of a manufacturing process of a semiconductor device of the prior art [description of main components]. 10 '50 semiconductor substrate 11, 51 circuit element portion 11a metal wiring layer 12, 52 photoresist 13, 53 through hole 14 second insulating film 15, 55 seed layer 16' 56 conductor 17a, 17b, 57 adhesive layer 18 first support 19 first insulating film 20' 21, 22 second support 20a, 21a, 22a second support Body opening portion 23 groove 24 element wafer 24a element wafer 25 element wafer through hole 26 portion 27' 28 corresponding to the element wafer on the support body. opening portion 54' of the second support body. Department 108745.doc ·27·
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005040556A JP3880602B2 (en) | 2005-02-17 | 2005-02-17 | Semiconductor device manufacturing method, semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| TW200701428A TW200701428A (en) | 2007-01-01 |
| TWI325627B true TWI325627B (en) | 2010-06-01 |
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| TW095105417A TW200701428A (en) | 2005-02-17 | 2006-02-17 | Semiconductor device manufacturing method and semiconductor device |
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| JP (1) | JP3880602B2 (en) |
| CN (1) | CN101120438B (en) |
| TW (1) | TW200701428A (en) |
| WO (1) | WO2006087957A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5478009B2 (en) | 2007-11-09 | 2014-04-23 | 株式会社フジクラ | Manufacturing method of semiconductor package |
| JP5138395B2 (en) | 2008-01-22 | 2013-02-06 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
| JP5142862B2 (en) * | 2008-07-10 | 2013-02-13 | 新光電気工業株式会社 | Wiring board manufacturing method |
| US8859424B2 (en) | 2009-08-14 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor wafer carrier and method of manufacturing |
| US20110042803A1 (en) * | 2009-08-24 | 2011-02-24 | Chen-Fu Chu | Method For Fabricating A Through Interconnect On A Semiconductor Substrate |
| KR101604607B1 (en) * | 2009-10-26 | 2016-03-18 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the semiconductor device |
| CN102120561B (en) * | 2010-01-08 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming wafer through hole |
| KR101185690B1 (en) | 2011-08-02 | 2012-09-24 | 성균관대학교산학협력단 | Method of processing a substrate |
| CN103258790A (en) * | 2013-04-27 | 2013-08-21 | 江阴长电先进封装有限公司 | Method for revealing inner metal of silicon through holes |
| JP5827277B2 (en) * | 2013-08-02 | 2015-12-02 | 株式会社岡本工作機械製作所 | Manufacturing method of semiconductor device |
| CN103441150B (en) * | 2013-08-09 | 2016-03-02 | 如皋市晟太电子有限公司 | A kind of applicable constant current tube simplifying encapsulation |
| JP6458429B2 (en) * | 2014-09-30 | 2019-01-30 | 大日本印刷株式会社 | Conductive material filled through electrode substrate and method for manufacturing the same |
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| JP2004319821A (en) * | 2003-04-17 | 2004-11-11 | Sharp Corp | Method for manufacturing semiconductor device |
| JP2004327910A (en) * | 2003-04-28 | 2004-11-18 | Sharp Corp | Semiconductor device and method of manufacturing the same |
| JP2005026405A (en) * | 2003-07-01 | 2005-01-27 | Sharp Corp | Through electrode structure and manufacturing method thereof, semiconductor chip and multichip semiconductor device |
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2005
- 2005-02-17 JP JP2005040556A patent/JP3880602B2/en not_active Expired - Lifetime
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| WO2006087957A1 (en) | 2006-08-24 |
| JP3880602B2 (en) | 2007-02-14 |
| TW200701428A (en) | 2007-01-01 |
| CN101120438B (en) | 2010-05-26 |
| JP2006228947A (en) | 2006-08-31 |
| CN101120438A (en) | 2008-02-06 |
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