TWI325621B - Chip assembly and chip package - Google Patents

Description

VIT06-0189 22506twf.doc/n IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a wafer assembly and a chip package. [Prior Art] In the semiconductor industry, the production of integrated circuits (1C) can be mainly divided into three stages: design of integrated circuits, fabrication of integrated circuits, and sealing of integrated circuits. In the fabrication of an integrated circuit, a chip is completed by a process of fabricating, forming an integrated circuit, and wafer sawing. The wafer has an active surface, which generally refers to the surface of the crystal having an active dement. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further provided with a plurality of bonding pads 'so that the wafers finally formed by the wafer can be electrically connected to each other via the pads. Carrier. The carrier is, for example, a leadframe or a drcuit board, which is configured by a wire-bonding technology nip-chip bonding technology and electrically connected to the carrier. Therefore, "these solder bumps can be electrically connected to a plurality of contacts carrying H to constitute -; the agricultural body. In the case of flip chip bonding technology, usually after forming these solder bumps on the active surface of the wafer' Will be made on each fat - conductive bump bump 'to act as an intermediary for the wafer to be electrically connected to the carrier. Since these conductive bumps are usually arranged in an area array on the active side of the wafer, make 1325621 22506twf.doc / n

VlT〇6-〇ig9 has a flip chip bonding technology suitable for chip packages with high junction count and high junction density, such as flip chip/ball grid array packages (flips) that have been commonly used in the semiconductor packaging industry. Chip/ball grid array package ). In addition, in the wire bonding technique, the flip-chip bonding technique can improve the electrical performance of the chip package because these conductive bumps provide a shorter routing path between the wafer and the carrier. When the wafer of the chip package of S is switched between high-speed start-up and turnoff, the current loop inside the chip generates switching noise, and is disposed in the chip package. The capacitor (decoupling capacit〇r) will stabilize the power supply and filter the noise in a timely manner. In conventional chip packages, the decoupling capacitors are placed in the carrier or on the carrier according to the requirements of the device. However, these configurations = the position of the coupling capacitor have their disadvantages. In other words, the 55-capacitor capacitor placed in the money device is not easy to manufacture and has a high manufacturing cost. In addition, the decoupling capacitors disposed on the carrier may have a larger capacitance value, but the decoupling capacitors disposed on the carrier are far from the wafer and cannot achieve the desired effect. SUMMARY OF THE INVENTION The present invention is directed to a wafer assembly and a wafer sealing body, which are more electrically effective. 8. The present invention provides a wafer assembly comprising a wafer and at least one passive element. The wafer includes a substrate (su^tra=), a circuit unit, a plurality of first pads, and a plurality of conductive vias. The substrate has a first surface and a second surface opposite to each other. The line unit is disposed on the first surface, and the plurality of pads 6 VIT06-0189 22506twf.doc/n are disposed on the second surface h. The conductive vias pass through the == these first pads and the line unit. In addition, the passive component is disposed on the second surface and electrically connected to the first pads. The chip package includes a carrier and a crystal body disposed on the carrier and electrically connected to the carrier: the 晶片 wafer and the at least one passive component. The wafer includes two bases: a line unit, a plurality of first pads, and a plurality of conductive vias. The substrate has a first surface and a second surface opposite each other, wherein the first surface faces the carrier. The line units are disposed on the first surface and on the first surfaces. These conductive vias extend through the substrate, wherein the two vias electrically connect the solder fillet to the wiring unit. In addition, the passive member is disposed on the second surface and electrically connected to the first solder pads. In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following detailed description will be made in accordance with the preferred embodiments. [Embodiment] Please refer to Fig. 1, which is a cross-sectional view showing a wafer package according to a first embodiment of the present invention. The chip package 2G0 of the first embodiment includes a carrier 210 and a wafer assembly 22A. The wafer assembly 22 is disposed on the carrier 210 and electrically connected to the carrier 21A, and the wafer assembly 22 includes a wafer 222 and at least one passive component 224 (only one of which is schematically shown in FIG. 1). The wafer 222 includes a substrate 222a, a line unit 22, a plurality of pads 222c and a plurality of conductive vias 222d. The substrate 222a has two surfaces Sb opposite to each other, wherein the surface S1 of the substrate 222a faces the carrier 1325621 VIT06-0189 22506twf.doc/n 210. The line unit 222b is disposed on the surface SI of the substrate 222a. These pads 222c are disposed on the surface S2 of the substrate 222a (i.e., the back surface of the wafer 222). The conductive vias 222d extend through the substrate 222a, wherein the conductive vias 222d electrically connect the pads 222c to the line cells 22%. In addition, the passive element 224 is disposed on the surface S2 of the substrate 222a and electrically connected to the pads 222c.

Since the passive component 224 is disposed on the surface S2 of the substrate 222a of the wafer 222, the passive component 224 of the chip package 2 is spaced from the wafer by a conventional method of disposing the passive component on the carrier. near. Therefore, when the wafer 222 is in operation, the passive component 224 can perform optimally, so that the electrical performance of the chip package 2 (8) is in the embodiment. The passive component 224 can be a capacitor, which includes two 2 = 4a and - Dielectric layer 224b. These conductive layers 224a can be electrically connected by a surface (surface _nting techn〇1〇gy)

Μ 5 and the dielectric layer 224b is disposed on the conductive layers 224a lav: ) ϋ, & some of the conductive layers can be ground layer (ground T only early: 222b includes at least - transistor 1 〇〇 scales not - a) with multiple lines moving, just, 106. =? 〇 =, and then electrically connected to the carrier = ^ '_ unit 222 one including other 峨 8 VIT06-0189 22506twf.doc / n with other integrated circuits ( The first embodiment is for illustrative purposes only and is not limiting of the invention. In detail, the power supply line 104 in the line unit 222b of the wafer 222 of the first embodiment may pass through a portion of the conductive via 222d (also That is, the power conductive via) and a portion of the pad 222c (ie, the power pad) are electrically connected to one of the conductive layers 224a (ie, the power layer) of the passive component 224. Further, in the circuit unit 222b of the wafer 222 The grounding line 1〇6 can be electrically connected to the other of the passive component 224 via another portion of the conductive via 222d (ie, the ground conductive via) and another portion of the solder bump 222c (ie, the ground pad). Conductive layer 224a (ie, ground layer). When the chip package 20 of the first embodiment When the wafer 222 of 0 is switched between high-speed start-up and turn-off, the current flowing in the line unit 222b of the wafer 222 causes switching noise. The passive element 224 disposed on the surface S2 of the substrate 222a can function as a decoupling capacitor. The power supply and the transitional high frequency noise are stabilized in a timely manner. Compared with the prior art, since the passive component 224 is close to the wafer 222, the passive component 224, such as a capacitor, has a better effect of stabilizing the power supply and transitioning the south frequency noise. It should be noted that, in the first embodiment, the carrier 21 can be a circuit board, and the wafer assembly 220 further includes a plurality of conductive bumps 226. The conductive bumps 226 are disposed on a surface S3 of the line unit 222b. (ie, the active surface of the wafer 222) and the carrier 21A, wherein the surface S3 is the surface of the line unit 222b away from the substrate 222a. The wafer 222 is electrically connected to the carrier 210 by the conductive bumps 226. In other words, the wafer 222 of the first embodiment is electrically connected to the carrier by flip chip bonding technology. 1325621 VIT06-0189 22506twf.doc/n Please refer to FIG. 2, which illustrates a second embodiment of the present invention. crystal A schematic diagram of a cross-section of the package. The main difference between the chip package 3 of the second embodiment and the chip package 200 of the first embodiment is the appearance and arrangement of the passive component 324. In the second embodiment The passive component 324 includes two conductive layers 324a, a dielectric layer 324b, and a plurality of conductive through holes 324c. The dielectric layer 324b is disposed on the conductive layer 324b.

Between the conductive layers 324a, the conductive vias 324c extend through the dielectric layer 324b. In addition, with respect to the relative position illustrated in FIG. 2, the conductive layer 324a under the dielectric layer has a plurality of pads 324d and a conductive portion 324e, and the pads 324d and the conductive portions 324e are electrically connected. insulation. The conductive vias 324c are electrically connected to the conductive layer 324a over the dielectric layer 32A and the pads 324d. In addition, the pads 324d are electrically connected to a portion of the pads 322c, and the conductive portions 324e are electrically connected to the pads 322c of the other portion.

In detail, the power line 104 in the line unit 32 of the wafer 322 of the second embodiment can pass through a portion of the conductive via 322d (ie, the power conductive via), a portion of the pad 322C (ie, the power pad), The pad 32 is electrically connected to the conductive layer 324 & (ie, the power layer) of the passive component 324 on the layer, such as the conductive via 324c'. In addition, the ground line 1〇6 of the circuit unit 322b of the wafer 322 can be electrically connected to the passive component/electrical portion via another portion of the conductive via (ie, the grounded conductive via) and the ground soldering node. That is, the ground layer). The conductive portion of the electrical layer (10) above the dielectric layer 324b and the dielectric layer under the dielectric layer VIT06-0189 22506twfdoc/n 3 can be respectively described as the ground layer and the power supply layer according to the design requirements, according to the above embodiment. It is intended to be illustrative only and not limiting.

It should be noted that since the two conductive layers X of the passive component may be parallel to the surface S2 of the substrate 322a (ie, the back surface of the wafer 322 is disposed on the wafer 322, the area of the two conductive layers is large. Therefore, when the wafer When the 322 is in operation, the passive component 324 can also serve as a thermal sheet to transfer the heat generated by the wafer 322 to the external environment. In summary, the wafer assembly and the chip package of the present invention have the following advantages: /, Since the passive component of the present invention is disposed on the crystal to compare the passive component to the carrier in the prior art, the passive component of the inventive crystal assembly is closer to the wafer. Therefore, when the wafer is in operation 'Passive components can achieve the best performance, so that the electrical performance of the wafer package and the chip package to which it is applied is improved. 2. Since the conductive layers of the passive component of the present invention can be arranged in a flat back manner On the wafer, the area of these conductive layers is β 乂 Therefore, when the wafer is in operation, the passive component can also act as a heat sink to transfer the heat generated by the wafer to the outer ring. A.,,, 3. Since the wafer assembly and the wafer package of the present invention can be placed on the surface of the wafer, the manufacturing method of the body and the wafer body can be compared with the existing method. Process Integration - Although the present invention has been disclosed above, it is not intended to limit the present invention, and any person having ordinary skill in the art can be deviated from the spirit and scope of the present invention, and some modifications and necessities can be made. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims. A section of the wafer package of the first embodiment is a wafer seal of the second embodiment. Carcass W section

[Description of main component symbols] 100: transistor 102, 104, 106: wiring 200, 300 · chip package 210 : carrier

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view of the present invention. Figure 2 is a schematic view of the invention. 220: wafer assembly 222, 322: wafer 222a, 322a: substrate 222b, 322b: wiring unit 222c, 322c, 324d: solder 222d, 322d: conductive via 224, 324: passive component 224a, 324a: conductive layer 224b, 324b: dielectric layer 226: conductive bump 324c: conductive through hole 324e: conductive portion 8 32, 82, 83: surface 12

Claims (1)

The wafer includes the patent application scope: a wafer assembly body including a 丨, "---一_ _ 1 ---------J surface,: a first surface and a first surface opposite to each other The second surface is in the middle of the wafer; the surface of the second surface is the back surface of the wafer; 鬌 = the line is disposed on the first surface; is placed on the second surface; and the electrical connection is such that the 'before the substrate' Wherein the conductive vias are at least - and are soldered to the circuit unit; and, [welding: = on the second surface and electrically connected to the passive component comprises: a first conductive layer; The 'having a plurality of second pads and a conductive portion, the first and second rates are electrically insulated from the conductive portion; and the / electrical layer is disposed on the conductive layer of the first conductive layer and the second conductive layer The electric layer is electrically connected to the first, and the (four)-= pad and the electrical connection is divided into the first ones. The electrical assembly is electrically connected to the wafer assembly of the other item... The wire and the plurality of wires, and the transistor = 3. The wafer assembly according to claim 1, which is 13 99-1-26 The component of the wafer assembly according to Item 1, wherein the 5曰1 is a layer and the conductive portion is a power layer. The wafer assembly according to the item, wherein the "electric layer, the source layer, and the conductive portion is a ground layer." The medium assembly described in the first aspect of the patent scope includes three tables. The bumper 'is disposed on the chip unit away from the substrate, and includes: a carrier; and a carrier, a chip assembly is disposed on the carrier, and is connected to the carrier The wafer assembly includes: a wafer comprising: a substrate having a first surface and a first table opposite to each other, wherein the first surface faces the carrier, the first surface being the wafer a back unit; a circuit unit disposed on the first surface; a solid first layer disposed on the second surface; and an electrical channel 'through the substrate, wherein the plurality of conductive electrodes are connected to the first solder a pad and the line unit; and a connection to the second piece, disposed on the second surface The passive component comprises: - a first conductive layer; a second conductive layer 'having a plurality of second pads and a conductive 14 99-1-26 second pad and the conductive portion Between the electrical layers; and a 'clade layer' disposed on the first conductive layer and the second conductive via, through the dielectric and electrically connected to the portion, the portion is connected to the portion of the first solder塾 且 该 该 如 如 如 如 如 如 如 如 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路The transistor package according to the seventh aspect of the present invention, wherein the transistor is a ground layer, and the conductive portion is a power supply layer. a lining-electroconductive enclosure according to item 7, wherein s is a power supply layer, and the conductive portion is a ground layer. The wafer die of the seventh aspect of the present invention, wherein the substrate is away from the substrate == bump, which is disposed in the circuit unit: by the conductive bumps:; ==, wherein the crystal substrate is 7 (4) (4) Body, its % 15