TWI325135B - A nand non-volatile two-bit memory - Google Patents

Description

1325135 [Prior Art] Although there is no power supply for a long period of time, the non-volatile semiconductor memory device can retain the stored data without loss. According to this characteristic, non-volatile memory devices can generally be divided into two sizes: ^ (read only memory), PROM (programmable read only memory), EPR 〇 M (can be erased programmable can only read Memory), EEPROM (electrically erasable programmable read-only memory), and flash memory. Because of its ability to be quickly erased/programmed, EEPROM flash memory is widely used in devices that store large amounts of data, such as memory cards, PDAs (personal digital assistants), and Mp3 players. The EEPROM flash suffix can be roughly divided into NAND (reverse) type and NOR (reverse) type. NAND flash memory has many memory cells that share source and drain with adjacent cells and are connected in series. N〇R flash memory has many parallel memory cells, and each has its own Its source and bungee. Because of this difference, NAND flash memory will have a higher cell density than NOR flash memory. U.S. Patent No. 6,885,586 describes a self-aligned split gate NAND flash memory in which each memory cell cell contains control gates and floating gates that are stacked on each other and self-aligned with each other, and In addition to the split gate between the stacked gates. The floating gate is made of a conductive material such as polycrystalline germanium or amorphous germanium with rounded sides to improve the erase and stylization effects. In the erasing operation, the electric field caused by the circular curvature of the floating gate

- And: = Cuibian borrowed Lang, Fowler-Nuo wears the effect by idle. In the stylized operation, the hot electron injection or the (Fowler-Nordham) wear-through effect is used by the channel area to be injected by electrons, floating inside. - Memory cell can be stored; Second: Under the need to store large amounts of data and reduce costs, a memory cell capable of storing a 70-bay machine and increasing the density of data storage has been developed. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for the production of a large amount of data and a cost reduction. In order to achieve the above object, the technology of the present invention is implemented as follows: 1. A non-volatile two-dimensional memory cell comprising a cell stack and a two-selective stack disposed on an active region of the substrate, stacked on each side They are respectively disposed on the side of the unit cell stack and have a side wall disposed between the crystal age stack and each of the selection stacks. The cell stack comprises four parts: a first dielectric layer disposed above the substrate; a charge layer disposed above the first dielectric layer to hold the charge in a portion to store information; a second dielectric layer over the charge accumulation layer; and a control gate disposed above the second dielectric layer. The selection stack comprises two parts: a third dielectric layer disposed above the substrate; and a selection gate disposed above the third dielectric layer to convert a lower channel region into a source of the memory cell / Nothing function. The above and other objects, features and advantages of the present invention will become more apparent. [Embodiment] - a kind of anti-scale ship two-dimensional memory unit cell, which contains a charge layer of brittle _, one side of charge tiring one: the information of Liyuan 'so' - a memory crystal The cell can store two core cells including - control gates and charge accumulation - and the second cell has two selective stacks with selective gates.任—Selecting the stacking I configuration ^ day cell stacking - side and stacking the cell and stacking ^ 'Selecting the stack can select the gate supply voltage higher than its threshold voltage to convert the lower channel region into the memory cell The source and the extreme function of the dragon can select the gate to control the source side in the stylized operation. ^ As shown in Fig. 1 - the type of anti-non-volatile package = substrate (10) - active area 12. 1 bis 145 'each lion stack (10), 145 are respectively arranged in the cell cell stack 130 and each of the selection stacks 140, (4) between the layers 134' is a second dielectric 8 that can hold the charge above a stack m In the charge of the tired side, control fine 38. The charge accumulation fine-side can respectively reserve the charge accumulation of the second dielectric layer 136 under the first dielectric layer 132. Therefore, one and the bit 1). Memory cells can store two bits of information (bit 0 1325135 each of the selected stacks 140, 145 includes a third dielectric layer 160, 165 disposed above the substrate no; and a third configuration The select gates 142, 147 above the dielectric layers 160, 165 convert a lower channel region into a source/drain function of the memory cell. When the gate 142, 147 is selected to supply a voltage higher than its threshold voltage At the same time, the channel region under the selection gates 142, 147 can be converted into the source/drain function of the memory cell according to the portion of the charge accumulation layer 134 that is being programmed.

When the right portion (bit 〇) of the charge accumulation layer 134 is programmed, the conversion channel region on the lower right side of the right selection stack 145 will have the source function of the memory cell. When the left portion (bit 丨) of the charge accumulation layer 134 is programmed, the conversion channel region below the left selection stack 140 will have the source function of the memory cell. By controlling the supply voltage, the gates 142, 147 are selected to control the injection of electrons from the source side to the charge accumulating layer 134 in the source side during the stylization operation.

In one embodiment, the substrate 110 is formed of a semiconductor material such as germanium. In the substrate 110, the active region 120 is formed by a p-well layer; above the active region 12', the thickness is 3G-5G. The first dielectric layer 132 is a dioxo layer, which can be lifted and insulated. Above the first dielectric layer 132, the thickness is "the charge accumulation layer 134 of the Ο is - the nitrogen layer" In the process of staging the memory cell, a function of retaining charge is provided; above the charge accumulating layer 134, a second dielectric layer 136 having a thickness of 2 〇·4 〇 is a dioxotomy layer; Above the two dielectric layers (9), a control gate 138 having a thickness of 1000 angstroms is formed by polycrystalline zebra; the 曰-selected closed-poles 142, 147 are slightly formed by polycrystals and are adjacent to the control gate 138. The sidewalls (9) and 155 between the cell stack 130 and the selection stack 14〇, 145 are included in the vicinity of the 胞 cell stack 130 and are made of nitrite “ 斤 ” ” ” ” ” ” ” The slave layer; while the side 8 1325135 walls 150, 155 have a thickness of about 180 angstroms. The third dielectric layer 160, 165 between the selected gates 142, 147 and the substrate 110 is a layer of dioxide dioxide having a thickness of about 140 angstroms. Fig. 2 discloses an inverted and non-volatile two-dimensional memory cell array in which a plurality of memory cells are arranged in columns and rows, and in the same row, the memory cells are connected in series to form a cell string. The electro-optic system is selected to be connected to each end of the unit cell string, and the complex number 6 of the even-numbered rows forms a ~~" even-numbered cell string, and the odd-numbered memory cells in the odd-numbered rows form an odd-numbered cell string. The two selected electro-optic systems respectively connected to one end of the even-numbered cell string are even-numbered string-selecting transistors, and the two selected electro-crystalline systems respectively connected to one end of the odd-numbered cell strings are odd-numbered string selecting transistors. Figure 3A is a two-serial circuit diagram formed by an even-numbered cell string, a two-even-string selection transistor, an odd-numbered cell string, and an odd-numbered string selection transistor, as shown in the figure: the first even-number string selects electricity The crystal and the first odd-numbered string selection transistor system are disposed at one end (upper end) of the two-string circuit to be connected with the even-numbered bit line; the second even-numbered string selection transistor and the second odd-numbered string selection transistor system are disposed in the two-string circuit One end (lower end) to connect with odd bit lines. In Fig. 2, the array has M memory cell strings and is divided into ()^+1)/2 cell string pairs, each of which has an even cell string and an odd cell string. Each cell string pair also includes a cell stack and a selective stack connection, the _ _ face cell, the cap lion stack is disposed on the two sides of the cell stack, and is stacked on the cell Select a side wall between the stacks. Because such an arrangement's arrangement of stacks between two cell stacks will be adjacent to each other, and the second is 'consistent with the unit cell. For the paste, if the illusion is shown, the choice of the heap is 1 for the secret (10) and the new (four) ;; in terms of frequency, the memory cell 0 contains the stack 〇, the cell stack 〇 and the selection stack Memory

9 1325135

The bulk cell 1 includes a selection stack 1, a cell stack 1 and a selection stack 2. The bit line pair including the even bit line and the odd bit line is connected as a one or two string circuit. The even bit line is connected to one end of the two string circuits via the first even string selection transistor and the first odd string selection transistor, and the odd bit line selects the transistor via the second even string selection transistor and the second odd string selection The crystal is connected to the other end of the two strings of circuits. For example, the bit line O (BLO) is connected to the upper end of the cell string 0 and the upper end of the cell string 1 via the first even string selection transistor and the first odd string selection transistor, respectively; bit line 1 ( BL 1) is connected to the lower end of the unit cell string and the lower end of the cell string 1 via the second even string selection transistor and the second odd string selection transistor, respectively. In the stylized process, the bit line 〇 and the bit line 1 provide voltage to the cell string 0 and the cell string 1 ' However, there is only one string in the cell string and the cell string 1 by the even string. The transistor or odd string is selected to select the transistor and is selected for programming. Therefore, the array can be divided into two pages, page 0 formed by even cell strings (strings 0, 2..., M-1) and formed by odd cells _ (chain 丨, 3, M) Page 1.

The sub-line is connected to the control gate of each cell string and the selection gate, and the selection line 0 (SEL 0) is connected to the even-numbered series transistor of the even-numbered cell string. When $line 0 (SEL G) is actuated, the 'even string selection transistor will be turned on, and the page 0 formed by the two-digit cell string will be selected until select line 1 (SEL 1) is connected to odd 1) When moving, the odd-numbered string of odd-numbered cell strings selects the transistor, and when the select=selects the electrical slit, it is turned on, and the odd-numbered cell 'is formedΓ;:: is: 3B is another electric mode with four depletion modes A two-series circuit diagram of a two-dimensional memory, the crystal is formed to form a reverse and a non-volatile as shown in the figure: the first empty hair 10 杈-type electric crystal system is vertically arranged in the first even-numbered string selection transistor and the selection gate And horizontally disposed on the same column line as the first odd-numbered string selection transistor; the first depletion mode electro-optic system is vertically disposed between the second even-numbered string selection transistor and the bit line 1, and is horizontally disposed The two odd-numbered φ select transistors are on the same column line, and the first two-dose mode electro-crystal system is vertically disposed between the first odd-numbered string selection transistor and the bit line 0, and is horizontally disposed in the same manner as the first even-numbered string selection transistor On the line; the fourth empty mode transistor is arranged in the straight line The gate N+1 and the second odd string select between the transistors 'and are horizontally arranged on the second and even string selection transistors. The process of making a memory cell to the memory cell is 'but it is permanently conductive, so it basically does not affect the memory. Section 4® is a schematic diagram that reveals the supply voltages, sub-lines, control gates, select gates, and other supply voltages in the erase, program, and read memory cell processes. During the erasing process, according to the F_N wear-through effect, the voltage difference between the control layer and the substrate P layer will discharge electrons from the charge accumulation layer to the p-well and establish an electric field. The word line connected to the control gate will be set to a voltage such as 0V' and the P-well layer of the substrate will be set to a voltage as high as 12V; the even-numbered string Ba body and the odd-numbered (four)-selective transistor will be set extremely For the voltage of 〇V==, the bribe bit line and the memory cell do not conduct each other. In order to avoid damage to the gate oxide layer caused by the voltage burst =, the mosquito will be reduced by about w to reduce the voltage difference between the well and the substrate P. In another embodiment, is the connection fixed? The 70-year-old slave is about _5Vi, and the p-well layer is set to the voltage difference of ^, and the optional idler system can be set to read to avoid damage to the gate oxide layer. The side of the lower part will be :::_ below; the pass = the wire is left in the electrical form · the electron is generated when the _ is generated _ is the source side. For the cattle column, the bit 〇 of the memory cell in the stylized cell string 0, the gate of the even-numbered transistor will be set to a high surface such as 7¥, and the gate of the odd-numbered series will be selected. Will be set to a low light such as 0V, in order to select the cell cascade ^ character line 1 of the control pole 1 will be set to about 9V to generate a vertical electric field; select gate 1 will be set to about 1.5V, High enough to turn on the channel area below the selected gate and low enough to avoid large current flows; all other control gates and select gates are set to approximately 7V. For the memory cell cell, the stylized data "0" 'the bit line connected to the source is set to about 〇v, and the bit line 1 connected to the drain is set to about 4.5V. In order to generate a lateral electric field, hot electrons from the source are injected into the upper portion of the charge accumulating layer of the memory cell 1. To program bit 1 of memory cell 1 in cell string 0, word line 1 connected to control pin 1 is set to about 9V to generate a vertical electric field; select gate 2 is set to about 1.5V. To control the flow of current. For the memory cell 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆In order to generate a lateral electric field, hot electrons from the source are injected into the lower portion of the charge accumulating layer of the memory cell 1. In the process of reading, in order to read the bit 0 stored in the memory cell 1 in the cell string 0, the gate of the even string selection transistor is set to about 4.5V, and the odd series is selected as 1325135: (4) _ will be set to about GV to select the cell string ο. The word line 1 connected to the control gate 1 is set to be about 1.5V, and the well layer of the substrate is set to about OV. The bit line 〇 is set to OV, connected to the source of the memory cell, and the bit line is set to 1.W, which is connected to the memory cell. If the charge is stored on the upper side of the memory cell 1 (bit 0), the threshold voltage of the control gate 1 will change, and the current flowing from the corresponding channel region to the sense amplifier will be affected. Therefore, it is not recognized how much charge is stored on the side of the charge accumulating layer, and is detected in the current flowing through the sensing diode.帛5 AdL H reveals a schematic diagram of a reverse-non-volatile two-dimensional memory array process, as shown in the figure: in Figure 5A, the single crystal substrate 5〇2 has a p-well active layer 504 An oxide layer 506 having a thickness of 30-50 angstroms and being used as the first dielectric layer is thermally grown over the substrate 502, and the oxide layer 5〇6 has an inter-electrode oxide layer or a pass-through oxide layer; - a thickness of 6 is applied as a charge accumulation ^ nitride layer 508 is deposited on the oxide layer 506 by LPVCD (low pressure chemical vapor deposition), a thickness of 20-40 angstroms and is regarded as a second dielectric The layer of the SiO2 layer 510 is deposited over the 氮化 夕 layer 5 〇 8; a polycrystalline 矽 layer 512 having a thickness of about Å and being used as a control gate is deposited over the yttrium oxide layer 51 , and polycrystalline 矽Layer 512 can be doped with N-type or P-type ions, while N-type polycrystalline germanium is typically doped with phosphorus; - TiO2 layer 514 having a thickness of about 3 G() is deposited over polycrystalline layer 512 To reduce the impedance of the word line connection; a nitride layer 516 with a thickness of about 2 angstroms is deposited over the Shixi chemical layer 514. In the subsequent surname process, the nitride layer 516 can provide a function as a protective cover to prevent the polycrystalline dream layer 512 in the control gate region from being erased by the surname. In Fig. 5B, a photoresist layer 518 is formed over the nitride layer 516, and the photoresist layer 518 is then patterned using conventional lithography techniques to define the control gate layer and the charge accumulation layer. The exposed portion of the nitride layer 516 is then etched away by dry etching, and the remaining photoresist layer is subsequently removed. In Fig. 5C, the remaining portion of the tantalum nitride layer 516 provides a function as a protective cover for the control of the side pole phase and the t-charge accumulation Weihe layer 514, polycrystalline by the anisotropic The stone layer 512, the SiO2 layer 51 and the nitriding layer are etched, and the cells 520-530 having the self-aligned (four) pole layer and the charge accumulating layer are formed. In the 5D®, a thickness of about 30 angstroms including the bottom portion 542, the side portion H, and the portion 546 of the nitrogen-cutting G-series LPCVD @ _ between the crystal and the side and top of the unit cell stack Above the portion of the oxide layer 5〇6—having a thickness of about 150 angstroms and including the bottom portion 552, the side portion 554, and the top portion of the current 55 〇m> JM LPCVD ^ 540J, : Figure 2: The lower layer of the oxidized crystal J, the resistance:, the dioxane as 'the selection gate between the cell stack can be made wider and more comparable. In the 5G diagram, the polysilicon is followed by the first: the oxidation of the outside of the cell stack Layer 506 will be engraved by the surname 'Oxygen II 506, = emulsified, 560 will be thermally oxidized to the cell stack nitriding _6 bis to 14 layers 562 will be etched back to a little below the nitrite The height of the top of layer 516; in the first map, CMP (Chemical Mechanical Polishing) can be used to grind down to tungsten telluride layer 514 and provide a flat top surface. Therefore, the remaining portion of the tantalum nitride layer 5丨6 and the specific portion of the polysilicon layer 562 are removed. In Fig. 51, a photoresist layer 564 is formed on the top surface and patterned to expose an area that is a depletion mode transistor. For example, N-type ions are implanted into the channel region under the gate of the depletion mode transistor to ensure permanent conduction of the depletion mode transistor, and the remaining photoresist layer 564 will subsequently be removed. In Figure 5j, the oxide layer 56〇 and the even-numbered string selection transistor and the odd-numbered string selection transistor which are originally located above the depletion mode transistor are removed by the side; a new oxidation of a thickness of about fine Shi Xi layer 566 will heat up on the top surface and become a depletion mode transistor, even

The string selects the transistor and the gate oxide layer of the odd string select transistor. In Figure 5K, a polycrystalline layer of thickness - about 1000 angstroms will be deposited and patterned to become the gate of the deficient mode transistor 568, 570, the even string selection transistor 572, and the odd string selection transistor 574. . In Fig. 5l, a god ion will be implanted to form the source and the pole of the even string selection transistor 572 and the odd string selection transistor 574. Although the present invention has been described as a preferred embodiment of the present invention, it is intended to define the present invention. Any person skilled in the art can make some changes to the present invention without departing from the spirit and scope of the present invention. Lai Xi # is subject to the definition of the patent application scope attached. [Simple description of the diagram] Figure 1 shows the cross-sectional view of the 1325135 with the unit cell embodiment. Figure 2 is a circuit diagram of a memory cell array of the present invention. Fig. 3A is a two-string circuit for forming a memory cell array of the present invention. _° Fig. 3B is a view showing an embodiment of the two-string circuit of the present invention. Figure 4 is a schematic diagram showing the supply voltage, word line, control gate, select gate, and other supply voltages in erase, stylize, and read memory cell overshoot. Figures 5A-5L are cross-sectional views of various stages of the process of the present invention. [Main component symbol description] 100 memory cell 110 substrate 120 active region 130 cell stack 132 first dielectric layer 134 charge accumulation layer 136 second dielectric layer 138 control gate 140 selection stack 142 selection gate 145 selection Stack 147 Select Gate 150 Sidewall 155 Sidewall 160 Third Dielectric Layer 165 Third Dielectric Layer 502 Substrate 504 P Well Active Layer 506 Oxide Layer 508 Tantalum Nitride Layer 510 Ceria Layer 512 Polycrystalline Layer 514 Deuteration Tungsten layer 516 gasified sand layer 518 photoresist layer 520-530 unit cell stack 540 nitride layer 542 bottom layer 16

Claims (1)

544 side portion 55 〇 〇 夕 554 layer 554 side portion 560 cerium oxide layer 564 photoresist layer 546 top portion 552 bottom layer 556 top portion 562 polycrystalline layer 556 cerium oxide layer 10, the scope of application: and ^ 性 记 ' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the above, the cell stack includes a f-distributed layer disposed above the substrate, and a charge accumulating layer disposed above the first dielectric layer, which can store information and configure information. a first electrical layer above the charge accumulating layer and a control electrode disposed above the second dielectric layer, the k-stack comprising - a third dielectric disposed above the substrate Selecting a closed pole above the dielectric layer, the memory cell 210 has a first state of the source and drain regions, and a voltage can be supplied to the selected closed terminal to enable the select gate to the lower channel region a second state β μ曰曰 converted to the source/dippole function of the memory abortion 2. According to the inverse of the claim 1 and the non-volatile memory unit cell, wherein the cell line is programmed by injecting electrons from the source terminal.思思 3. According to the reverse of the request 1 and the non-volatile memory unit cell, the layer contains nitriding. -μ电电系 17 4. The non-volatile memory cell according to claim 1, wherein either side of the charge accumulation layer can store one-bit information. 5' The reverse-non-volatile memory cell according to claim 1, wherein the selective gate comprises polysilicon. 6. The non-volatile memory cell according to claim 1, wherein the sidewall comprises an inner layer of tantalum nitride and an outer layer of germanium dioxide. 7 - a non-volatile memory cell array comprising: a plurality of memory cells arranged in a plurality of columns and rows, and wherein the memory cells in the same row are connected in series to form a cell string, And each end of the cell string is connected to a selective transistor; and ^ a plurality of bit line pairs, the bit line pair includes an even bit line and an odd bit line, the even bit line Connected to the selection transistor disposed at one end of the two adjacent cell strings, the odd bit line is connected to the selection transistor disposed at an opposite end of the two adjacent cell strings; wherein, the memory cell A unit cell stack and a second selection stack are disposed on a substrate, and the selected stacks are respectively disposed on each side of the unit cell stack and disposed between the unit cell stack and the selected stacks. a side wall; the cell stack includes a first dielectric layer disposed above the substrate, and a charge accumulating layer disposed above the first dielectric layer, wherein the charge is stored in a portion to store information, Configured above the charge accumulation layer a dielectric layer and a control side electrode disposed above the second dielectric layer; the respective = stack includes a third dielectric phase disposed above the top layer and - disposed above the third dielectric layer Selecting a gate, the memory cell has a first state that does not contain a pole and a poleless region, and can be converted to a lower channel region of the selected gate via the selected supply-electricity, 18-voltage A second state of the source/drain function of the memory cell. 8. The anti-volatile memory cell array according to claim 7, wherein during the stylization process, electrons are injected into a portion of the charge accumulation layer by source side injection. 9. The anti-volatile memory cell array according to claim 7, wherein the charge accumulating layer contains tantalum nitride. 10. According to the item 7 of the non-volatile memory cell array, wherein either side of the charge accumulation layer can store one-bit information. 11. The anti-volatile memory cell array according to claim 7, wherein the sidewall comprises an inner layer of tantalum nitride and an outer layer of germanium dioxide. I2. According to the inverse of the non-volatile memory cell array of claim 7, a plurality of depletion mode transistors may be further included.