16440twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種電源供應系統’且特別是有關於 一種節省電力的電源供應之方法與裂置。 【先前技術】 隨著科技的進步與生活品質的持續提升，加上冗產 業的整合與持續成長’使得積體電路的應用領域越來越 廣。電子產品也不斷地朝向輕薄短小、多魏 低的方向發展。 -般來說，傳統的積體電路❹功能產品的電源配 置，會配置如圖1的架構，請參考圖卜i中包括電壓 調節器100、第一負載區塊102、第二負载區塊1〇4、第三 負載區塊106以及第四負載區塊1〇8。其中，電； 綱的輸入電壓為VDD。假設每一個負載區塊使用的電源 電壓皆為電壓調節器10 0所輸出的v〇ut。另外，假哎第二 負載區塊102所需供應的電流為第一電流n，第二 塊104所需供應的電流為第二電流12、第三負載區塊 所需供應的第四負載區塊1G 應的電流為第四電流14。 ％164. The invention is related to a power supply system, and in particular to a method and a split for a power-saving power supply. [Prior Art] With the advancement of technology and the continuous improvement of the quality of life, coupled with the integration and continuous growth of the redundant industry, the application fields of integrated circuits are becoming more and more extensive. Electronic products are also constantly moving towards light, short, and low. Generally speaking, the power configuration of the conventional integrated circuit ❹ functional product will be configured as shown in FIG. 1 , please refer to FIG. 1 including the voltage regulator 100, the first load block 102, and the second load block 1 〇4, the third load block 106 and the fourth load block 1〇8. Among them, the input voltage of the circuit is VDD. It is assumed that the power supply voltage used by each load block is v〇ut output by the voltage regulator 10 0. In addition, the current required to supply the second load block 102 is the first current n, and the current required to be supplied by the second block 104 is the second current 12, and the fourth load block to be supplied by the third load block. The current that 1G should be the fourth current 14. %
若圖1的電壓調節器100以—般的線性電壓調節器 取代，在理想的狀況下，此電壓調節器100的輸入電i U 等於11+12+13+14。而此電壓調節器1〇〇的功率消耗會 Iin*(VDDH-V〇ut)。然而’若考慮不理想狀況，則會^承 多的電力。 K 1644〇twf.doc/〇〇6 【發明内容】 用以 本發明的目的就是在提供一種電源供應之裝 減少雩力消耗。 乂 本發明的再一目的是提供一種電源供應之方法， 供應多個負載所需的電力。 以 本發明提出一種電源供應之裝置，用以供應多 所需的電力。此裝置包括N條電源線（N為大於2之自= 數）、電源供應器以及電源控制電路。第！條電源線與= 1+1條電源線之間耗接至少-負載，其中1為自然^且 〇<I<N°電源供應器用以供應第i條電源線_第—電 位’並供應第N條電源線-第二電源電位。綠控制電路 搞接所有的電源線’ _魏/提供第了_丨條電源線盘第j 條電源線之_負載電流以及第；條電源線與第糾、 源線之間的貞载電叙差值使各電祕電壓轉在設計值 上’其中J為自然數且1<j<n。 本發明提出-種電源供應之方法，用以供應多個負載 所需的電力。此方法包括：提供Μ電源線，其中第工條 電源線與第1+1條電源線之間耦接至少一負載，其中I為 自然數且G<I<N。供應第丨條電源線—第―電源電位，並 供應第N條電源線—第二電源電位。吸收/提供第條電 源線與第j條電源線之_負載電流以及第了條電源線與 第W條電源線之間的負載電流之差值使各電源線電卿 持在。又„十值上，其中，N、j為自然數，N大於2且。 依照本發明的較佳實施例所述之電源供應之方法，上 16440twf.doc/006 述之吸收/提供第：·1條電源線與第I條電源線之間的負載 電流以及第J條電源線與第J+1條電源線之間的負載電流 之差偉包括：當第第^條電源線與第：條電源線之間的 負載電流大於第；條電源線與第H1條電源線之間的負載 電抓將此兩負载電流之差值吸收。冑第第條電源線 與第J條電源線之間的負載電流小於第】條電源線與第j+l 條電源線之間的負載電流，供應此兩負載電流之差值至第 J條電源線使各電源線電壓轉在設計值上。 本發明因_在電財透過將貞載適當的串聯以降 低電源供應轉出電流，因此除了可以供應多個負載所需 的電力外，還可以減少電力消耗。 為讓本發月之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例，尬合所關式， 明如下。 v 【實施方式】 圖2為本發明實施例之電源供應之裝置電路圖。請先 參考圖2 ’圖2包括第一負載200、第二負載202、第三負 載撕、第四負载2。6、第-電源線琢、第二電源線、2?0、 第二電源線212、電源控制電路以及電源供應器216。 其中’電源供應器216供應第-電1原電位(在此例如為高電 .位VDD)至第—電源線208»電源供應器216供應第二電源 電位(在此例如為低電位VSS)至第三電源線212。第一負載 2〇〇與第二負載202耦接在第一電源線208與第二電源線 210之間。第三負載2〇4與第四負載2〇6耦接在第二電源 16440twf,doc/006 線210與第三電源線212之間。而第一電源線2〇8、第二 電源線210與第三電源線212均輕接至電源控制電路214。 為了說明方便’本實施例做了以下假設，但本發明不 以此為限。首先’假設VDD為5V，VSS為接地〇V。另 外，假設第一負載200、第二負载202、第三負载204以及 第四負載206的電源供應電壓設計值為2.5 V(所謂的負載 電路的電源供應電壓設計值’熟知此技術者應當知道，根 據不同電路’會有不同的設計值，將在以下實施例中欽 述）。第一負載200所需的電流定義做第一電流n、第二負 載202所需的電流定義做第二電流12、第三負載2〇4所需 的電流定義做第三電流13、第四負載206所需的電流定義 做第四電流14。另外假設電源控制電路214用以鉗制 (Clamp)第二電源線210上的電壓，使第二電源線21〇之電 壓準位保持在2.5V。 首先，電源供應器216供應5v電壓至第一電源線 208 ’並供應0V電壓至第三電源線212。設計此電路時， 可考慮第一電流II加上第二電流12近似於第三電流13加 上第四電流14。若理想狀況下，第一電流n加上第二電流 12專於第二電流13加上第四電流μ。 然而，上面的例子為特殊例子。一般來說，設計者僅 可能盡量讓第-電流n加第二電流12近似於第三電流13 加第=電流14。若當第—電流u加第二電流12稱大於第 三電流13加第四電流14時，電源控制電路214便吸收 16440twf.doc/006 I1+I2_(I3+I4)的電流差值，將此電流導入第三電源線212， 並使第一電源線210上的電壓維持在2 5V。若當第一電流 II加等二電流12稍小於第三電流13加第四電流14時，電 源控制電路214便利用電源供應器216供應I3+I4_(I1+I2) 的電流差值至第二電源線21〇。 然而’此技術並不一定要負載所需的電源供應電壓相 同方能實施。例如第一負載2〇〇與第二負載2〇2的電源供 應電壓設計值為2.2V、第三負载2〇4與第四負載2〇6的電 源供應電壓設計值為2.8V，或是第一負載2〇〇與第二負載 202的電源供應電壓設計值為18v、第三負載2〇4與第四 負載206的電源供應電壓設計值為3·2ν。只要是第一電源 線208與第二電源線21〇之間的負載的電壓設計值，加上 第-電源線21G與第三電源線之間的貞載的賴、電壓設計 值，兩者的和等於第一電源線2〇8與第三電源線212之間 的電壓，經由電源控制電路214的控制，此電路即可以正 常運作。 以本發明實施例圖2的拓樸架構與習知圖丨的拓樸架 構作比較，習知圖1的總功率為，然 而本貫施例圖2的總功率為VDD*MAX(11+12,13+14)，因 此本發明可以大幅降低總功率。再者，比較習知圖！與本 實施例® 2巾之功率損失，習知圖1的架構有 (VDD-Vout)*(Il+I2+I3+I4)是電壓調節器1〇〇之功率消 耗，以圖2來說，電源控制電路214的功率消耗為 16440twf.doc/006 204/206所需的電源供應電壓相同）。對習知圖！來說， 此為今要的功率消耗。然而，對圖2來說，若電路設計得 當，便可以更加減少功率消耗。 另外’現在積體電路的應用上，常需要整合多個供應 電壓的結構，例如在積體電路中類比電路需要3.〇v，數位 邏輯與έ己憶體需要2.0V。然而習知的做法便如圖1，針對 每個所需的電壓(3.0V或2.0V)，分別配置不同的電壓調節 器，以便將外部提供之電源電壓（例如5.〇ν)降壓至3.0V 與2.0V。在追些電壓調節器降壓而供應各種内部電壓的過 知中’將會產生許多功率損失，減低電路效率、然而利用 本發明的技術，將積體電路中之負載串接而省去電麼調節 為’便可以減少功率損失再者，f知圖丨架構使用了電 歷調節器’由於電壓調節器需要供應大電流，因此其勢必 佔據晶片很大的面積。錢用本發明實關電源控制電 此電路供應電流僅為麵差值。相較於習知的大電流， ”施=須供應小電後，若本發明___路 成^必可以減少“柄⑽，進《少積體電路晶片 ^ 列之電源供應之裝置電路圖， Μ參考圖3。此電路包括第〜負載細 三負載304、第四負載306、第五負載％ 電載=第 第二電源線312、第三電源錄 t原線310、 、緣314、第四電源線316、電源 1323063 16440twf.doc/006 控制電路318以及電源供應器32卜其中 供應第—電源電位(例如高電位卿)至第_電_If the voltage regulator 100 of Figure 1 is replaced by a general linear voltage regulator, under ideal conditions, the input power i U of the voltage regulator 100 is equal to 11+12+13+14. The power consumption of this voltage regulator 1〇〇 is Iin*(VDDH-V〇ut). However, if you consider the unsatisfactory situation, you will have more electricity. K 1644〇twf.doc/〇〇6 SUMMARY OF THE INVENTION The object of the present invention is to provide a power supply package that reduces power consumption. Still another object of the present invention is to provide a method of supplying power to supply power required for a plurality of loads. The present invention proposes a power supply device for supplying a plurality of required power. The device includes N power lines (N is greater than 2 since the number), a power supply, and a power control circuit. The first! Between the power line and the = 1+1 power line, at least the load is consumed, where 1 is natural ^ and 〇 <I<N° power supply is used to supply the ith power line _ first potential and supply the first N power lines - second power supply potential. The green control circuit connects all the power lines' _Wei/Provides the first _ 电源 电源 电源 电源 第 第 j 电源 电源 电源 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载 负载The difference causes each voltage to be turned on the design value 'where J is a natural number and 1<j<n. The present invention proposes a method of power supply for supplying power required for a plurality of loads. The method includes: providing a power line, wherein the first power line and the 1+1 power line are coupled to at least one load, where I is a natural number and G<I<N. Supply the first power cord - the first power supply potential, and supply the Nth power supply line - the second power supply potential. The difference between the load current of the first power supply line and the jth power supply line and the load current between the first power supply line and the Wth power supply line is such that each power supply line is held. Further, in the tens of values, wherein N and j are natural numbers, and N is greater than 2. And, according to the method of power supply according to the preferred embodiment of the present invention, the absorption/providing method described in the above 16440 twf.doc/006: The difference between the load current between the 1 power line and the 1st power line and the load current between the Jth power line and the J+1th power line includes: when the first ^ power line and the first: The load current between the power lines is greater than the first; the load between the power line and the H1 power line is absorbed by the difference between the two load currents. Between the first power line and the Jth power line The load current is less than the load current between the power supply line and the j+l power supply line, and the difference between the two load currents is supplied to the Jth power supply line to turn the voltage of each power supply line to a design value. _In the case of electricity, the appropriate series connection to reduce the power supply to reduce the current, in addition to the power required to supply multiple loads, can also reduce power consumption. For the above and other purposes, characteristics of this month And advantages can be more clearly understood. The following is a preferred embodiment, [Embodiment] FIG. 2 is a circuit diagram of a power supply device according to an embodiment of the present invention. Referring first to FIG. 2, FIG. 2 includes a first load 200, a second load 202, and a third load tear. The fourth load 2.6, the first power line 琢, the second power line, the second power line 212, the power control circuit, and the power supply 216. The power supply 216 supplies the first power The potential (here, for example, high power. bit VDD) to the first power line 208» power supply 216 supplies a second power supply potential (here, for example, a low potential VSS) to the third power line 212. The first load 2〇〇 The second load 202 is coupled between the first power line 208 and the second power line 210. The third load 2〇4 and the fourth load 2〇6 are coupled to the second power source 16440twf, the doc/006 line 210 and the first The first power line 2〇8, the second power line 210 and the third power line 212 are all connected to the power control circuit 214. For convenience of description, the following assumptions are made in this embodiment, but The invention is not limited to this. First, 'assuming VDD is 5V and VSS is ground 〇V. In addition, assume the first load 20 0. The power supply voltage of the second load 202, the third load 204, and the fourth load 206 is designed to be 2.5 V (the so-called power supply voltage design value of the load circuit is well known to those skilled in the art, and depending on the circuit) Different design values will be explained in the following embodiments. The current required for the first load 200 is defined as the current required for the first current n and the second load 202 is defined as the second current 12 and the third load 2〇. 4 The required current is defined as the third current 13. The current required for the fourth load 206 is defined as the fourth current 14. It is further assumed that the power control circuit 214 is used to clamp the voltage on the second power line 210. The voltage level of the two power lines 21〇 is maintained at 2.5V. First, the power supply 216 supplies a voltage of 5v to the first power line 208' and supplies a voltage of 0V to the third power line 212. When designing this circuit, it is contemplated that the first current II plus the second current 12 approximates the third current 13 plus the fourth current 14. In the ideal case, the first current n plus the second current 12 is specific to the second current 13 plus the fourth current μ. However, the above example is a special example. In general, the designer is only likely to let the first current n plus the second current 12 approximate the third current 13 plus the = current 14. If the first current u plus the second current 12 is greater than the third current 13 plus the fourth current 14, the power control circuit 214 absorbs the current difference of 16440 twf.doc / 006 I1 + I2_ (I3 + I4), Current is directed to the third power line 212 and the voltage on the first power line 210 is maintained at 25 V. If the first current II plus the equal current 12 is slightly smaller than the third current 13 plus the fourth current 14, the power control circuit 214 facilitates supplying the current difference of I3+I4_(I1+I2) to the second by the power supply 216. The power cord is 21〇. However, this technology does not necessarily require the same power supply voltage required for the load to be implemented. For example, the power supply voltage design value of the first load 2〇〇 and the second load 2〇2 is 2.2V, and the power supply voltage design value of the third load 2〇4 and the fourth load 2〇6 is 2.8V, or The power supply voltage design value of one load 2〇〇 and the second load 202 is 18v, and the power supply voltage design value of the third load 2〇4 and the fourth load 206 is 3·2ν. As long as it is the voltage design value of the load between the first power line 208 and the second power line 21〇, plus the design value of the load between the first power line 21G and the third power line, both of which are And the voltage between the first power line 2〇8 and the third power line 212 is controlled by the power control circuit 214, and the circuit can operate normally. Comparing the topology of FIG. 2 with the topology of the conventional diagram in the embodiment of the present invention, the total power of FIG. 1 is known, but the total power of FIG. 2 is VDD*MAX (11+12). , 13+14), so the present invention can greatly reduce the total power. Furthermore, compare the familiar map! With the power loss of the present embodiment, the structure of the conventional FIG. 1 has (VDD-Vout)*(Il+I2+I3+I4) is the power consumption of the voltage regulator 1,, as shown in FIG. The power consumption of the power control circuit 214 is the same as the power supply voltage required for the 16440 twf.doc/006 204/206. For the custom map! For this reason, this is the power consumption that is required today. However, for Figure 2, if the circuit is properly designed, the power consumption can be further reduced. In addition, in the application of integrated circuits, it is often necessary to integrate multiple supply voltages. For example, analog circuits need to be 3.〇v in integrated circuits, and digital logic and 2.0V are required. However, the conventional practice is as shown in Figure 1. For each required voltage (3.0V or 2.0V), different voltage regulators are respectively configured to step down the externally supplied power supply voltage (for example, 5.〇ν) to 3.0V and 2.0V. In the over-understanding that some voltage regulators are stepped down to supply various internal voltages, a lot of power loss will be generated, and circuit efficiency will be reduced. However, by using the technique of the present invention, the load in the integrated circuit is connected in series to save power. Adjusting to 'can reduce power loss, and knowing that the architecture uses a power regulator' because the voltage regulator needs to supply a large current, so it is bound to occupy a large area of the wafer. The money is controlled by the power supply of the present invention. The current supplied by the circuit is only the face value difference. Compared with the conventional high current, "Shi = must supply a small power, if the invention ___ road into ^ can reduce the "handle (10), into the "small integrated circuit chip ^ column power supply device circuit diagram, Μ Refer to Figure 3. The circuit includes a first load three load 304, a fourth load 306, a fifth load %, an electric load = a second power line 312, a third power source t original line 310, a rim 314, a fourth power line 316, and a power source. 1323063 16440twf.doc/006 control circuit 318 and power supply 32 in which the first power supply potential (for example, high potential) is supplied to the first power_
電源供應器32〇供應第二電源電位(例如低電位至第 四電源線第-負載300與第二負載3〇2祕在第一 電源線310與第二電源線312之間。第三負載3〇4斑第四 負載306輕接在第二電源線312與第三電源線314之間。 第五負載308輕接再第二電源線314與第四電源線316之 間。第一電源線310、第二電源線312、第三電源線314 以及第四電源線316均耦接至電源控制電路3丨8。 同樣的，為了說明方便，本實施例做了以下假設，但 本發明不以此為限。首先，假設VDD為5V，vss為接地 〇V。另外，假設第一負載300以及第二負載3〇2的電源供 應電M s免s十值為2.0 V。第三負载3〇4以及第四負載3〇6 的電源供應電壓設計值為1.8 V。第五負載3〇8的電源供應The power supply 32 〇 supplies a second power supply potential (for example, the low potential to the fourth power line - the load 300 and the second load 3 〇 2 is between the first power line 310 and the second power line 312. The third load 3 The fourth load 306 is lightly connected between the second power line 312 and the third power line 314. The fifth load 308 is lightly connected between the second power line 314 and the fourth power line 316. The first power line 310 The second power line 312, the third power line 314, and the fourth power line 316 are all coupled to the power control circuit 3丨8. Similarly, for the convenience of description, the following assumptions are made in the present embodiment, but the present invention does not First, assume that VDD is 5V and vss is ground 〇V. In addition, assume that the power supply M s of the first load 300 and the second load 3 免2 is free from s tens of 2.0 V. The third load is 3 〇 4 And the power supply voltage design value of the fourth load 3〇6 is 1.8 V. The power supply of the fifth load 3〇8
電壓設計值為1.2 V。第一負載3〇〇所需的電流定義做第一 電流II。第二負載302所需的電流定義做第二電流12。第 三負載304所需的電流定義做第三電流13。第四負載306 所需的電流定義做第四電流14。第五負載3〇8所需的電流 定義做第五電流15。另外假設電源控制電路31 $用以甜制 (Clamp)以及第三電源線314上的電壓，使第二電源線312 上的電壓穩定在3.0V’第三電源線314上的電壓穩定在 1.2V。 首先’電源供應320供應5V電|至第·一電源線 11 1323063 16440twf.doc/006 310 ’並供應0V電壓至第四電源線3i6。若理想狀況下， 弟一電^IL 11加上第*一電流12專於第三電流13加上第四電 流14，而且第三電流13加上第四電流14會等於第五電流 15。 然而’電路設計上並不一定能設計出理想狀況。一般 來說’設計者僅可能盡量讓第一電流II加第二電流12近 似於第三電流13加第四電流14。若當第一電流η加第二 電流12稍大於第三電流13加第四電流14時，電源控制電 路318便吸收11+12-(13+14)的電流差值，使得第二電源線 312上的電壓維持在3.0V。若當第一電流η加第二電流12 稍小於第三電流13加第四電流14時，電源控制電路214 便供應13+14-(11+12)的電流差值至第二電源線312，使得 第二電源線312上的電壓維持在3.0V。 同樣的’當第三電流13加第四電流14略大於第五電 流15時’電源控制電路318便吸收I3+I4-I5的電流差值， 使得第三電源線314上的電壓維持在1.2V。當第三電流π 加第四電流14略小於第五電流15時，電源控制電路318 便供應15-(13+14)的電流差值’使得第三電源線314上的電 壓維持在1.2V。 由上面兩個實施例’熟知此技術者不難發現，本發明 更可以例如用圖4的方式來實施。由電源供應器供應VDD 與VSS至上下兩條電源線404 〇電源控制電路4〇〇耦接N 個電源線404。相鄰的電源線之間耦接至少一個負載4〇2。 12 1323063 16440twf.doc/006 原理與上述貫施例相同’故不予贅述。 根據上面的實施例，本發明提出一種電源供應之方 法。® 5為本發明實施例之電源供應之方法流程圖，請參 考圖5。首先，提供N條電源線，其中第I條電源線與第 1+1條電源線之間耦接至少一負載(步驟5〇1)。供應第i條 電源線第一電源電位(如上面實施例的VDD)，並供應第N 條電源線第二電源電位（如上面實施例的vss)(步驟 5〇3)。吸收/提供第條電源線與第了條電源線之間的負 f電流以及第J條電源線與第J+1條電源線之間的負載電 流之差值，其中，N、〗、】為自然數且N大於2(步驟5〇5)。 其中，步驟505包括下面幾個子步驟。首先，判斷第 J-1條電源線與第m電源線之間的負載電流大於或小於第 條電源線與第J+1條電源線之間的負载電流(步驟515)。 2斷為大於時，吸收此兩負載電流之差值（步驟525)。 i(步nr時’供應此兩負載電流之差值至第j條電源 的本發明因_錢路巾整合㈣供應電墨 二=何以供應多個負載所需的電力外，還可 限定議·^，财並非用以 和範=當=此技藝者’在不脫離本發明之精神 ，當視後附之申請專利範圍所界定者3本 護 【圖式簡單說明】 A者為準。 13 1323063 16440twf.doc/006 圖l繪示為習知積體電路電源配置電路方塊圖。 圖2繪示為本發明一實施例電源供應之裝置電路方塊 圖。 圖3繪示為本發明另一實施例電源供應之裝置電路方 塊圖。 圖4繪示為本發明再一實施例電源供應之裴置電路方 塊圖。 圖5繪示為本發明一實施例電源供應之方法流程圖。 【主要元件符號說明】 100 :電壓調節器 102 :第一負載區塊 104 :第二負載區塊 106 :第三負載區塊 108 :第四負載區塊 11 ： 第一電流 12 ： 第二電流 13 : 第三電流 14 ： 第四電流 15 ： 第五電流 200 、300 :第一 負 載 202 、302 :第二 負 載 204 、304 :第三 負 載 206 、306 :第四 負 載 14 1323063 16440twf.doc/006 208、310 :第一電源線 210、312 :第二電源線 212、314 :第三電源線 ‘ 214、318、400 :電源控制電路 • 216、320、410 :電源供應器 308 :第五負載 316 :第四電源線 404 :N條電源線 • 402 :多個負載 501〜535 :本發明實施例之步驟 15The voltage design value is 1.2 V. The current required for the first load 3 定义 is defined as the first current II. The current required for the second load 302 is defined as the second current 12. The current required for the third load 304 is defined as the third current 13. The current required for the fourth load 306 is defined as the fourth current 14. The current required for the fifth load 3〇8 is defined as the fifth current 15. In addition, it is assumed that the power control circuit 31$ is used for the voltage on the Clamp and the third power line 314, so that the voltage on the second power line 312 is stabilized at 3.0V. The voltage on the third power line 314 is stable at 1.2V. . First, the power supply 320 supplies 5V power|to the first power supply line 11 1323063 16440twf.doc/006 310' and supplies the 0V voltage to the fourth power supply line 3i6. In the ideal case, the first voltage 12 is added to the third current 13 plus the fourth current 14, and the third current 13 plus the fourth current 14 is equal to the fifth current 15. However, 'the circuit design does not necessarily design the ideal situation. In general, the designer may only try to have the first current II plus the second current 12 be similar to the third current 13 plus the fourth current 14. If the first current η plus the second current 12 is slightly larger than the third current 13 plus the fourth current 14, the power control circuit 318 absorbs the current difference of 11+12-(13+14), so that the second power line 312 The voltage on it is maintained at 3.0V. If the first current η plus the second current 12 is slightly smaller than the third current 13 plus the fourth current 14, the power control circuit 214 supplies a current difference of 13+14-(11+12) to the second power line 312. The voltage on the second power line 312 is maintained at 3.0V. Similarly, when the third current 13 plus the fourth current 14 is slightly larger than the fifth current 15, the power control circuit 318 absorbs the current difference of I3+I4-I5 so that the voltage on the third power line 314 is maintained at 1.2V. . When the third current π plus the fourth current 14 is slightly less than the fifth current 15, the power supply control circuit 318 supplies a current difference of '-(13+14)' such that the voltage on the third power line 314 is maintained at 1.2V. It will be readily apparent to those skilled in the art from the above two embodiments that the present invention can be implemented, for example, in the manner of Figure 4. VDD and VSS are supplied from the power supply to the upper and lower power lines 404, and the power control circuit 4 is coupled to the N power lines 404. At least one load 4〇2 is coupled between adjacent power lines. 12 1323063 16440twf.doc/006 The principle is the same as the above-mentioned embodiment, so it will not be repeated. According to the above embodiment, the present invention proposes a method of power supply. ® 5 is a flow chart of a method of power supply according to an embodiment of the present invention, please refer to FIG. 5. First, N power supply lines are provided, wherein at least one load is coupled between the first power supply line and the 1+1th power supply line (step 5〇1). The i-th power supply line first power supply potential (such as VDD of the above embodiment) is supplied, and the Nth power supply line second power supply potential (such as vss of the above embodiment) is supplied (step 5〇3). Absorbing/providing the difference between the negative f current between the first power line and the first power line and the load current between the Jth power line and the J+1th power line, where N, 〖, and Natural number and N is greater than 2 (step 5〇5). Wherein, step 505 includes the following sub-steps. First, it is judged that the load current between the J-1th power supply line and the mth power supply line is greater or smaller than the load current between the first power supply line and the J+1th power supply line (step 515). When 2 is greater than, the difference between the two load currents is absorbed (step 525). i (when nr, the difference between the supply of the two load currents to the jth power supply is due to the integration of the money road towel (4) supply of electric ink 2 = how to supply the power required for multiple loads, and may also be limited ^, Finance is not used and Fan = when = this artist's without departing from the spirit of the present invention, as defined by the scope of the patent application, which is defined by the scope of the application of the patent, [the simple description of the schema] A. 13 1323063 16440twf Figure 1 is a block diagram of a power supply configuration circuit of a conventional integrated circuit. Figure 2 is a block diagram of a power supply device according to an embodiment of the present invention. Figure 4 is a block diagram of a power supply circuit according to still another embodiment of the present invention. Figure 5 is a flow chart showing a method of power supply according to an embodiment of the present invention. 100: voltage regulator 102: first load block 104: second load block 106: third load block 108: fourth load block 11: first current 12: second current 13: third current 14: Fourth current 15 : fifth current 200, 300: first load 202, 302: second load 204, 304: third load 206, 306: fourth load 14 1323063 16440twf.doc / 006 208, 310: first power line 210, 312: second power Lines 212, 314: third power line '214, 318, 400: power control circuit • 216, 320, 410: power supply 308: fifth load 316: fourth power line 404: N power lines • 402: multi Loads 501~535: Step 15 of the embodiment of the present invention