200814485f.d〇c/〇〇6 九 '發明說明： 【發明所屬之技術領域】 ，發明是有關於一種電源供應系統，且特別是有關於 一種節省電力的電源供應之方法與裴置。 【先前技術】 隨著科技的進步與生活品質的持續提升’加上3C產 業的整合與持續成長，使得積體電路的應用領域越來越 廣。電子產品也不斷地朝向輕薄短小、多功能以及耗電量 低的方向發展。 一般來說，傳統的積體電路或多功能產品的電源配 置丄會配置如圖1的架構，請參考圖i。圖i中包括電壓 調節器100、第一負載區塊102、第二負載區塊1〇4、第三 負載區塊106以及第四負載區塊。其中，電壓調節哭 100的輸入電壓為VDD。假設每一個負載區塊使用的電& 電壓皆為電壓調節器100所輸出的v〇ut。另外，假設第一 負載區塊102所需供應的電流為第一電流n，第二負載區 •塊104所需供應的電流為第二電流12、第三負载區塊應 所需供應的電流為第三電流13 ,第四負載區塊1〇8所需供 應的電流為第四電流14。 若圖1的電壓調節器1〇〇以一般的線性電壓調節器來 取代，在理想的狀況下，此電壓調節器100的輸入電流Iin 等於11+12+13+14。而此電壓調節器1〇〇的功率消耗會等於 Iin (VDDH-Vout)。然而，若考慮不理想狀況，則會消耗更 多的電力。 5 200814485^^/006 【發明内容】 、本發明的目的就是在提供一種電源供應之裝置，用以 減少零力消耗。 本發明的再-目的是提供一種電源供應之方法，用以 供應多個負載所需的電力。200814485f.d〇c/〇〇6 九 'Inventive description: [Technical field to which the invention pertains] The invention relates to a power supply system, and in particular to a method and a device for saving power. [Prior Art] With the advancement of technology and the continuous improvement of the quality of life, coupled with the integration and continuous growth of the 3C industry, the application fields of integrated circuits are becoming more and more extensive. Electronic products are also constantly moving toward thin, short, versatile and low power consumption. In general, the power configuration of a conventional integrated circuit or multi-function product will be configured as shown in Figure 1. Please refer to Figure i. The voltage regulator 100, the first load block 102, the second load block 1-4, the third load block 106, and the fourth load block are included in FIG. Among them, the voltage adjustment cry 100 input voltage is VDD. It is assumed that the electric & voltage used by each load block is v〇ut outputted by the voltage regulator 100. In addition, assuming that the current required to be supplied by the first load block 102 is the first current n, the current required to be supplied by the second load region block 104 is the second current 12, and the current required to be supplied by the third load block is The third current 13 and the current required to be supplied by the fourth load block 1〇8 are the fourth current 14. If the voltage regulator 1 of Figure 1 is replaced by a general linear voltage regulator, under ideal conditions, the input current Iin of the voltage regulator 100 is equal to 11+12+13+14. The power consumption of this voltage regulator 1〇〇 will be equal to Iin (VDDH-Vout). However, if you consider an undesired situation, you will consume more power. 5 200814485^^/006 SUMMARY OF THE INVENTION The object of the present invention is to provide a power supply device for reducing zero force consumption. A further object of the present invention is to provide a method of power supply for supplying power required by a plurality of loads.
本發明提出-種電源供應之裂置，用以供應多個負載 所需的電力。此裝置包括N條電源線（N為大於2之自缺 數）、電源供應器以及電源控制電路。第〗條 第 叫條電源線之間祕至少-負载，其中 〇<I<N。電源供應器用以供應第i條電源線—第—電源電 位’亚供應第n條電源線-第二電源電位。電源控制電路 輕接所有的魏線，_魏/提供第W條魏線與第J 條電源線之間的負載電流以及第J條電源線與第J+1條電 源線之_貞載電流之差做各電麟電壓_在設計值 上’其中J為自然數且1<j<N。 本發明提出一種電源供應之方法，用以供應多個負載 所需的電力。此方法包括··提供^^條電源線，其中第工條 電源線與第1+1條電源線之間耦接至少一負載，其中I為 自然，且G<I<N。供應第丨條電源線—第―電源電位，並 供應第N條電源線一第二電源電位。吸收/提供第w條電 ，線與第；條電源線之間的負載電流以及第】條電源線與 第J+1條電源線之間的負載電流之差值使各電源線電壓維 持在没计值上，其中，N、j為自然數，N大於2且1<J<N。 依照本發明的較佳實施例所述之電源供應之方法，上 6 200814485^doc/006 述之吸收/提供第j-i條電源線與第j條電源線之間的負載 電流以及第J條電源線與第J+1條電源線之間的負载電流 之差偉包括··當第第J-1條電源線與第J條電源線之間的 負載電流大於第J條電源線與第J+1條電源線之間的負載 電流，將此兩負載電流之差值吸收。當第第條電源線 與第J條電源線之間的負載電流小於第J條電源線與 1 條電源線之間的負載電流，供應此兩負載電流之差值至第 J條電源線使各電源線電壓維持在設計值上。 本發明因採用在電路中透過將負載適當的串聯以降 低電源供應器輸出電流，因此除了可以供應多個負載所需 的電力外，還可以減少電力消耗。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 ’ 【實施方式】 圖2為本發明實施例之電源供應之裝置電路圖。請先 參考圖2，圖2包括第一負載200、第二負載2〇2、第三負 載204、第四負載2〇6、第一電源線2〇8、第二電源線^、、 第三電源線212、電源控制電路214以及電源供應器216。 其中，電源供應裔216供應第一電源電位(在此例如為高電 位VDD)至第一電源線2〇8。電源供應器216供應第二電源 電位(在此例如為低電位VSS)至第三電源線212。第一負載 200與第二負载202耦接在第一電源線208與第二電源線 210之間。第三負載204與第四負載2〇6耦接在第二電源 7 200814485— 線210與第三電源線212之間。而第一電源線208、第二 電源線210與第三電源線212均麵接至電源控制電路214。 奉了說明方便，本實施例做了以下假設，但本發明不 以此為限。首先，假設VDD為5V，VSS為接地〇v。另 外，假設第一負載200、第二負載202、第三負载204以及 第四負載206的電源供應電壓設計值為2·5 V(所謂的負載 電路的電源供應電壓設計值，熟知此技術者應當知道，根 據不同電路，會有不同的設計值，將在以下實施例中敘 述）。第一負載2〇〇所需的電流定義做第一電流η、第二負 載202所需的電流定義做第二電流12、第三負载2〇4所需 的電流定義做第三電流13、第四負載206所需的電流定義 做第四電流14。另外假設電源控制電路214用以钳制 (Clamp)第二電源線210上的電壓，使第二電源線21〇之電 壓準位保持在2.5V。 首先，電源供應器216供應5V電壓至第一電源線 2〇8 ’並供應*〇V電壓至第二電源線212。設計此電路時， 可考慮第一電流II加上第二電流12近似於第三電流13加 上第四電流14。若理想狀況下，第一電流n加上第二電流 12等於第三電流13加上第四電流14。 然而，上面的例子為特殊例子。一般來說，設計者僅 可，盡量讓第-電流II加第二電流12近似於第三電流13 ^第=電流14。若當第—電流11加第二電流12稱大於第 一電/现13加第四電流14時，電源控制電路2ι4便吸收 8 200814485f d〇c/〇°6 I1+I2_(I3+M)的電流差值，將此電流導入第三電源線犯， 並使第二電源線210上的電壓維持在2·5ν。若當第一電流 II加萆二電流12稍小於第三電流13加第四電流14時，電 源控制電路214便利用電源供應器216供應Ι3+Ι4_(Ι1+Ι2) 的電流差值至第二電源線210。 然而’此技術並不一定要負載所需的電源供應電壓相 同方能實施。例如第一負載2〇〇與第二負載2〇2的電源供 應電壓設計值為2·2V、第三負載2〇4與第四負載2〇6的電 源供應電壓設計值為2.8V，或是第一負載2〇〇與第二負載 202的電源供應電壓設計值為18¥、第三負載2〇4與第四 負載206的電源供應電壓設計值為3·2ν。只要是第一電源 線208與第二電源線210之間的負載的電壓設計值，加上 第二電源線210與第三電源線之間的負載的電源電壓設計 值，兩者的和等於第一電源線2〇8與第三電源線212之間 的電壓，經由電源控制電路214的控制，此電路即可以正 常運作。 - 以本發明實施例圖2的拓樸架構與習知圖丨的拓樸架 構作比較，習知圖1的總功率為VDD*(I1+I2+I3+I4)，然 而本實施例圖2的總功率為VDD*MAX(I1+I2，I3+I4)，因 此本發明可以大幅降低總功率。再者，比較習知圖丨與本 實施例圖2中之功率損失，習知圖1的架構有 (VDD-V〇ut)*(Il+I2+I3+I4)是電壓調節器1〇〇之功率消 耗，以圖2來说，電源控制電路214的功率消耗為 9 200814485·祕 =；f1[(I1+I2Ml3+I4)]j (假設負載蠢02與負載 204/206所需的電源供庫雷厭士门、私 ” M執 此為必要的功率I肖耗相同）。對習知圖1來說， 對圖2來說，若電路設計得 虽，便可以更加減少功率消耗。 雷現在積體電__上，常需要整合多個供應 Γ 積體電路中類比電路需要3浙，數位 ^輯”讀、體需要2.0V。然而f知的做法便如圖i，針對 Γ個所需的電壓(娜或，，分別配置不同的電壓調節 益，以便將外部提供之電源電壓（例如5 〇v)降壓至3观 〜2.0V纟這些電壓調節II降壓而供應各種内部電壓的過 耘中’將會產生許多功率損失，減低電路效率。然而利用 =發明的技術，將積體電財之負載串接而省去電壓調節 為，便可以減少功率損失。再者，習知圖i架構使用了電 壓調節器，由於電麈調節器需要供應大電流，因此其勢: 佔據晶片很大的面積。若使用本發明實施例電源控制電 路，此電路供應電流僅為電流差值。相較於習知的大電流， 本發明實施例只須供應小電流，若本發明應用於積體電路 上，勢必可以減少晶片佈局空間，進而減少積體電路晶片 的成本。 圖3為本發明另一實施例之電源供應之裝置電路圖， 請參考圖3。此電路包括第一負載300、第二負载3〇2、第 三負載304、第四負載306、第五負載308、第一電源線31〇、 第二電源線312、第三電源線314、第四電源線316、電源 200814485·福 控制,318以及電源供應器32〇。其中，電源供應器32〇 供應第一電源電位(例如高電位VDD)至第一電源線31〇。 電源牮應1§ 320供應第二電源電位(例如低電位vss)至第 四電源線316。第一負載300與第二負載3〇2耦接在第一 電源線310與第二電源線312之間。第三負载3〇4與第四 負載306耦接在第二電源線312與第三電源線314之間。 第五負載308耦接再第三電源線314與第四電源線316之 間。第一電源線310、第二電源線312、第三電源線314 以及弟四電源線316均輕接至電源控制電路ΜΑ。 同樣的，為了說明方便，本實施例做了以下假設，但 本發明不以此為限。首先，假設VDD為5V，vss為接地 〇 V。另外，假設第一負載3 〇 〇以及第二負載3 〇 2的電源供 應電壓設計值為2.0 V。第三負載3〇4以及第四負載3〇6 的電源供應電壓設計值為h8v。第五負載通的電源供應 電壓設計值為1.2V。第—負載所需的電蚊義做第一 電流II。第二負載302所需的電流定義做第二電流12。第 三負載304所需的電流定義做第三電流13。第四負載遍 所需的電流定義做第四電流14。第五負載娜所需的電流 定義做第五電流15。另外假設電源控制電路318用以甜制 (Clamp)以及第三電源線314上的電壓，使第二電源線312 上的電壓穩定在3游，第三電源線314上的電壓穩定在 1.2V。 首先’電源供應器32()供應^電壓至第—電源線 11 200814485f.d〇 c/006 31〇，並供應ον電壓至第四電源線316。若理想狀況下， =一電流π加上第二電流12等於第三電流13二上第四電 流14，而且第三電流13加上第四電流14會等於第五電流 15 〇 然而，電路設計上並不一定能設計出理想狀況。一般 來說，設計者僅可能盡量讓第一電流n加第二電流12近 似於第三電流13加第四電流14。若當第一電流n加第二 電流12稍大於第三電流13加第四電流14時，電源控制^ 路318便吸收I1+I2_(I3+I4)的電流差值，使得第二電源線 312上的電壓維持在3 〇v。若當第一電流n加第二電流乜 稍小於第三電流13加第四電流14時，鶴㈣電路’叫 ，供應13+14-(11+12)的電流差值至第二電源線312，使得 第二電源線312上的電壓維持在3.0V。 同樣的，當第三電流13加第四電流14略大於第五電 "IL15 k ’電源控制電路318便吸收I3+I4-I5的電流差值， 使得第三電源線314上的電壓維持在1.2V。當第三電流13 加第四電流14略小於第五電流;[5時，電源控制電路 便供應15-(13+14)的電流差值，使得第三電源線314上的 壓維持在1.2V。 由上面兩個實施例，熟知此技術者不難發現，本發明 更可以例如用圖4的方式來實施。由電源供應器供應vXdd 與VSS至上下兩條電源線404。電源控制電路4〇〇轉接N 個電源線404。相鄰的電源線之間耦接至少一個負載4〇2。 12 200814485— 原理與上述實施例相同’故不予赞述。 根據上面的實施例，本發明提出一種電源供應之方 法。琴5為本發明實施例之電源供應之方法流程圖，請參 考圖5。首先，提供N條電源線，其中第I條電源線與第 1+1條電源線之間耦接至少一負載(步驟5〇1)。供應第1條The present invention proposes a split of a power supply for supplying power required for a plurality of loads. The device includes N power lines (N is a self-reduced number greater than 2), a power supply, and a power control circuit. The first clause is called at least the power line between the power lines, where 〇 <I<N. The power supply is used to supply the i-th power supply line - the first power supply level - sub-supply the nth power supply line - the second power supply potential. The power control circuit is connected to all the Wei lines, _Wei/ provides the load current between the Wth line and the Jth line, and the Jth line and the J+1th line. The difference is the voltage of each electric _ _ in the design value 'where J is a natural number and 1 < j < N. The present invention proposes a method of power supply for supplying power required for a plurality of loads. The method includes providing a power supply line, wherein the first power line and the 1+1 power line are coupled to at least one load, where I is natural and G<I<N. Supply the first power cord - the first power supply potential, and supply the Nth power supply line to a second power supply potential. Absorbing/providing the load current of the wth line, the line and the first power line, and the difference between the load current between the first power line and the J+1 power line maintains the voltage of each power line In the calculation, where N and j are natural numbers, N is greater than 2 and 1 < J < N. According to the method of power supply according to the preferred embodiment of the present invention, the load current between the ji power line and the jth power line and the Jth power line are absorbed/provided by the above 6 200814485^doc/006 The difference between the load current and the J+1 power supply line includes: · When the load current between the J-1th power supply line and the Jth power supply line is greater than the Jth power supply line and the J+1th The load current between the power lines absorbs the difference between the two load currents. When the load current between the first power supply line and the Jth power supply line is less than the load current between the Jth power supply line and the 1 power supply line, the difference between the two load currents is supplied to the Jth power supply line so that each The power line voltage is maintained at the design value. The present invention reduces power consumption by using a proper series connection of loads in the circuit to reduce the power supply output current, so that in addition to the power required to supply a plurality of loads, power consumption can be reduced. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] FIG. 2 is a circuit diagram of a device for supplying power according to an embodiment of the present invention. Please refer to FIG. 2 first. FIG. 2 includes a first load 200, a second load 2〇2, a third load 204, a fourth load 2〇6, a first power line 2〇8, a second power line ^, and a third Power line 212, power control circuit 214, and power supply 216. The power supply 216 supplies a first power supply potential (here, for example, a high potential VDD) to the first power line 2〇8. The power supply 216 supplies a second power supply potential (here, for example, a low potential VSS) to the third power supply line 212. The first load 200 and the second load 202 are coupled between the first power line 208 and the second power line 210. The third load 204 and the fourth load 2〇6 are coupled between the second power source 7 200814485—the line 210 and the third power line 212. The first power line 208, the second power line 210 and the third power line 212 are evenly connected to the power control circuit 214. The following assumptions have been made in the present embodiment, but the present invention is not limited thereto. First, assume that VDD is 5V and VSS is ground 〇v. In addition, it is assumed that the power supply voltage design values of the first load 200, the second load 202, the third load 204, and the fourth load 206 are 2·5 V (so-called power supply voltage design value of the load circuit, which is well known to those skilled in the art) It is known that there will be different design values depending on the circuit, which will be described in the following embodiments). The current required for the first load 2〇〇 is defined as the first current η, and the current required for the second load 202 is defined as the second current 12, and the current required for the third load 2〇4 is defined as the third current 13, The current required for the four loads 206 is defined as the fourth current 14. Further, it is assumed that the power supply control circuit 214 is used to clamp the voltage on the second power supply line 210 to maintain the voltage level of the second power supply line 21 at 2.5V. First, the power supply 216 supplies a voltage of 5 V to the first power supply line 2〇8' and supplies a voltage of *〇V to the second power supply line 212. When designing this circuit, it is contemplated that the first current II plus the second current 12 approximates the third current 13 plus the fourth current 14. If ideally, the first current n plus the second current 12 is equal to the third current 13 plus the fourth current 14. However, the above example is a special example. In general, the designer can only try to make the first current II plus the second current 12 approximate the third current 13^the = current 14. If the first current 11 plus the second current 12 is greater than the first electric/current 13 plus the fourth current 14, the power control circuit 2ι4 absorbs 8 200814485f d〇c/〇°6 I1+I2_(I3+M) The current difference is introduced to the third power line and the voltage on the second power line 210 is maintained at 2.5 ν. If the first current II plus the second current 12 is slightly smaller than the third current 13 plus the fourth current 14, the power control circuit 214 facilitates the supply of the current difference Ι3+Ι4_(Ι1+Ι2) to the second by the power supply 216. Power line 210. However, this technology does not necessarily require the same power supply voltage required for the load to be implemented. For example, the power supply voltage design value of the first load 2〇〇 and the second load 2〇2 is 2·2V, and the power supply voltage design value of the third load 2〇4 and the fourth load 2〇6 is 2.8V, or The power supply voltage design value of the first load 2〇〇 and the second load 202 is 18¥, and the power supply voltage design value of the third load 2〇4 and the fourth load 206 is 3·2ν. As long as the voltage design value of the load between the first power line 208 and the second power line 210, plus the power supply voltage design value of the load between the second power line 210 and the third power line, the sum of the two is equal to The voltage between a power line 2〇8 and the third power line 212 is controlled by the power control circuit 214, and the circuit can operate normally. - comparing the topology of FIG. 2 with the topology of the conventional figure in the embodiment of the present invention, the total power of FIG. 1 is VDD*(I1+I2+I3+I4), but FIG. 2 of the embodiment The total power is VDD*MAX (I1+I2, I3+I4), so the present invention can greatly reduce the total power. Furthermore, comparing the conventional figure with the power loss in FIG. 2 of the present embodiment, the conventional structure of FIG. 1 has (VDD-V〇ut)*(Il+I2+I3+I4) is a voltage regulator 1〇〇 The power consumption, in Figure 2, the power consumption of the power control circuit 214 is 9 200814485 · secret =; f1 [(I1 + I2Ml3 + I4)] j (assuming the power supply required for the load stupid 02 and the load 204 / 206 Cule is tired of the door, private "M is the necessary power I need the same power." For the conventional figure 1, for Figure 2, if the circuit is designed, it can reduce the power consumption. Integral power __, it is often necessary to integrate multiple supply Γ 电路 中 中 中 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类 类However, the method of knowing is shown in Figure i. For each of the required voltages (Na or, respectively, different voltage regulation benefits are configured, so that the externally supplied power supply voltage (for example, 5 〇v) is stepped down to 3 to 2.0. V纟 These voltage regulation II step-down and supply various internal voltages in the overshoot will generate a lot of power loss and reduce the circuit efficiency. However, using the technology of the invention, the load of the integrated electricity is connected in series to eliminate the voltage regulation. In addition, the power loss can be reduced. Furthermore, the conventional architecture uses a voltage regulator. Since the power regulator needs to supply a large current, it has the potential to occupy a large area of the wafer. If the power supply of the embodiment of the present invention is used. The control circuit, the current supply current is only the current difference. Compared with the conventional high current, the embodiment of the invention only needs to supply a small current. If the invention is applied to the integrated circuit, the layout space of the wafer is inevitably reduced, and thus Figure 3 is a circuit diagram of a power supply device according to another embodiment of the present invention. Please refer to Figure 3. The circuit includes a first load 300, a second load 3, and a second The three loads 304, the fourth load 306, the fifth load 308, the first power line 31, the second power line 312, the third power line 314, the fourth power line 316, the power supply 200814485, the control 318, and the power supply 32. The power supply 32 〇 supplies a first power supply potential (for example, a high potential VDD) to the first power line 31 〇. The power supply § should supply a second power supply potential (eg, a low potential vss) to the fourth power supply. The first load 300 and the second load 3〇2 are coupled between the first power line 310 and the second power line 312. The third load 〇4 and the fourth load 306 are coupled to the second power line 312. The third load 308 is coupled between the third power line 314 and the fourth power line 316. The first power line 310, the second power line 312, the third power line 314, and the fourth The power line 316 is connected to the power control circuit ΜΑ. Similarly, for the convenience of description, the following assumptions are made in this embodiment, but the invention is not limited thereto. First, assume that VDD is 5V and vss is ground 〇V. , assuming a first load 3 〇〇 and a second load 3 〇 2 power supply voltage The value is 2.0 V. The power supply voltage design value of the third load 3〇4 and the fourth load 3〇6 is h8v. The power supply voltage of the fifth load pass is designed to be 1.2V. The first current II is defined as the second current 302. The current required for the third load 304 is defined as the third current 13. The current required for the fourth load is defined as the fourth current. 14. The current required by the fifth load is defined as the fifth current 15. It is further assumed that the power control circuit 318 is used to clamp the voltage on the third power line 314 to stabilize the voltage on the second power line 312. At 3 swims, the voltage on the third power line 314 is stable at 1.2V. First, the power supply 32() supplies the voltage to the first power supply line 11 200814485f.d〇 c/006 31〇, and supplies the ον voltage to the fourth power supply line 316. If ideally, a current π plus a second current 12 is equal to the third current 13 and a fourth current 14, and the third current 13 plus the fourth current 14 is equal to the fifth current 15 〇 However, the circuit design It is not always possible to design an ideal situation. In general, the designer may only try to maximize the first current n plus the second current 12 to be similar to the third current 13 plus the fourth current 14. If the first current n plus the second current 12 is slightly larger than the third current 13 plus the fourth current 14, the power control circuit 318 absorbs the current difference of I1+I2_(I3+I4), so that the second power line 312 The voltage on it is maintained at 3 〇v. If the first current n plus the second current 乜 is slightly smaller than the third current 13 plus the fourth current 14, the crane (four) circuit 'calls, supplies 13+14-(11+12) current difference to the second power line 312 The voltage on the second power line 312 is maintained at 3.0V. Similarly, when the third current 13 plus the fourth current 14 is slightly larger than the fifth power "IL15k', the power control circuit 318 absorbs the current difference of I3+I4-I5, so that the voltage on the third power line 314 is maintained at 1.2V. When the third current 13 plus the fourth current 14 is slightly smaller than the fifth current; [5, the power control circuit supplies a current difference of 15-(13+14), so that the voltage on the third power line 314 is maintained at 1.2V. . From the above two embodiments, it will be readily apparent to those skilled in the art that the present invention can be implemented, for example, in the manner of Figure 4. VXdd and VSS are supplied from the power supply to the upper and lower power lines 404. The power control circuit 4 turns the N power lines 404. At least one load 4〇2 is coupled between adjacent power lines. 12 200814485 - The principle is the same as the above embodiment, so it is not mentioned. According to the above embodiment, the present invention proposes a method of power supply. The piano 5 is a flowchart of a method for power supply according to an embodiment of the present invention, please refer to FIG. 5. First, N power supply lines are provided, wherein at least one load is coupled between the first power supply line and the 1+1th power supply line (step 5〇1). Supply Article 1
電源線第一電源電位(如上面實施例的VDD)，並供應第N 條電源線第二電源電位（如上面實施例的vss)(步驟 503)。吸收/提供第j-i條電源線與第j條電源線之間的負 載私流以及弟J條電源線與第j+1條電源線之間的負載電 ml之差值，其中，n、I、J為自然數且N大於2(步驟5〇5)。 其中，步驟505包括下面幾個子步驟。首先，判斷第 j-i條電源線與第j條電源線之間的貞載電流大於或小於第 J條電源線與第！+1條電麟之_貞载電流(步驟515)。 當判斷為大於時，吸收此兩負載電流之差值（步驟525)。 =判斷為小辦’供應此兩負載電流之差值至第^條電源 線(步驟535)。 、、’’τ'上所述’本發明因制在電路中整合多個供應電壓 、:：巧’因此除了可以供應多個負載所需的電力外 ，還可 以減少電力消耗。 pf本發日犯崎佳實施例揭露如上，然其並非用以 二鬥t明’任何热習此技藝者，在不脫離本發明之精神 範：後之更動翻飾，因此本發明之保護 【圖；=】申请專利範圍所界定者為準。 13 200814485fd〇c/〇°6 圖 塊圖 塊圖 圖1繪示為習知積體電路電源配置電路方塊圖。 圖2繪示為本發明一實施例電源供應之裝置電路方塊 圖3繪示為本發明另一實施例電源供應之裝置電路方 〇 圖4繪不為本發明再一實施例電源供應之裝置電路方 圖5繪示為本發明一實施例電源供應之方法流程 圖 【主要元件符號說明】 100 電壓調節器 102 第一負載區塊 104 第二負載區塊 106 第三負載區塊 108 第四負載區塊 11 ： 第一電流 12 : 第二電流 13 ： 第三電流 14 ： 第四電流 15 ： 第五電流 200 、300 :第一負載 202 、302 :第二負載 204 、304 ·•第三負載 206 、306 ··第四負載 14 200814485fd〇c/〇°6 208、310 :第一電源線 210、312 :第二電源線 212、314 :第三電源線 214、318、400 :電源控制電路 216、320、410 :電源供應器 308 :第五負載 316 :第四電源線 404 : N條電源線 402 :多個負載 501〜535 :本發明實施例之步驟 15The power supply line has a first power supply potential (such as VDD of the above embodiment) and supplies a second power supply line second power supply potential (such as vss of the above embodiment) (step 503). Absorbing/providing the difference between the load private flow between the ji power cable and the j power cable and the load power ml between the J power cable and the j+1 power cable, where n, I, J is a natural number and N is greater than 2 (step 5〇5). Wherein, step 505 includes the following sub-steps. First, determine that the load current between the j-i power line and the jth power line is greater than or less than the Jth power line and the first! +1 电 之 贞 贞 current (step 515). When it is determined to be greater than, the difference between the two load currents is absorbed (step 525). = It is judged that the small office supplies the difference between the two load currents to the second power supply line (step 535). The present invention is based on the fact that the present invention integrates a plurality of supply voltages in a circuit, so that power consumption can be reduced in addition to the power required to supply a plurality of loads. The pf is issued as above, but it is not used for the purpose of any enthusiasm of the artist, without departing from the spirit of the invention: after the change, the protection of the present invention Figure; =] The scope of the patent application is subject to change. 13 200814485fd〇c/〇°6 Block Diagram Block Diagram Figure 1 shows a block diagram of a conventional integrated circuit power supply configuration circuit. 2 is a block diagram of a power supply device according to another embodiment of the present invention. FIG. 3 is a circuit diagram of a power supply device according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a power supply device according to still another embodiment of the present invention. FIG. 5 is a flow chart of a method for supplying power according to an embodiment of the present invention. [Main component symbol description] 100 voltage regulator 102 first load block 104 second load block 106 third load block 108 fourth load region Block 11: first current 12: second current 13: third current 14: fourth current 15: fifth current 200, 300: first load 202, 302: second load 204, 304 · third load 206, 306 ··4th load 14 200814485fd〇c/〇°6 208, 310: first power lines 210, 312: second power lines 212, 314: third power lines 214, 318, 400: power control circuits 216, 320 410: power supply 308: fifth load 316: fourth power supply line 404: N power supply lines 402: multiple loads 501 to 535: step 15 of the embodiment of the present invention