l8832twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製程，且特別是 有關於一種線路基板及其鍍通孔(plating ttlr〇ugh h〇le，pTH) 的製造方法。 【先前技術】 覆晶技術由於具有縮小晶片封裝面積及縮短訊號傳 輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如 晶片尺寸構裝(Chip Scale Package, CSP)、晶片直接貼附封 裝（Direct Chip Attached，DCA)以及多晶片模組封裝 (Multi-Chip Module, MCM)等型態的封裝模組，均可以利用 覆晶技術而達到封裝的目的。 在覆晶封裝製程中，由於晶片與線路基板之熱膨脹係 數的差異甚大，因此晶片外圍的凸塊無法與線路基板上對 應的接點形成良好的接合，使得凸塊可能自線路基板上剝 離。另一方面，隨著積體電路之積集度的增加，由於晶片 與線路基板之間的熱膨脹係數不匹配(mismatch)，其所產 生的熱應力（thermal stress)與翹曲(warpage)的現象也日漸 嚴重，其結果將導致晶片與線路基板之間的可靠产 (reliability)下降，並且造成信賴性測試的失敗。 : 上述問題’習知提出了制半導體基材製作線路基板的 程’其中由於半導體基材與晶片的材質接近，因此可^ 效避免熱膨脹係數不匹配所產生的問題。 習知製作此種半導體線路基板時，同樣會先在半導體 18832twf.doc/g 基材'上製作鍍通孔，再於半導體基材的一側陸續沉積多層 線路層與介電層，以完成線路基板的製作。其中，需要注 意的是，由於半導體基材本身具有半導體的特性，因此在 製作鍍通孔時，需要額外在半導體基材與鍍通孔之間形成 一絕緣層。 圖1A至圖1D即繪示習知此種線路基板之鍍通孔的 製作流程。首先，如圖1A與1B所示，提供一半導體基材 110,並且在半導體基材11〇之表面u〇a形成一盲孔122。 接著，如圖1C所示，應用化學氣相沉積法於半導體基材 110之表面110a上以及盲孔122内壁形成一絕緣層124。 然後，如圖1D所示，應用填孔電鍍（viaflllingplating) 的技術在盲孔122内填充導電材料，以形成導電柱 (conductive post) 126。如此，即完成鍍通孔120的製作。 然而，在上述習知的鑛通孔製程中，由於是使用化學 氣相沉積法來製作絕緣層，故存在製程成本昂貴以及製程 效率低落等問題。因此，如何改良習知此種鐘通孔的製程， 以進一步降低製程成本與提高製程效率，乃是此種半導體 線路基板在實際應用與量產上的重要關鍵。 【發明内容】 有鑑於此，本發明之目的之一便是提供一種較為簡 易、快速’且成本較低的鍍通孔的製作方法。 曰 此外，本發明之另一目的是提供一種線路基板，其铲 通孔是採用上述方法製作而成，因此相對具有較低廉之萝 作成本以及較高之生產效率。 ^ 1321595 18832twf.doc/gL8832twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a process thereof, and more particularly to a circuit substrate and a plated through hole thereof (plating ttlr〇ugh h〇le) , pTH) manufacturing method. [Prior Art] Flip chip technology has been widely used in chip packaging fields due to its advantages of shrinking chip package area and shortening signal transmission path, such as chip scale package (CSP), wafer direct attach package (Direct Chip Attached (DCA) and Multi-Chip Module (MCM) package modules can be packaged using flip chip technology. In the flip chip packaging process, since the thermal expansion coefficients of the wafer and the circuit substrate are greatly different, the bumps on the periphery of the wafer cannot form a good bond with the corresponding contacts on the wiring substrate, so that the bumps may be peeled off from the wiring substrate. On the other hand, as the degree of integration of the integrated circuit increases, thermal stress and warpage occur due to mismatch of thermal expansion coefficient between the wafer and the circuit substrate. It is also becoming more and more serious, and as a result, the reliability of the reliability between the wafer and the circuit substrate is lowered, and the reliability test is failed. The above problem has been proposed in the art of fabricating a circuit substrate for a semiconductor substrate. Since the semiconductor substrate is close to the material of the wafer, the problem of mismatch in thermal expansion coefficient can be avoided. When such a semiconductor circuit substrate is conventionally fabricated, a plated through hole is first formed on the semiconductor 18832 twf.doc/g substrate, and a plurality of wiring layers and dielectric layers are successively deposited on one side of the semiconductor substrate to complete the circuit. Fabrication of the substrate. Among them, it is to be noted that since the semiconductor substrate itself has the characteristics of a semiconductor, it is necessary to additionally form an insulating layer between the semiconductor substrate and the plated through hole when the through hole is formed. 1A to 1D are views showing a process of fabricating a plated through hole of such a circuit substrate. First, as shown in Figs. 1A and 1B, a semiconductor substrate 110 is provided, and a blind via 122 is formed on the surface of the semiconductor substrate 11A. Next, as shown in Fig. 1C, an insulating layer 124 is formed on the surface 110a of the semiconductor substrate 110 and the inner wall of the blind via 122 by chemical vapor deposition. Then, as shown in FIG. 1D, a technique of viafllling plating is applied to fill the via holes 122 with a conductive material to form a conductive post 126. Thus, the fabrication of the plated through hole 120 is completed. However, in the above-described conventional mine through hole process, since the insulating layer is formed by chemical vapor deposition, there are problems such as high process cost and low process efficiency. Therefore, how to improve the process of the conventional clock hole to further reduce the process cost and improve the process efficiency is an important key to the practical application and mass production of such a semiconductor circuit substrate. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method for fabricating a plated through hole that is relatively simple, fast, and low in cost. Further, another object of the present invention is to provide a circuit substrate in which the swash hole is formed by the above method, and therefore has a relatively low cost and a high production efficiency. ^ 1321595 18832twf.doc/g
為達上述或疋其他目的’本發明提出一種鍛通孔的製 作方法，其包栝下列步驟。首先’提供一半導體基材’其 中半導體基材具有相對之一第一表面與一第二表面。然 後，於第一表面形成一盲孔。接著，於第一表面塗佈一感 光性絕緣材料，並使感光性絕緣材料填入盲孔。接下來’ 對感光性絕緣材料進行微影製程（Photolithography Process)，以移除盲孔内的部份感光性絕緣材料，並在第 —表面上以及盲孔的内壁上形成一絕緣層。之後，在盲孔 内形成一導電枉’以完成鍍通孔之製作。 在本發明之一實施例中，在移除盲孔内的部份感光性 &緣材料之後’並在形成導電柱之前，更包括對剩餘的感 光性絕緣材料進行固化，以形成絕緣層。 在本發明之-實施例中，形成導電柱的方法包括下列 步驟。首先，在、絕緣層上形成一電鍍種子層。然後In order to achieve the above or other objects, the present invention proposes a method of producing a forged through hole which comprises the following steps. First, a semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface. Then, a blind hole is formed on the first surface. Next, a photosensitive insulating material is applied to the first surface, and the photosensitive insulating material is filled in the blind via. Next, a photolithography process is performed on the photosensitive insulating material to remove a portion of the photosensitive insulating material in the blind via, and an insulating layer is formed on the first surface and the inner wall of the blind via. Thereafter, a conductive 枉' is formed in the blind via to complete the fabrication of the plated via. In one embodiment of the invention, after removing a portion of the photosensitive & edge material in the blind vias' and prior to forming the conductive pillars, the remaining photosensitive insulating material is further cured to form an insulating layer. In an embodiment of the invention, the method of forming a conductive pillar comprises the following steps. First, a plating seed layer is formed on the insulating layer. then
種，上，且圖案化罩幕暴露出盲: =主:之後，移除圖案化罩幕，並移除盲孔以‘ 在本發明之一實施例中 是濺鍍。 形成電錢㈣層的方法例如 是先在電賴子層上全面形成1阻H幕的方法例如 進行微影製程，以形賴案化罩幕。θ ’著再對光阻層 本發明再提ώ-種線路騎 ，、匕栝一+導體基材、 8 I8832twf.doc/g -導電柱以及-絕緣層。導電她置於半導縣材内，而 絕緣層配置於導餘與半導縣材之間，以使導電枉斑半 導體基材電性隔絕，其中絕緣層的材料為—感紐的絕緣 好姐。 在本發明之一實施例中，感光性的絕緣材料例如是有 機材料。 在本發明之一實施例中，半導體基材例如是石夕基板。 一本發明是在半導體基材表面上以及盲孔中塗佈一烕 光性絕緣材料以形成-絕緣詹，取代了習知之應用化學氣 相沉積法於半導絲材表面上以及盲孔⑽成—絕緣層的 方法。相較於習知技術，本發明除了可降低線路基板之製 作成本外，亦可使線路基板之製作更有效率。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【貫施方式】 I圖2A至圖2J繪示為本發明較佳實施例之一種鍍通孔 的製作流程圖。首先，如圖2A所示，提供一半導體基材 210，其中半導體基材21〇具有相對之一第一表面 210a 與 一第=表面210b。舉例來說，半導體基材21〇例如是矽基 =然後’如圖2B所示，於第一表面2i〇a形成一盲孔222, 中盲孔222之形成方式例如是機械鑽孔（Mechanical DriUing)或是雷射燒银（Laser Ablating)。 接著，如圖2C所示，於第一表面21〇a塗佈一感光性 18832twf.doc/g 絕緣射料224，並使感光性絕緣材料224填入盲孔222。如 =後續形成於盲孔222中之導紐226(請參考圖2h)即 # 21() °在本實施例中，感光性的絕 、.彖材料224例如是有機材料。接下來，如圖2〇至圖邛所 二對感光性絕緣材料224進行微影製程，以移除盲孔姐 内的部份感光性絕緣材料224，並在第一表面施以及盲 形成—絕緣層224，。下文將對上述之微影 2考圖2D ’在本實施财之微影製糊如是藉由 對塗佈於第一表面2咖以及填入盲孔奶中之感 =絶緣材料224進行曝光。接著，將光罩25〇上之圖案 ，P於感光性絕緣材料224上（如圖2E所示）。上述之感 緣材料224例如是，型感光材料，其可藉由光化學 ='來=未曝光部分之感光性絕緣材料22知溶於驗性溶 m保《絲分之感紐絕緣材料島。在 'I' 2?4 ' °目；22中未被曝光的部分感光性絕緣材料 a ρ可被移除’而未被移除之部分感紐絕 例如可經由固化以形成絕緣層故，（如圖2F所示）。告献’ 感光性絕緣材料224亦可以是正型感光㈣，田^ 先bi=r光部分之感光性絕緣材料，而保 分之感光性絕緣材料。未被移除 絕緣材料224同樣可經由固化以形成絕緣層224， 承上所述’在盲孔222的内壁上形成絕緣層似，之 1321595 18832twf.doc/g 後’接著本實施例會在盲孔222内形成導電柱η6(請 圖2J) ’以完成鑛通孔之製作。導電柱之製作方法例二 括下列步驟：首先’如圖2G獅，錢緣層似，上开^ -電鑛種子層230，其中在絕緣層224，上形成電 ^, above, and the patterned mask exposes blindness: = Main: Afterwards, the patterned mask is removed and the blind vias are removed to 'spray in one embodiment of the invention. The method of forming the layer of the electric money (four) is, for example, a method of forming a full-resistance H screen on the electric sub-layer first, for example, performing a lithography process to shape the mask. θ ′ and then the photoresist layer. The invention further provides a line ride, a +-+ conductor substrate, an 8 I8832twf.doc/g-conductive pillar, and an insulating layer. Conductively placed in the semi-conducting material, and the insulating layer is placed between the guide and the semi-conducting material to electrically isolate the conductive freckle semiconductor substrate, wherein the material of the insulating layer is the insulating sister of the sense . In an embodiment of the invention, the photosensitive insulating material is, for example, an organic material. In one embodiment of the invention, the semiconductor substrate is, for example, a stone substrate. One invention is to apply a light-emitting insulating material on the surface of a semiconductor substrate and in a blind via to form an insulating material, instead of using conventional chemical vapor deposition on the surface of a semi-conductive wire and blind holes (10). - Method of insulating layer. Compared with the prior art, the present invention can reduce the manufacturing cost of the circuit substrate and make the circuit substrate more efficient. The above and other objects, features and advantages of the present invention will become more <RTIgt; [FIG. 2A to 2J] FIG. 2A to FIG. 2J are flowcharts showing the fabrication of a plated through hole according to a preferred embodiment of the present invention. First, as shown in Fig. 2A, a semiconductor substrate 210 is provided in which a semiconductor substrate 21 has a first surface 210a and a first surface 210b. For example, the semiconductor substrate 21 is, for example, a bismuth base = then 'as shown in FIG. 2B, a blind hole 222 is formed on the first surface 2i 〇a, and the blind hole 222 is formed by mechanical drilling (Mechanical DriUing, for example). ) or Laser Ablating. Next, as shown in Fig. 2C, a photosensitive 18832 twf.doc/g insulating shot 224 is applied to the first surface 21A, and the photosensitive insulating material 224 is filled into the blind via 222. For example, the guide 226 formed in the blind hole 222 (refer to FIG. 2h), that is, #21() ° In the present embodiment, the photosensitive material 224 is, for example, an organic material. Next, the photosensitive insulating material 224 is subjected to a lithography process as shown in FIG. 2A to FIG. 2 to remove a portion of the photosensitive insulating material 224 in the blind hole and is formed on the first surface and blindly formed. Layer 224,. In the following, the above-mentioned lithography 2 is shown in Fig. 2D. The lithography paste in the present embodiment is exposed by the sensation of the insulating material 224 applied to the first surface 2 and filled in the blind hole milk. Next, the pattern of the mask 25 is placed on the photosensitive insulating material 224 (as shown in Fig. 2E). The above-mentioned sensitizing material 224 is, for example, a photosensitive material which can be dissolved in the photosensitive insulating material 22 of the unexposed portion by photochemical = 'to = unexposed portion. A portion of the photosensitive insulating material a ρ that is not exposed in 'I' 2?4'° mesh; 22 can be removed', and the portion that is not removed can be formed, for example, by curing to form an insulating layer. As shown in Figure 2F). The photosensitive insulating material 224 may also be a positive photosensitive (four), a photosensitive insulating material that is bi=r light portion, and a photosensitive insulating material. The unremoved insulating material 224 can also be cured to form the insulating layer 224, which is said to form an insulating layer on the inner wall of the blind via 222, which is 1321595 18832 twf.doc/g followed by a blind hole in this embodiment. A conductive pillar η6 (see FIG. 2J) is formed in 222 to complete the fabrication of the mine through hole. Example 2 of the manufacturing method of the conductive column includes the following steps: First, as shown in Fig. 2G lion, the edge of the money edge is opened, and the electric seed layer 230 is opened, wherein the electric layer is formed on the insulating layer 224.
230的目的是利於後續電鑛製程之進行，而形成^錢種^ 層230的方法例如是應用濺鍍。在絕緣層224，上形成電 種子層230之後，接著如圖2H所示，提供一圖案化罩^ 240於電鍵種子層230上，且圖案化罩幕24〇暴露出盲孔 222内的電鍍種子層230,以利填孔電鍍之技術在盲孔222 中填充導電材料。在本實關巾，勤是先在電鑛種子層 230上全面形成-光阻層（未繪示），接著再對光阻層進^ 微影製程’以形成圖案化罩幕24〇 ’其中微影製程包括類 似前述之曝光和顯影等步辦。 、The purpose of 230 is to facilitate the subsequent electrowinning process, and the method of forming the layer 230 is, for example, application of sputtering. After the electrical seed layer 230 is formed on the insulating layer 224, then as shown in FIG. 2H, a patterned mask 240 is provided on the key seed layer 230, and the patterned mask 24 exposes the electroplated seeds in the blind vias 222. Layer 230 is filled with a conductive material in blind via 222 in a manner that facilitates hole-fill plating. In the actual customs towel, the first is to form a photoresist layer (not shown) on the electric ore seed layer 230, and then to the photoresist layer to form a patterned mask 24'. The lithography process includes steps such as exposure and development as described above. ,
本實施例在電鍍種子層230上形成圖案化罩幕24〇之 後，接著便可藉由填孔電鍍之技術在盲孔222内的電鍍種 子層230上電鍍形成導電柱226(如圖21所示），其中配置 於導電柱226與半導體基材間之絕緣層224,即可使導電柱 226與半導體基材210電性隔絕。接著，如圖2J所示，移 除圖案化罩幕240，並應用蝕刻技術來移除盲孔222以外 的電鍍種子層230與導電柱226’以完成鍍通孔22〇之製 作。當然，在完成上述鍍通孔22〇之製作後，可以依線路 基板之設計再對半導體基材210進行研磨製程，使得位於 半導體基材210中之導電柱226其兩端部均暴露出（如圖 2K所示），以進行後續製程。 1321595 18832twf.doc/g 圖3即繪示為本發明一實施例之線路基板與晶片以及 電路板接合的示；H㈣3可知，本實施狀線路基板 200主要包括上述之半導體基材、一導電柱以及一 絕緣層224’。由上文可知，由於導電柱226配置於半導體 基材210内，且絕緣層224，配置於導電柱226與半導體基 材210之間。因此，導電柱226與半導體基材21〇電性隔 絕。此外’導電柱226可與半導體基材21〇上之疊合層 電性連接，其中疊合層228例如是依序由多個圖案化曰線路 層228a與多個介電層雇交互疊合而成。圖案化線路層 228a的材質例如可以是鈦/銅合金或鈦/銅/鈦合金。 請再參考圖3，本實施例之線路基板200適於與一晶 片300接合，並使晶片3〇〇透過線路基板2⑻電性連接至 外部電路n面，本實刻之線祕板雇亦可在銲 球塾260上形成多個銲球262，並藉由銲球262連接線路 基板200與外部之電路板4〇化線路基板2〇〇與電路板4⑻ 接合後，晶片30〇即可透過線路基板200而與電路板4〇〇 電性連接。 、示上所述，本發明是在半導體基材表面上以及盲孔中 塗佈一感光性絕緣材料，並藉由微影製程以於半導體基材 ，面上及盲孔内壁上形成—絕緣層接著再以電鑛製程於 目孔⑽成-導電柱，以完成鑛通孔之製作。上述 孔的製作妓相較於習知可具有較低之製作成本以及=古 =於此種類型之半導體線路基板在實; 12 丄 18832twf,doc/g 一雖=本發明已以較佳實施例揭露如上，然其並非用以 =本發明，任何熟習此技藝者，在不賴本發明之精神 1°把圍内’當可作些許之更動與潤飾，因此本發明之保護 摩巳圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1D繪示為習知之鍍通孔的製作流程圖。 =至圖2K纟會示為本發明較佳實闕之一種鍍通 孔的製作流程圖。After forming the patterned mask 24 on the plating seed layer 230, the conductive pillar 226 can be formed by electroplating on the plating seed layer 230 in the blind hole 222 by the technique of hole filling plating (as shown in FIG. 21). The insulating layer 226 is electrically isolated from the semiconductor substrate 210 by the insulating layer 224 disposed between the conductive pillar 226 and the semiconductor substrate. Next, as shown in FIG. 2J, the patterned mask 240 is removed and an etching technique is applied to remove the plating seed layer 230 and the conductive pillars 226' other than the blind vias 222 to complete the plating via 22 〇. Of course, after the fabrication of the plated through holes 22 is completed, the semiconductor substrate 210 can be further polished according to the design of the circuit substrate, so that both ends of the conductive pillars 226 located in the semiconductor substrate 210 are exposed (eg, Figure 2K) for subsequent processing. 1321595 18832twf.doc/g FIG. 3 is a view showing a circuit substrate bonded to a wafer and a circuit board according to an embodiment of the present invention; and H(4) 3, the circuit substrate 200 of the present embodiment mainly includes the above-mentioned semiconductor substrate, a conductive pillar, and An insulating layer 224'. As can be seen from the above, since the conductive pillars 226 are disposed in the semiconductor substrate 210 and the insulating layer 224 is disposed between the conductive pillars 226 and the semiconductor substrate 210. Therefore, the conductive post 226 is electrically isolated from the semiconductor substrate 21. In addition, the conductive pillar 226 can be electrically connected to the laminated layer on the semiconductor substrate 21, wherein the laminated layer 228 is sequentially overlapped by a plurality of patterned germanium circuit layers 228a and a plurality of dielectric layers. to make. The material of the patterned wiring layer 228a may be, for example, a titanium/copper alloy or a titanium/copper/titanium alloy. Referring to FIG. 3 again, the circuit substrate 200 of the present embodiment is adapted to be bonded to a wafer 300, and the wafer 3 is electrically connected to the external circuit through the circuit substrate 2 (8). A plurality of solder balls 262 are formed on the solder balls 260, and the circuit board 200 is connected to the external circuit board 4 by solder balls 262, and the circuit board 2 is bonded to the circuit board 4 (8). The substrate 200 is electrically connected to the circuit board 4 . According to the invention, a photosensitive insulating material is coated on the surface of the semiconductor substrate and in the blind via hole, and the insulating layer is formed on the semiconductor substrate, the surface and the inner wall of the blind via by the lithography process. Then, an electro-mine process is performed on the mesh hole (10) to form a conductive column to complete the production of the mine through hole. The fabrication of the above-mentioned holes can be lower than the conventional manufacturing cost and the conventional semiconductor circuit substrate of this type is practical; 12 丄 18832 twf, doc / g - although the present invention has been a preferred embodiment As disclosed above, it is not intended to be used in the present invention, and anyone skilled in the art can make some changes and refinements in the context of the spirit of the present invention. Therefore, the protection of the present invention is considered to be The scope defined in the patent application is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are flowcharts showing the fabrication of a conventional plated through hole. = to Fig. 2K will show a flow chart for the fabrication of a plated through hole according to a preferred embodiment of the present invention.
以及電 圖3繪示為本發明一實施例之線路基板與晶片 路板接合的示意圖。 【主要元件符號說明】 110 :半導體基材 110a :表面 120 :鍍通孔 122 :盲孔And FIG. 3 is a schematic view showing the bonding of the circuit substrate and the wafer board according to an embodiment of the present invention. [Main component symbol description] 110 : Semiconductor substrate 110a : Surface 120 : Plated through hole 122 : Blind hole
124 :絕緣層 126 :導電柱 210 :半導體基材 210a :第一表面 210b :第上表面 220 :鍍通孔 222 :盲孔 224、224a、224b :感光性絕緣材料 224’ ：絕緣層 1321595 18832twf.doc/g 226 :導電柱 228 :疊合層 228a .圖案化線路層 228b :介電層 230 :電鍍種子層 240 :圖案化罩幕 250 :光罩 260 :銲球墊 262 :銲球 14124: insulating layer 126: conductive pillar 210: semiconductor substrate 210a: first surface 210b: upper surface 220: plated through hole 222: blind hole 224, 224a, 224b: photosensitive insulating material 224': insulating layer 1321595 18832twf. Doc/g 226: conductive pillar 228: laminated layer 228a. patterned wiring layer 228b: dielectric layer 230: electroplated seed layer 240: patterned mask 250: reticle 260: solder ball pad 262: solder ball 14