14783twf.doc/c 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件（semic〇nduct〇r device)之結構及其製造方法，且特別是有關於一種液晶顯 示器（liquid crystal display，LCD)之畫素結構(ρ—血⑽㈣ 及其製造方法。 【先前技術】 針對多媒H社會之急速進步’多半受惠於半導體元 件或顯示裝置的親性進步。賴示器而言，陰極射線管 (cathode ray tube，CRT)因具有優異的顯示品質鱼苴經濟 性，-直獨佔近年來的顯示器市場。然而，對於個人在桌 上操作多數終端機/顯示n裝置的環境 點切入’若以節省能_潮流加，測，陰極射線管因空 間利用以及能源消耗上仍存在报多問題，而對沖、薄、 短、小以及低雜功率的需求無法有效提供解^道。因 此’具有高晝質、空間利用效率佳、低消耗功率、碎射 等優越特性之薄膜電晶體液㈣示器⑽n mm如以伽 liquid crystd display，TFT_LCD)已逐漸成為市場之主流。 薄膜電晶體液晶顯示器主要由薄膜電晶體陣列基 板、彩色濾光陣列基板和液晶層所構成， 陣列基板是由多個陣列排列之薄膜電晶體以== 膜電晶體對應配置之晝素電極(pixd細她)所組成。而 溥膜電晶體制來作為液晶顯示單元㈣關元件4外， 1320868 I4783twf,doc/c 為I控制_的晝素單元，通常會經崎描配線(謂line) 與貧料配線(date line)以選取特定之畫素，並藉由提供適 當的操作電愿，以顯示對應此畫素之顯示資料。另外，上 述之畫素電極的部分區域通常會覆蓋於掃描配線或是共用 配線(common line)上，以形成儲存電容。習知技術中，有 一種儲存電容為金屬層-絕緣層-金屬層（metal-insulator-i^etal, MIM)之架構’以下將針對此種架構之儲存電容結 構進行說明。 圖1繪示為習知金屬層_絕緣層-金屬層⑽M)架構之 =存電容的剖面示意圖。請參關i，在習知的畫素結構 ，金屬層-絕緣層-金屬層(MIM)架構之儲存電容 =藉由掃描配線或共用配線1〇〇與其上方之上電極i2〇 口而成。而掃描配線或共用配線1〇〇與上 緣層彼此電性絕緣。此外，晝素電極二= '、濩層130中的開口 132與上電極12〇電性連接。’、曰 〜值得注意岐，在掃描配線4共用配線1⑻之二侧 在有些許微粒(Particle)5〇。而這些微/粒％容易你 于知描配線或共用配線1〇〇與上電極12〇 使 流的現象，導致儲存電容Cst之電容值降低門存在有漏電 【發明内容】 因此’·本發明的目的就是在提供一種畫 Γίί:知金屬層絕緣層·金屬層(mim)架構之:存:ΐ 令易漏電的缺點，以提高儲存電容值。 仔兒公 6 1320868 14783twf.doc/c 法’其可使畫餘狀齡f構的製造7 本發明的又-目的是提供一種^子電進1提高良率 要係抑制層來防止儲存電容漏電:構’ ^ 其包括—线元件一畫”H電t料素結構， -上電極、—賴層錢—漏^ 間絕緣層、[Technical Field] The present invention relates to a structure of a semiconductor device and a method of fabricating the same, and more particularly to a liquid crystal display (liquid) Crystal display, LCD) pixel structure (ρ-blood (10) (four) and its manufacturing method. [Prior Art] For the rapid advancement of the multimedia H society, most of the benefits of semiconductor components or display devices, the progress of the affinity. In other words, cathode ray tube (CRT) has excellent display quality and economical performance, and it has dominated the display market in recent years. However, for individuals who operate most terminal/display n devices on the table. Cut into 'If you save energy _ current plus, measurement, cathode ray tube still has many problems due to space utilization and energy consumption, and the demand for hedging, thin, short, small and low power can not effectively provide solutions. 'Thin film electro-crystal liquid (4) with high enamel quality, good space utilization efficiency, low power consumption, crushing, etc. (4) n mm such as gamma liquid crystd Display, TFT_LCD has gradually become the mainstream of the market. The thin film transistor liquid crystal display mainly comprises a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer, and the array substrate is a thin film transistor arranged by a plurality of arrays, and the pixel electrode corresponding to the == film transistor is arranged (pixd) Fine her). The tantalum transistor is made as the liquid crystal display unit (4), except for the component 4, 1320868 I4783twf, doc/c is the I control unit of the I control_, usually through the traced wiring (called line) and the poor material wiring (date line) To select a specific pixel and display the corresponding display material of the pixel by providing an appropriate operation. Further, a partial region of the above-described pixel electrode is usually overlaid on a scan wiring or a common line to form a storage capacitor. In the prior art, there is a structure in which the storage capacitor is a metal-insulator-metallization (MIM). The storage capacitor structure of this architecture will be described below. FIG. 1 is a cross-sectional view showing a storage capacitor of a conventional metal layer _ insulating layer-metal layer (10) M). Please refer to i. In the conventional pixel structure, the storage capacitance of the metal layer-insulator-metal layer (MIM) structure is formed by scanning the wiring or the common wiring 1〇〇 with the upper electrode i2. The scanning wiring or the common wiring 1〇〇 and the upper edge layer are electrically insulated from each other. Further, the halogen electrode 2 = ', the opening 132 in the ruthenium layer 130 is electrically connected to the upper electrode 12 。. ‘,曰 ～~ It is worth noting that there are some particles 5 〇 on the two sides of the common wiring 1 (8) of the scanning wiring 4. And these micro/grain% are easy for you to know the phenomenon that the wiring or the common wiring 1〇〇 and the upper electrode 12 are caused to flow, and the capacitance value of the storage capacitor Cst is lowered to cause leakage of the gate. [Invention] Therefore, the present invention The purpose is to provide a kind of drawing Γ ίί: know the metal layer insulation layer · metal layer (mim) structure: save: 令 make the leakage of electricity shortcomings to increase the storage capacitance value.儿公公6 1320868 14783twf.doc/c method 'which can make the production of the remaining age of the structure of the invention 7 - the purpose of the invention is to provide a ^ ^ ^ 1 to improve the yield to suppress the layer to prevent storage capacitor leakage : Construct ' ^ It includes - line component one painting" H electric t material structure, - upper electrode, - Lai layer money - leakage ^ insulation layer,
主動元件電性連接，而下電極係配置“素:素電極係病 此外’閘絕緣層從絲元件延伸至$素：=極的下方。 ，而上電極係配置於閘絕緣層：，且:全：覆! 以覆蓋住上電極之部分區域，而：;:之素電極下方， 於下i極ΐ=:ί=;抑制層的部分區域J 上方之&域’且未完全覆蓋下電極上方 、上述之晝素結構中，保護層中例如具有一 ^£。The active device is electrically connected, and the lower electrode is configured to be "the prime electrode electrode is further connected." The gate insulating layer extends from the wire member to the lower side of the element:= pole. The upper electrode is disposed on the gate insulating layer: Full: Overlay! To cover part of the upper electrode, and below::: the element of the electrode, under the bottom i = ί = ί =; the partial area of the suppression layer J above the & field 'and does not completely cover the lower electrode In the upper and above-mentioned halogen structure, for example, the protective layer has a stamp.
二if出部分上電極’且畫素電極例如係透過第二 上電極電性連接。 乐開口與 ^述之畫素結構中，主動元件例如是—薄膜電晶體。 本發明另提出-種畫素結構的製造方法，其主要勺 ^下列步驟：首先，形成-閘極與—下電極於—基板上^ 垂之’形成-閘絕緣層於基板上㈣絕緣層覆蓋閘極與下 電極。接著，形成-通道層與—漏電流抑制層於閘絕緣層 上丄其中通道層係位於閘極上方，而漏電流抑制層未完全 覆蓋下電極上方之區域。 7 1320868 14783twf.doc/c 上述之畫素結獅製造方_如更包括於基板切 成-源極/祕與-上電極，其中源極/汲極係覆蓋通道層 與部分閘絕緣層，而上電極係覆蓋下電極與漏電流抑^ 層。然後’於基板上形成-保護層，以覆蓋閘絕緣層 電極以及祕級極。接著，於賴層上形成—晝素電極。 上述之晝素結構的製造方法中，漏電流抑制^The second out portion of the upper electrode ' and the pixel electrode are electrically connected, for example, through the second upper electrode. In the structure of the opening and the pixel structure, the active element is, for example, a thin film transistor. The invention further proposes a method for manufacturing a pixel structure, the main steps of which are: firstly, forming a gate electrode and a lower electrode on the substrate to form a gate-insulation layer on the substrate (four) insulating layer covering Gate and lower electrode. Next, a channel-forming layer and a drain current suppressing layer are formed on the gate insulating layer, wherein the channel layer is above the gate, and the leakage current suppressing layer does not completely cover the region above the lower electrode. 7 1320868 14783twf.doc/c The above-mentioned picture lion manufacturing _ is further included in the substrate dicing-source/secret and upper electrode, wherein the source/drainage layer covers the channel layer and part of the gate insulating layer, and The upper electrode covers the lower electrode and the leakage current suppressing layer. Then, a protective layer is formed on the substrate to cover the gate insulating layer electrode and the secret electrode. Next, a halogen electrode is formed on the Lay layer. In the above method for manufacturing a halogen structure, leakage current suppression ^
成^法例如係於下電極二側上方形成二條狀圖案，以^ 覆蓋下電極上方之部分區域。 /、 刀 上述之晝素結構的製造方法中，漏電流抑制 成方法例如係於閘絕緣層上形成—框狀圖案，其中^狀 圖案之-對邊係位於下電極二側上方 上方之部分區域。 7 h〜訂電極 二上述之畫素結構的製造方法巾，於形成畫素電極 刖’例如更包括於保護層中形成—第―開口 分上電極》 恭路出4For example, a two-layer pattern is formed on both sides of the lower electrode to cover a portion of the upper portion of the lower electrode. In the manufacturing method of the above-described halogen structure, the leakage current suppressing method is formed, for example, on a gate insulating layer to form a frame-like pattern, wherein the opposite side of the pattern is located above a portion above the lower side of the lower electrode . 7 h~stamp electrode 2 The manufacturing method of the pixel structure described above is formed in the pixel electrode 刖', for example, further included in the protective layer - the first opening is divided into the upper electrode.
’於形成晝素電極之 二開口，以暴露出部 上述之晝素結構的製造方法中 前，例如更包括於保護層中形成一第 分源極/汲極。 二上述之晝素結構的製造方法中，於形成源極/没極之 月'J，例如更包括於通道層上形成一歐姆接觸層。 —η本發明又提出—種储存電容結構，其包括〜下電極、 你ίΐί二上電極以及一漏電流抑制層。其中，絕緣層 '、復|住下電極，而上電極係配置於絕緣層上。此外，漏 電流抑制層，係配置㈣緣層與上電極之間，而漏電卜^ 14783twf.d〇c/c ::=部分區域係位於下電極上 下電極上方之區域。 匕兑且禾凡全覆蓋 下電極上=;位於下電極二側上方’且分別覆蓋 例如構與儲存電容結構巾，漏電流抑制層 側，L G二此框狀圖案之一對邊係位於下電極二 另復盍下电極上方之部分區域。 如更包括-，雜非 本發明之晝素結構及其製造方法中，揼 、£ +、亡 =置於間絕緣層與上電極之間，：二;= 右:P刀區域係位於下電極上方。藉由此漏電流抑制層可以 欢防止存在於下電極二側之微粒造成此金屬層-絕緣層_ -屬層(MIM)架構之儲存電容漏電，進而提高良率。 為讓本發明之上述和其他目的、特徵和優點能更明 _易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 圖2A係繪示依照本發明一較佳實施例所述之一種晝 素結構的上視圖，而圖3繪示為圖2A中μι，線之剖面圖。 1320868 14783twf.doc/cThe first source/drain is formed in the protective layer before forming the two openings of the halogen electrode to expose the above-described halogen structure. In the above method for fabricating a halogen structure, an ohmic contact layer is formed on the channel layer, for example, on the formation of the source/depolarization. - η The present invention further proposes a storage capacitor structure comprising a lower electrode, an upper electrode, and a leakage current suppressing layer. Wherein, the insulating layer ', the complex|lives the lower electrode, and the upper electrode is disposed on the insulating layer. In addition, the leakage current suppressing layer is disposed between the (four) edge layer and the upper electrode, and the leakage current is 14783twf.d〇c/c:= part of the region is located above the upper electrode of the lower electrode.匕 且 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和Second, the partial area above the lower electrode is retraceed. If it further includes -, the heterogeneous structure of the present invention and the manufacturing method thereof, 揼, £ +, 死 = between the insulating layer and the upper electrode, two: = right: the P-knife region is located at the lower electrode Above. The leakage current suppressing layer can prevent the particles existing on both sides of the lower electrode from causing leakage of the storage capacitor of the metal layer-insulator layer (MIM) structure, thereby improving the yield. The above and other objects, features, and advantages of the present invention will be apparent from the description of the appended claims. 2A is a top view of a bismuth structure according to a preferred embodiment of the present invention, and FIG. 3 is a cross-sectional view of the line ι in FIG. 2A. 1320868 14783twf.doc/c
Cst。於某些情況下，下電極⑽二側通常存在 =料粒50，其容易造成儲存電容Cst漏電。然而， 由於問^緣層24G與上電極25〇之間配置有漏電流抑制層 27 ’其可防止這些微粒5〇造成上電*⑽與下電極23〇 。因此’本實施例之晝素結構雇可以防止儲存 電谷Cst漏電，進而提高液晶顯示器的顯示品質。 佥J f係繪示依照本發明一較佳實施例所述之又-種 2B ’在本發明—較佳實施 _ —旦素結構200之電流抑制層27〇除了如@ 2A所繪 圖案外，電流抑制層270亦可為-框狀圖案， =此=圖案之側邊272、274係位於下電極23〇二側上 刀別覆盍下電極230上方之部分區域。 圖=與圖4Β係緣示依照本發明—較佳實施例所述 另-種旦素結構的上視圖。請參照圖4Α血圖4Β，在 2AH交佳實施例中，儲存電容之下電極，除了為圖 -;B中所繪不之共用配線外，下電極23G亦<為 己線。此外’漏電流抑制層27()例如是二條狀圖# (如圖4A所示）或一框狀圖案(如圖4β所示卜 ^ 5,示為圖2A中⑽，線之剖面圖。請參照圖％ 在本發明一較佳實施例中，主動元件2H)例如是 =膜電晶體，其包括-閘極212、—通道層214以及〆游 汲極216。其中，閘極212係配置於閘絕緣層24〇卞 方’而通道層214係、配置於閉極212上方 曰4〇 上°此外’源極/沒極216係配置於保護層26〇下方，真 11 1320868 14783twf.doc/c 覆蓋通道層214及部分閘絕緣層，其中源極/汲極別 係與畫素電極㈣電性連接。另外，主動元件別例如更 包括一歐姆接觸層218，其配置於通道層m與源極/及 極216之間。 上述之晝素結構200中，保護層26〇係覆蓋源極/汲 極々216以及閘絕緣層24G。此彳，保護層巾例如具有 第一開264，以暴露出部分源極/汲極216，且畫素電 極220例如係透過第二開口 264與源極/沒極216電性連 接。 圖6A至圖6F係繪示依照本發明一較佳實施例所述 之晝素，構的製造方法之步驟流程圖。請參照圖6A至圖 6F ’本只加例之畫素結構的製造方法主要包括下列步驟： 首先，如圖6A所示，形成一閘極212與一下電極23〇於 一基板300上。其中，閘極212與下電極230例如是同時 形成’其形成方法例如是先以濺鍵(sputtering)或物理氣相 沈積(physics vap0r deposition，PVD)在基板 300 上形成一 導體材料層（未繪示再圖案化此導體材料層，以形成 閘極212與下電極23〇。 值得注意的是，在本實施例中下電極230可為掃描 配線或共用配綠。亦即，若欲製作閘極上具有儲存電容(c s t on gate)的晝素結構(如圖4所示），則下電極23〇為掃描配 線°而若欲製作共用配線上具有儲存電容(Cst on common) 的畫素結構(如圖2所示），則下電極230為共用配線。 繼之’如圖6B所示，形成一閘絕緣層240於基板300 12 14783twf.doc/c 上，以覆蓋閘極212與下電極230。其中，閘絕緣層240 的形成方法疋利用化學氣相沈積積法（chemical vapor deposition，CVD)或電漿加強化學氣相沈積（plasma enhanced CVD，PECVD)法，於基板3〇〇上形成一氮化矽 層。 接著，如圖6C所示，形成一通道層214與一非晶矽 層276於閘絕緣層240上’並於通道層214與非晶石夕層276 上分別形成一歐姆接觸層218與一 n型摻雜非晶矽層 278。其中，通道層214係位於閘極212上方，而非晶矽 層276與η型摻雜非晶矽層278係構成一漏電流抑制層 270，此漏電流抑制層270未完全覆蓋下電極23〇上方之 區域。此外，通道層214與非晶矽層276的形成方法，例 如係先於閘絕緣層240上形成一非晶矽材料層（未繪示）， 之後再圖案化此非晶石夕材料層，以形成通道層214與非晶 矽層276。另外，歐姆接觸層218之材質例如是η型摻雜 非晶碎。 在本發明一較佳實施例中，漏電流抑制層270例如 係二條狀，案(如圖2中所示），其位於下電極23()二側， 以分別覆蓋下電極23〇之部分區域。此外，漏電流抑制層 270亦可為一框狀圖案(如圖4中所示），其中此框狀圖案 之對邊272、274係位於下電極230二側，且分別覆蓋 下電極230之部分區域。 之後如圖6D所示，於基板3〇〇上形成一源極/汲 極216與一上電極250，其中源極/汲極216係覆蓋歐姆 J4783twf.doc/c 接觸層218與部分閘絕緣層240，而上電極250係覆蓋下 電極230與漏電流抑制層27卜此外，源極/汲極21^與 上電極250例如係同時形成，其形成方法例如係先以濺鍍 法或物理軋相沈積法在基板3〇〇上形成一導體材料層（未 繪示），再圖案化此導體材料層，以形成源極/汲極216 與上電極250。另外，在圖案化導體材料層時，更包括圖 案化歐姆接觸層218，以於歐姆接觸層218甲形成一開口 218a 〇Cst. In some cases, the two sides of the lower electrode (10) usually have a material particle 50, which is liable to cause leakage of the storage capacitor Cst. However, since the leakage current suppressing layer 27' is disposed between the edge layer 24G and the upper electrode 25A, it can prevent the particles 5' from being electrically charged*(10) and the lower electrode 23''. Therefore, the elemental structure of the present embodiment can prevent the storage of the electricity valley Cst from leaking, thereby improving the display quality of the liquid crystal display.佥J f shows a current suppression layer 27 in accordance with a preferred embodiment of the present invention, in addition to the pattern drawn by @ 2A, in addition to the pattern of the current suppression layer 27 of the present invention. The suppression layer 270 may also be a -frame-like pattern, and the side edges 272, 274 of the pattern = are located on a portion of the lower electrode 23 on both sides of the lower electrode 230. Figure 4 is a top view of the structure of another denier according to the present invention - preferred embodiment. Referring to FIG. 4, in the embodiment of the 2AH, in the embodiment of the 2AH, the lower electrode 23G is also included in the electrode below the storage capacitor except for the common wiring depicted in FIG. Further, the 'leakage current suppressing layer 27 () is, for example, a two-bar graph # (as shown in FIG. 4A) or a frame-like pattern (as shown in FIG. 4β, which is shown as a cross-sectional view of the line in FIG. 2A (10). Referring to Figure % In a preferred embodiment of the invention, active element 2H) is, for example, a = film transistor comprising - gate 212, channel layer 214 and migratory drain 216. The gate 212 is disposed on the gate insulating layer 24 and the channel layer 214 is disposed above the closed electrode 212. Further, the source/dot 216 is disposed under the protective layer 26〇. True 11 1320868 14783twf.doc/c covers the channel layer 214 and part of the gate insulating layer, wherein the source/drain electrodes are electrically connected to the pixel electrode (4). In addition, the active device includes, for example, an ohmic contact layer 218 disposed between the channel layer m and the source/pole 216. In the above-described halogen structure 200, the protective layer 26 is covered with the source/drain electrodes 216 and the gate insulating layer 24G. Thus, the protective cover has, for example, a first opening 264 to expose a portion of the source/drain 216, and the pixel 220 is electrically coupled to the source/drain 216, for example, through the second opening 264. 6A-6F are flow diagrams showing the steps of a method for fabricating a pixel in accordance with a preferred embodiment of the present invention. Referring to FIG. 6A to FIG. 6F, the manufacturing method of the pixel structure of the present invention mainly includes the following steps. First, as shown in FIG. 6A, a gate 212 and a lower electrode 23 are formed on a substrate 300. Wherein, the gate 212 and the lower electrode 230 are simultaneously formed, for example, by forming a conductive material layer on the substrate 300 by sputtering or physical vapor deposition (PVD). The conductive material layer is patterned to form the gate 212 and the lower electrode 23A. It should be noted that in the embodiment, the lower electrode 230 may be a scan wiring or a shared green. That is, if the gate is to be fabricated A memory structure having a storage capacitor (cst on gate) (as shown in FIG. 4), the lower electrode 23 is a scan wiring, and a pixel structure having a storage capacitor (Cst on common) is to be fabricated on the shared wiring (eg, 2, the lower electrode 230 is a common wiring. Next, as shown in FIG. 6B, a gate insulating layer 240 is formed on the substrate 300 12 14783 twf.doc/c to cover the gate 212 and the lower electrode 230. Wherein, the method for forming the gate insulating layer 240 is to form a nitrogen on the substrate 3 by chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD).矽 layer. Next, as 6C, forming a channel layer 214 and an amorphous germanium layer 276 on the gate insulating layer 240 and forming an ohmic contact layer 218 and an n-type doping on the channel layer 214 and the amorphous layer 276, respectively. The germanium layer 278, wherein the channel layer 214 is located above the gate 212, and the amorphous germanium layer 276 and the n-type doped amorphous germanium layer 278 form a leakage current suppressing layer 270, and the leakage current suppressing layer 270 is not completely The region above the lower electrode 23 is covered. Further, the channel layer 214 and the amorphous germanium layer 276 are formed, for example, by forming an amorphous germanium material layer (not shown) on the gate insulating layer 240, and then patterning. The amorphous material layer is formed to form the channel layer 214 and the amorphous germanium layer 276. In addition, the material of the ohmic contact layer 218 is, for example, an n-type doped amorphous chip. In a preferred embodiment of the invention, the leakage current The suppression layer 270 is, for example, in the form of two strips, as shown in FIG. 2, on the two sides of the lower electrode 23 () to cover a portion of the lower electrode 23, respectively. Further, the leakage current suppression layer 270 may also be a a frame pattern (as shown in Figure 4), wherein the opposite sides of the frame pattern 272, 274 are tied On both sides of the lower electrode 230, and respectively covering a partial region of the lower electrode 230. Then, as shown in FIG. 6D, a source/drain 216 and an upper electrode 250 are formed on the substrate 3, wherein the source/drain The 216 series covers the ohmic J4783twf.doc/c contact layer 218 and the partial gate insulating layer 240, and the upper electrode 250 covers the lower electrode 230 and the leakage current suppressing layer 27. Further, the source/drain 21 and the upper electrode 250 are, for example, At the same time, the formation method is, for example, first forming a conductive material layer (not shown) on the substrate 3 by sputtering or physical roll deposition, and then patterning the conductive material layer to form a source/germanium. The pole 216 and the upper electrode 250. In addition, when patterning the conductive material layer, the patterned ohmic contact layer 218 is further included to form an opening 218a in the ohmic contact layer 218.
，後’如圖6E所示，於基板300上形成一保護層26〇， 以覆蓋閘絕緣層24〇、上電極250以及源極/汲極216。其 中，保護層260的形成方法例如係以化學氣相沈積法或電 襞加強化學氣相沈積法於基板上形.氮化石夕層。 接著，如圖6F所示，於保護層26〇上形成一畫素電 極220，以與上電極25〇及源極/汲極216電性連接。而Then, as shown in FIG. 6E, a protective layer 26A is formed on the substrate 300 to cover the gate insulating layer 24A, the upper electrode 250, and the source/drain 216. The method for forming the protective layer 260 is, for example, a chemical vapor deposition method or an electric field enhanced chemical vapor deposition method on the substrate. Next, as shown in FIG. 6F, a pixel electrode 220 is formed on the protective layer 26A to be electrically connected to the upper electrode 25A and the source/drain 216. and
，旦素電極220之材質例如是钢錫氧化物㈣_如 xide，ITO)、銦鋅氧化物(In(Jium 透明導電材質。 他 2注意的是’本發明一實施例中在形成晝素電極 之月”例如更包括於保護層26〇中形成一第一開口 ml露出部分上電極250，而畫素電極220例如係 ^開口 262與上電極250電性連接。此外，於形 ί晝^極220之前’例如更包括於保護層260中形成- 22「:丨L264、，以暴露出部分源極/沒極216 ’而晝素電極 糸透過此第二開口 264與源極/汲極216電性連 14 14783twf.doc/c 接。 綜上所述，本發明之畫素結構及其製造方法至少且 有下列優點： ' 〃 1. 相較於習知技術’本發明之畫素結_具有一漏電 流抑制層’因此可叫善存在於下m之微粒，容易 造成儲存電容漏電的缺點，進而提高晝素結構的良率。 2. 本發明之晝素結構的製造方法與現有製程相容， 不改變製程的情況下’能夠增加晝素結構的良率。 、，然本發明已以較佳實施例揭露如上，然其並非用 以限^本發日月’任何熟習此技藝者，在不脫離本發明之精 神和耗_ ’當可作些許之更動與㈣，因此本發明之保 護範圍當視後附之巾請專利範_界定者為準。 〃 【圖式簡單說明】 圖1繪不為習知金屬層-絕緣層-金屬層(MIM)架構之 儲存電容的剖面示意圖。 圖2A係繪示依照本發明一較佳實施例所述之一種書 素結構的上視圖。 一 圖2B係繪示依照本發明一較佳實施例所述之又一種 畫素結構的上視圖。 圖3、.會示為圖2a中η’線之剖面圖。 囝14圖4B係繪示依照本發明一較佳實施例所述 之另一種畫素結構的上視圖。 圖5繪示為圖2A中ΙΙ-ΙΓ線之剖面圖。 1320868 14783twf.doc/c 圖6A至圖6F係繪示依照本發明一較佳實施例所述 之晝素結構的製造方法之步驟流程圖。 【主要元件符號說明】 _ 50 :微粒 100 :掃描配線或共用配線 • 110、240:閘絕緣層 120、250 :上電極 藝 130、260 :保護層 132、218a :開口 140、220 :晝素電極 • 200:晝素結構 210 :主動元件 212 :閘極 214 :通道層 216 :源極/汲極 218 :歐姆接觸層 # 230 :下電極 262 :第一開口 264 :第二開口 270 :漏電流抑制層 272、274 :側邊 276:非晶矽層 278 : η型摻雜非晶矽層 Cst :儲存電容 16The material of the denier electrode 220 is, for example, steel tin oxide (tetra) (such as xide, ITO), indium zinc oxide (In (Jium transparent conductive material). 2 is noted that in the embodiment of the present invention, a germanium electrode is formed. For example, the first opening 105 is formed in the protective layer 26A to expose a portion of the upper electrode 250, and the pixel electrode 220 is electrically connected to the upper electrode 250, for example, the opening 262. Before 220, it is further included in the protective layer 260 to form - 22 ": 丨 L264, to expose part of the source / no pole 216 ' and the halogen electrode 糸 through the second opening 264 and the source / drain 216 In summary, the pixel structure of the present invention and the method of fabricating the same have at least the following advantages: ' 〃 1. Compared with the prior art, the photographic element of the present invention has A leakage current suppression layer 'is therefore a good particle present in the lower m, which easily causes the leakage of the storage capacitor, thereby improving the yield of the halogen structure. 2. The manufacturing method of the halogen structure of the present invention is compatible with the existing process. , can increase the structure of the alizarin without changing the process The present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the scope of the present invention to anyone skilled in the art, without departing from the spirit and scope of the present invention. Further, and (4), the scope of protection of the present invention is subject to the definition of the patent attached. 〃 [Simple description of the drawing] Figure 1 is not a conventional metal layer - insulating layer - metal layer (MIM) 2A is a top view of a structure of a book according to a preferred embodiment of the present invention. FIG. 2B is a view showing a structure of a book according to a preferred embodiment of the present invention. Figure 3 is a cross-sectional view taken along line η' in Figure 2a. Figure 14B is a diagram showing another pixel structure in accordance with a preferred embodiment of the present invention. Figure 5 is a cross-sectional view of the ΙΙ-ΙΓ line of Figure 2A. 1320868 14783twf.doc/c FIGS. 6A-6F illustrate a method of fabricating a halogen structure according to a preferred embodiment of the present invention. Step flow chart. [Main component symbol description] _ 50 : Particle 100: Scan wiring or total Wiring • 110, 240: Gate insulating layer 120, 250: Upper electrode art 130, 260: Protective layer 132, 218a: Opening 140, 220: Alizarin electrode • 200: Alizarin structure 210: Active element 212: Gate 214: Channel layer 216: source/drain 218: ohmic contact layer #230: lower electrode 262: first opening 264: second opening 270: leakage current suppression layer 272, 274: side 276: amorphous germanium layer 278: η Type doped amorphous germanium layer Cst : storage capacitor 16