CN102566168B - Array substrate, manufacturing method thereof and liquid crystal display device - Google Patents

Abstract

The present invention provides an array substrate and its manufacturing method, and a liquid crystal display device, wherein the array substrate includes a display area and a frame area surrounding the display area, and the display area includes: a plurality of orthogonal and mutually insulated Data lines and scanning lines; the plurality of data lines and scanning lines divide the display area into a plurality of pixel areas arranged in an array, each pixel area includes a pixel electrode, a common electrode, a thin film transistor, and a The first transparent electrode which is on the same potential as the pixel electrode and the second transparent electrode which is arranged on the common electrode and has the same potential as the common electrode; also includes a plurality of scanning connection lines, connecting each corresponding scanning line with the external drive chip electrically connected, the second transparent electrode is also located on the scanning connection line. The invention can save the area of the frame area and improve the utilization rate of the substrate.

Description

Array substrate, manufacturing method thereof, and liquid crystal display device

technical field

The invention relates to a liquid crystal display device, in particular to an array substrate with a narrow frame design for reducing the frame width of a coplanar conversion type liquid crystal display device, a liquid crystal display device and a manufacturing method thereof.

Background technique

Flat-panel displays are currently the most popular displays, among which liquid crystal displays are widely used in electronic products such as computer screens, mobile phones, personal digital assistants, and flat-screen TVs because of their thin and light appearance, power saving, and no radiation.

Fig. 1 is a schematic cross-sectional view of an existing liquid crystal display device. As shown in Fig. 1, a liquid crystal display device generally includes a color filter substrate 1, an array substrate 3 arranged opposite to the color filter substrate 1, and a liquid crystal layer 2 sandwiched between the color filter substrate 1 and the array substrate 3. The array substrate 3 is provided with pixel electrodes and thin film transistors on the inner side relative to the color filter substrate 1, and a common electrode is provided on the array substrate 3 or the color filter substrate 1, and a driving liquid crystal layer is formed between the pixel electrodes and the common electrode. 2, the liquid crystal molecules in 2 turn to the electric field, and the image display can be realized.

According to the different mechanisms of liquid crystal molecules being turned by the electric field, liquid crystal display devices generally include in-plane switching (In-Plane Switching, IPS) and twisted nematic (Twisted Nematic, TN).

FIG. 2 is a schematic cross-sectional structure diagram of a coplanar switching liquid crystal display device in the prior art. As shown in Figure 2, unlike the twisted nematic liquid crystal display device, where the two electrodes are respectively on the upper and lower substrates, and an electric field is formed between the upper and lower substrates, the two electrodes 16A and 16B of the IPS liquid crystal display device are located on the array substrate 14B Above, the color filter substrate 14A is the upper substrate, and the polarizers 10 and 12 are attached to the outer sides of the array substrate 14B and the color filter substrate 14A, respectively. All the liquid crystal molecules are arranged parallel to the array substrate 14B, and the electrodes 16A and 16B are respectively applied with voltage to form an electric field. Under the action of the electric field, the liquid crystal molecules will deflect in a direction parallel to the array substrate 14B. This arrangement greatly improves the performance of the liquid crystal display device. perspective.

FIG. 3 is a schematic top view of a coplanar switching liquid crystal display device in the prior art. The liquid crystal display device includes a display area 20 and a frame area 30 according to functions. The display area 20 includes scan lines and data lines arranged vertically and horizontally, and pixel units defined by them. The frame area 30 includes a plurality of scanning connection lines 21 for connecting with corresponding scanning lines and transmitting the signal of the external driving circuit 40 to the corresponding scanning lines.

The existing technology has the following problems: the frame area 30 is used to accommodate the scanning connection lines 21. With the increasing resolution of liquid crystal display and the miniaturization of liquid crystal display devices, it is necessary to reduce the area of the frame area 30 to improve the utilization rate of the liquid crystal panel. Therefore, there is not enough space in the frame area 30 to accommodate a plurality of scanning connection lines 21 .

How to realize the narrowing of the frame area 30 and improve the utilization rate of the liquid crystal panel has become a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

The technical problem solved by the present invention is to provide an array substrate and its manufacturing method, and a liquid crystal display panel, which reduces the area of the frame area of the array substrate and the liquid crystal display panel, and improves the utilization rate of the array substrate and the liquid crystal display panel.

The array substrate of the coplanar switching liquid crystal display device provided by the present invention includes a display area and a frame area surrounding the display area, and the display area includes:

Multiple orthogonal and mutually insulated data lines and scan lines;

The plurality of data lines and scanning lines divide the display area into a plurality of pixel areas arranged in an array, and each pixel area includes a pixel electrode, a common electrode, a thin film transistor, and also includes a pixel electrode arranged on the pixel electrode and connected to the pixel electrode, etc. The first transparent electrode of the potential and the second transparent electrode arranged on the common electrode and having the same potential as the common electrode;

It also includes a plurality of scanning connection lines for electrically connecting corresponding scanning lines with external drive chips, and the second transparent electrode is also located on the scanning connection lines.

The common electrode overlaps with the pixel electrode to form a storage capacitor.

Optionally, the scanning connection lines are arranged in parallel with the data lines. The scanning connection line and the data line have the same length in the display area. The scanning connection line and the data line are of the same layer of metal. The width of the scanning connection line is smaller than the width of the second transparent electrode above it, and is covered by the second transparent electrode.

The scanning connection line is connected with the scanning line in the display area.

Optionally, an insulating medium layer formed with a via hole is arranged between the scanning connection line and the scanning line, and the scanning connection line is directly connected to the scanning connection line in the via hole.

Optionally, the scanning connection line is indirectly connected to the scanning line through a via hole located thereon and other layer metals located in the via hole.

Optionally, the pixel electrode is divided into a first pixel electrode and a second pixel electrode, and the scanning connection line is located between the first pixel electrode and the second pixel electrode. The common electrode is divided into a first common electrode and a second common electrode, and the first common electrode and the second common electrode are respectively located outside the first pixel electrode and the second pixel electrode.

Optionally, the scanning connection line is located between the pixel electrode and the data line in the adjacent pixel area.

Optionally, the first transparent electrode and the second transparent electrode are made of indium tin oxide or zinc oxide.

Optionally, the common electrodes in adjacent pixel regions in the same row are connected to each other. The common electrode is driven by DC voltage.

The gate of the thin film transistor in each row of pixel area is correspondingly connected to a scanning line; the source of the thin film transistor in each column of pixel area is correspondingly connected to a data line, and the drain is correspondingly electrically connected to the pixel electrode in the pixel area. connect.

The coplanar conversion type liquid crystal display device of the present invention includes a liquid crystal layer and a color filter substrate, and also includes the above-mentioned array substrate, and the liquid crystal layer is located between the array substrate and the color filter substrate.

The present invention also provides a method for manufacturing the above-mentioned array substrate, including:

providing a substrate, the substrate is divided into a display area and a frame area surrounding the display area;

Form a first metal layer in the display area, and use a first mask and a photolithography process to pattern the first metal layer to form a gate of a thin film transistor, a scan line connected to the gate, and a common electrode ;

forming a first insulating dielectric layer;

Using a second mask, etching the first insulating dielectric layer by a photolithography process to form a first via hole, the first via hole exposes the scan line;

Forming an amorphous silicon layer and a doped amorphous silicon layer, and using a third mask and photolithography to etch to form the active layer of the thin film transistor;

Forming a second metal layer, patterning the second metal layer using a fourth mask and a photolithography process to form data lines, pixel electrodes, scanning connection lines and source and drain metals of thin film transistors, the data lines and thin film transistors The source metal connection of the scanning connection line is directly connected to the scanning line in the first via hole;

forming a second insulating dielectric layer, and etching the second insulating dielectric layer by using a fifth mask and a photolithography process to form a second via hole exposing the drain metal of the thin film transistor;

The data line and the scanning line divide the display area into pixel areas arranged in an array, and a first transparent electrode and a second transparent electrode are formed on the surface of the structure, and the first transparent electrode is connected to the thin film transistor in the second via hole. The drain electrode is connected, and the second transparent electrode covers the scanning connection line and the common electrode below it.

Optionally, the forming of the first transparent electrode and the second transparent electrode includes: depositing electrode material on the surface of the second insulating medium layer, and simultaneously forming the second transparent electrode in the pixel region by using a sixth mask and a photolithography process. A transparent electrode and a second transparent electrode. The electrode material is indium tin oxide or zinc oxide.

Compared with the prior art, the present invention has the following advantages: the scanning connection line is arranged in the display area, overlaps with the second transparent electrode, and the second transparent electrode and the common electrode are at the same potential, and the scanning driving circuit signal is transmitted by the scanning connection line. Transmission to corresponding scanning lines saves the area of the frame area without affecting the aperture ratio of the display area and improves the utilization rate of the substrate.

Further optimally, the scanning connection line and the data line are made of the same layer of metal, which is easy to manufacture; and does not occupy the pixel area, so the aperture ratio of the display area will not be affected.

In addition, the common electrode can be driven by direct current during the working process of the liquid crystal display device, so as to avoid disturbing the voltage of the scanning line or the scanning connection line.

Description of drawings

FIG. 1 is a schematic cross-sectional view of an existing liquid crystal display panel;

2 is a schematic cross-sectional view of an existing coplanar switching liquid crystal display device;

FIG. 3 is a schematic top view of an existing coplanar switching liquid crystal display device;

4 is a schematic top view of the structure of the array substrate according to the first embodiment of the present invention;

Fig. 5 is a schematic cross-sectional structure diagram of the array substrate shown in Fig. 4 along the line A-B;

6 to 17 are schematic cross-sectional views of each step of the manufacturing method of the first embodiment;

6a to 17a are schematic top views of some steps of the manufacturing method of the first embodiment;

18 is a schematic top view of the structure of the array substrate according to the second embodiment of the present invention;

FIG. 19 is a schematic cross-sectional structure diagram of the array substrate shown in FIG. 18 along line C-C;

20 to 23 are schematic cross-sectional views of some steps of the manufacturing method of the second embodiment;

FIG. 24 is a schematic top view of the array substrate according to the third embodiment of the present invention.

Detailed ways

The technical solutions of the present invention will be described in detail below in conjunction with specific embodiments.

first embodiment

Referring to FIG. 4 , it is a schematic top view structure diagram of the array substrate according to the first embodiment of the present invention.

The array substrate is divided into a display area and a frame area surrounding the display area. To simplify the illustration, FIG. 4 only shows a schematic top view of a part of the display area. The display area includes: a glass substrate (not shown in the figure); a plurality of scanning lines on the glass substrate: scanning line 101, scanning line 103, scanning line 105, etc.; a plurality of data lines: data line 102, data Line 104, data line 106, etc., each scan line is orthogonal to the data line and is insulated from each other. The data line and the scan line are made of different layers of metal and are separated by an insulating medium layer. The data line is located above the scan line, and the two will display The area is divided into a plurality of pixel areas arranged in an array, and each pixel area includes a thin film transistor 110, a pixel electrode, and a common electrode, and the common electrode and the scanning line are made of the same layer of metal.

The pixel electrode and the common electrode have an overlapping area to form a storage capacitor 1213, and in the overlapping area, the pixel electrode and the common electrode respectively form two upper and lower plates of the storage capacitor 1213, with an insulating layer interposed therebetween.

Specifically, a loop-shaped area is formed between the pixel electrode and the common electrode, the pixel electrode is divided into a first pixel electrode 1201 and a second pixel electrode 1202, and a first transparent electrode 120 is arranged above the pixel electrode. , the first transparent electrode 120 electrically connects the first pixel electrode 1201 and the second pixel electrode 1202 and the first transparent electrode 120 and the first pixel electrode 1201 and the second pixel electrode 1202 are at the same potential.

The common electrode is also divided into a first common electrode 1301 and a second common electrode 1302, and a second transparent electrode 130 is arranged above the common electrode, and the second transparent electrode 130 combines the first common electrode 1301 and the second common electrode 1301. The common electrode 1302 is electrically connected and the second transparent electrode 130 is at the same potential as the first common electrode 1301 and the second common electrode 1302, and the first common electrode 1301 and the second common electrode 1302 are respectively located at the first pixel electrode 1201 and the second The outside of the second pixel electrode 1202 .

A pixel voltage is applied to the first pixel electrode 1201 and the second pixel electrode 1202, a common voltage is applied to the first common electrode 1301 and the second common electrode 1302, and the first transparent electrode 120 also has a pixel voltage, and the first transparent electrode 120 also has a pixel voltage. The two transparent electrodes 130 also have a common voltage, so that the transverse electric field required for driving the horizontal deflection of liquid crystal molecules can be formed between the first transparent electrode 120 and the second transparent electrode 130 in the pixel area.

The array structure in FIG. 4 has 2 rows and 2 columns, which is only for illustration. Wherein, the gates of the thin film transistors 110 in each row of pixel regions are electrically connected to a scanning line, the sources of the thin film transistors 110 in each column of pixel regions are electrically connected to a data line, and the drains of each thin film transistor 110 are connected through The via hole 121 is electrically connected to the pixel electrode in the pixel area. The specific connection mode is the same as that of the prior art, which is common knowledge of those skilled in the art, and will not be repeated here.

In addition, a plurality of scanning connection lines are also included in the display area: scanning connection lines 202, scanning connection lines 203, etc., and the scanning connection lines electrically connect the scanning lines with an external driving chip (not shown in the figure).

Specifically, in this embodiment, the scanning connection line, the data line, and the pixel electrode are formed by etching the same metal layer, and the material of the metal layer may be aluminum or molybdenum-aluminum alloy. The scanning connection line is located between the first pixel electrode and the second pixel electrode and arranged in parallel with the first pixel electrode and the second pixel electrode. Specifically, referring to FIG. 4 , the scanning connection line 202 is located between the first pixel electrode 1201 and the second pixel electrode 1202 and is arranged in parallel with the first pixel electrode 1201 and the second pixel electrode 1202 .

An insulating layer is also provided above the scanning connection line 202, and a second transparent electrode 130 is provided above the insulating layer, and the second transparent electrode 130, the first common electrode 1301, and the second common electrode 1302 are Equipotentially, the second transparent electrode 130 is between the first pixel electrode 1201 and the second pixel electrode 1202 and forms with it the transverse electric field required for driving the horizontal deflection of the liquid crystal molecules in the coplanar switching liquid crystal display device.

The scanning connection line 202 is located under the second transparent electrode 130 and is electrically insulated therefrom. The scanning connection line 202 has a line width smaller than that of the second transparent electrode 130 so that it is covered by the second transparent electrode 130 . The advantage of such setting is that the transparent electrode 130 can shield the voltage on the scanning connection line 202 from affecting the deflection of the liquid crystal molecules. The scanning connection line 202 is located under the second transparent electrode 130, rather than under the pixel electrode or the first transparent electrode 120, which avoids excessive parasitic capacitance between the scanning connection line and the pixel electrode or the first transparent electrode 120, which affects Display effects such as flickering.

Each scanning connection line is directly connected to the corresponding scanning line through the via hole in the display area: for example, the scanning connection line 202 is connected to the scanning line 101 through the via hole 141 , and the scanning connection line 203 is connected to the scanning line 103 through the via hole 142 .

In order to better illustrate the structure of the above-mentioned via hole, please refer to FIG. 5 , which is a schematic cross-sectional structure diagram of the array substrate shown in FIG. 4 along the line A-B. Since the scan lines are bottom metal, the scan connection lines are located above the scan lines. Taking the via hole 141 as an example, there is an insulating medium layer between the scanning connection line 202 and the scanning line 101 , but at the via hole 141 , the scanning line 101 is exposed at the bottom. When a metal layer is deposited on the surface of the insulating dielectric layer, the metal will fill the via hole 141 . Then the metal layer is patterned to form the scanning connection line 202 , so that the scanning connection line 202 is directly connected to the scanning line 101 in the via hole 141 .

In this embodiment, the scanning connection line located under the second transparent electrode 130 and covered by the second transparent electrode 130 makes the scanning line electrically connected to the external driving chip, thereby transmitting the driving signal of the scanning driving chip to the scanning line. The pixel area of the corresponding row is selected, and the thin film transistor 110 in each pixel area is controlled to be turned on or off.

As a preferred solution, in this embodiment, the scanning connection lines and the data lines are made of the same layer of metal, and are arranged parallel to each other, and can be patterned and fabricated by using the same metal layer, thereby simplifying the structure of the array substrate and reducing the cost of the array substrate. The difficulty of the production process. Further preferably, the lengths of the scanning connection lines and the data lines in the display area can be equal, so that the uniformity of pixel display in the display area can be maintained.

As a preferred solution, in this embodiment, the common electrodes in adjacent pixel regions of each row are also connected to each other. Since the common electrodes in the same row of pixel regions have the same potential during operation, the advantage of this arrangement is that it can simplify the connection of the common electrodes, avoid occupying more area of the display area, and thus increase the aperture ratio. Further, the common electrode can be driven by direct current during the working process of the liquid crystal display device, so as to avoid voltage crosstalk between the common electrode and the scanning connection line covered by it.

In order to manufacture the array substrate with the above structure, this embodiment also provides a corresponding manufacturing method. Figures 6 to 17 are schematic cross-sectional views of each step of the manufacturing method described in this embodiment; correspondingly, Figures 6a to 17a are schematic top views of some steps of the manufacturing method, where the section line is A'-B'section Wire. For the convenience of description, only the metal layer is shown in the above schematic top view, and the insulating dielectric structure is omitted. In addition, the following schematic diagrams are not drawn to scale, and the focus is only to illustrate the gist of the manufacturing method of the present invention. For clarity, the dimensions of layers and regions have been exaggerated and the structures have been renumbered.

First, referring to FIG. 6 and its top view shown in FIG. 6 a , a glass substrate 400 is provided. The glass substrate 400 is divided into a display area and a frame area, and the frame area surrounds the display area. To simplify the description, the subsequent figures only show a cross-sectional or top view of the display area.

Referring to FIG. 7, a first metal layer 500 is formed on the surface of the glass substrate 400, and the first metal layer can be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or metal organic compound chemical vapor deposition. (MOCVD) and other methods to form.

Referring to FIG. 8 and its top view shown in FIG. 8a, the first metal layer 500 is patterned using a first mask and a photolithography process to form gates 501 of several thin film transistors, and gates electrically connected to the gates. The scan line 502 and the common electrode 503 as an electrode of the storage capacitor (the other electrode is a pixel electrode). The scanning lines 502 are electrically connected to the gates 501 of the thin film transistors in the pixel area of the same row for selecting the pixels in the row, and the scanning lines 502 are parallel to each other. The storage capacitor is used to store charges, so that when the liquid crystal display device is working, the display of pixels can be maintained between adjacent frames.

Referring to FIG. 9 , a first insulating dielectric layer 600 is formed on the surface of the structure shown in FIG. 8 . The first insulating dielectric layer 600 can be formed by chemical vapor deposition, and the material can be conventional insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride.

Referring to FIG. 10 , the surface of the first insulating dielectric layer 600 is etched using a second mask and photolithography process to form a first via hole 801 . The bottom of the first via hole 801 exposes the scan line 502 . The part of the first insulating dielectric layer 600 located on the surface of the gate 501 can be used as a gate dielectric layer of a thin film transistor.

Referring to FIG. 11, on the basis of the structure shown in FIG. 10, an amorphous silicon layer 601 and a doped amorphous silicon layer 602 are continuously formed, and then the amorphous silicon layer 601 is etched using a third mask and a photolithography process. , The doped amorphous silicon layer 602 forms the island region of the thin film transistor, and at the same time exposes the first via hole 801 and the scan line 502 at the bottom. Among them, the amorphous silicon layer 601 can be used to form the active layer of the thin film transistor, such as the source and drain and the conductive channel between them; and the doped amorphous silicon layer 602 is used to form an ohmic layer with the source and drain. The contact facilitates electrical connection with the subsequently formed data line or pixel electrode.

Referring to FIG. 12, a second metal layer 700 is formed on the basis of the structure shown in FIG. Vapor deposition (MOCVD) and other methods. The second metal layer 700 is filled in the first via hole 801 and directly connected to the scan line 502 .

Referring to FIG. 13 and its top view shown in FIG. 13a, the second metal layer 700 is patterned using a fourth mask and photolithography process to form several data lines 701, scanning connection lines 702, source electrodes 703 and drain electrodes 704, At the same time, a first pixel electrode and a second pixel electrode connected to the drain electrode 704 are also formed.

Wherein, when etching the second metal layer 700, the small island region of the thin film transistor will be over-etched, the doped amorphous silicon layer 602 will be etched and disconnected, and the amorphous silicon layer 601 located therebelow will be exposed, and at the same time A part of the amorphous silicon 601 is also over-etched, so that the source 703 and the drain 704 are insulated from each other.

Each data line 701 is connected to the source 703 of the thin film transistor in the pixel area of the same column. The plurality of data lines 701 and the plurality of scan lines 502 below are perpendicular to each other, forming an orthogonal relationship, that is, each pixel area can be divided.

The scanning connection line 702 is arranged parallel to the data line 701 , and the lengths of the two are equal in the display area. The scanning connection line 702 is directly connected to the corresponding scanning line 502 below it in the first via hole 801 .

Referring to FIG. 14, a second insulating dielectric layer 800 is formed on the surface of the structure shown in FIG. 13. The second insulating dielectric layer 800 can also be formed by chemical vapor deposition, and the material can be silicon nitride, silicon oxide or oxynitride Common insulating materials such as silicon.

Referring to FIG. 15 , the second insulating dielectric layer 800 is etched using a fifth mask and a photolithography process to form a second via hole 802 exposing the drain 704 of the TFT.

Referring to FIG. 16 , an indium tin oxide layer 900 is deposited on the surface of the second insulating dielectric layer 800 . It can be formed by chemical or physical vapor deposition. The above-mentioned ITO layer 900 is also filled in the second via hole 802 and connected to the drain 704 .

Referring to FIG. 17 and its top view 17 a , the indium tin oxide layer 900 is etched using a sixth mask and photolithography process to form a first transparent electrode 901 and a second transparent electrode 902 . The first transparent electrode 901 is directly connected to the drain electrode 704 in the second via hole 802 , and further electrically connected to the first pixel electrode and the second pixel electrode to realize equipotential.

The second transparent electrode 902 and the common electrode 503 are also electrically connected through a via hole (not shown), and the second transparent electrode 902 covers the scanning connection line 702 and its width is larger than that of the scanning connection line 702 line width. The second transparent electrodes 902 in adjacent pixel regions in a row can be connected to each other.

In addition, the material of the above-mentioned first transparent electrode 901 and the second transparent electrode 902 may be Zinc Oxide instead of Indium Tin Oxide. It is only necessary to deposit a zinc oxide layer on the surface of the second insulating dielectric layer 800 to replace the aforementioned indium tin oxide layer 900 .

Through the above manufacturing process, the array substrate described in this embodiment is formed.

second embodiment

In the above embodiments, the scan connection lines are directly connected to the scan lines through via holes in the display area, which is easily limited by wiring during actual manufacturing. As another optional embodiment, the scanning connection line and the scanning line may also be indirectly connected through a via hole located thereon and other layer metals located in the via hole.

Specifically, refer to FIG. 18 , which is a schematic top view structure diagram of the array substrate according to the second embodiment of the present invention. Comparing FIG. 18 with FIG. 4 , it can be seen that the difference between this embodiment and the first embodiment is only that the connection structure between the scanning connection lines is indirectly connected through other metal layers.

In order to better illustrate the connection structure above, please refer to FIG. 19 , which is a schematic cross-sectional structure diagram of the array substrate shown in FIG. 18 along line C-C. Taking the connection structure between the scanning line 101 and the scanning connection line 202 as an example, the connection structure includes a via hole 151 located on the scanning line 101, a via hole 152 located on the scanning connection line 202, and a bridging metal deposited and covering the via hole. Layer 160.

Since the scanning connection line 202 and the scanning line 101 are not located in the same layer of metal, the corresponding scanning line 101 and scanning connection line 202 can be drawn out to the same bridging metal layer 160 through the via hole 151 and the via hole 152 filled with metal. The bridging metal layer 160 covering the via hole electrically connects the scanning connection line 202 to the scanning line 101 . The via hole 151 penetrates between the scanning connection line 202 and the scanning line 101 and the insulating medium layer on the surface of the scanning connecting line 202, while the via hole 152 only penetrates the insulating medium layer on the surface of the scanning connecting line 202, so The bridging metal layer 160 can be separately fabricated on the top of the array substrate. The above-mentioned via holes need to avoid the pixel electrodes and the common electrodes during fabrication, so as not to interfere with the display of the pixels.

In order to manufacture the array substrate of this embodiment, a method for manufacturing the corresponding array substrate is also provided. The only difference between this embodiment and the first embodiment lies in the connection structure between the scanning connection lines and the scanning lines. Therefore, only the formation process of the related connection structure will be described below. Please refer to FIG. 20 to FIG. 23 , which are schematic diagrams of the manufacturing method described in this embodiment. To simplify the description, this embodiment is based on the schematic cross-sectional view of the manufacturing method in the first embodiment.

Firstly, the manufacturing process related to the first via hole in the manufacturing method of the first embodiment is omitted to form the array substrate structure shown in FIG. 20 . As shown in FIG. 20 , different from the first embodiment, the scanning connection line 202 is isolated from the scanning line 101 by the first insulating medium layer 140 , and the two are mutually independent metal layers.

Referring to FIG. 21 , a third insulating dielectric layer 150 is formed on the surface of the structure shown in FIG. 20 . The material of the third insulating dielectric layer 150 may be the same as that of the first insulating dielectric layer 600 and formed by chemical vapor deposition.

Referring to FIG. 22 , align the scanning connection line 702 and the scanning line 502 at the bottom, and use different masks and photolithography processes to etch and form the via hole 151 on the scanning line 101 and the via hole on the scanning connection line 202 respectively. Vias 152 . When forming the above-mentioned via hole, it is necessary to avoid penetrating through the pixel electrode, the common electrode layer and other metal layers.

Referring to FIG. 23, a bridging metal layer 160 is formed on the surface of the third insulating dielectric layer 150, and the bridging metal layer 160 is respectively connected to the scanning line 101 in the via hole 151 and connected to the scanning connection line in the via hole 152. 202 connection. Finally, the connection structure described in this embodiment is formed.

The difference between this embodiment and the first embodiment is that it is no longer necessary to make the first via hole connecting the scanning connection line and the scanning line, and those skilled in the art should easily deduce the specific implementation of the remaining steps according to the solution disclosed in the first embodiment method.

third embodiment

In the above embodiments, the scanning connection lines are located between the first pixel electrode and the second pixel electrode, that is, at the center of the pixel area. As another optional embodiment, the scanning connection lines can also be located in a part of the pixel area. side, and adjacent to the data line of the adjacent pixel area.

FIG. 24 is a schematic top view of the array substrate according to the third embodiment of the present invention. As shown in FIG. 24 and FIG. 4 , the only difference between this embodiment and the first embodiment is that the scanning connection line is located between the pixel electrode and the data line in the adjacent pixel area. Specifically, the scanning connection line 202 is located between the first pixel electrode 1201 and the data line 104, and is located below the second transparent electrode 130 and parallel to the data line 104; the scanning connection line 203 is also located between the first pixel electrode 1201 and the adjacent Between the data lines 106 , under the second transparent electrode 130 and parallel to the data lines 106 .

The structure of this embodiment is similar to that of the first embodiment, only the position of the scanning connection line is changed, so there is no big difference in the forming process, only the layout pattern needs to be changed when the corresponding metal layer is patterned to form the scanning connection line. Those skilled in the art should easily deduce the formation process of this embodiment according to the solution disclosed in the first embodiment.

To sum up, in the array substrate provided by the present invention, the scanning connection line is arranged in the display area, and the scanning line is electrically connected to the external driving chip through the scanning connection line. Since there is no need to arrange scanning connection lines in the frame area, the area of the scanning connection lines in the frame area is reduced, the area of the display area is increased, and the utilization rate of the glass substrate is improved.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (20)

1. An array substrate of a coplanar conversion liquid crystal display device, comprising a display area and a frame area surrounding the display area, wherein the display area includes: Multiple orthogonal and mutually insulated data lines and scan lines; The plurality of data lines and scanning lines divide the display area into a plurality of pixel areas arranged in an array, and each pixel area includes a pixel electrode, a common electrode, a thin film transistor, and also includes a pixel electrode arranged on the pixel electrode and connected to the pixel electrode, etc. The first transparent electrode of the potential and the second transparent electrode arranged on the common electrode and having the same potential as the common electrode; It also includes a plurality of scanning connection lines for electrically connecting corresponding scanning lines with external drive chips, and the second transparent electrode is also located on the scanning connection lines. 2. The array substrate according to claim 1, wherein the common electrode overlaps with the pixel electrode to form a storage capacitor. 3. The array substrate according to claim 1, wherein the scanning connection lines are arranged parallel to the data lines. 4. The array substrate according to claim 3, wherein the scan connection lines and the data lines have the same length in the display area. 5. The array substrate according to claim 1, wherein the scanning connection lines and the data lines are of the same layer of metal. 6 . The array substrate according to claim 1 , wherein the width of the scanning connection line is smaller than the width of the second transparent electrode above it, and is covered by the second transparent electrode. 7. The array substrate according to claim 1, wherein the scanning connection lines are connected to the scanning lines in the display area. 8. The array substrate according to claim 7, wherein an insulating medium layer with a via hole is arranged between the scanning connection line and the scanning line, and the scanning connection line is directly connected to the scanning connection line in the via hole. connect. 9 . The array substrate according to claim 7 , wherein the scanning connection line is indirectly connected to the scanning line through a via hole located thereon and other layer metal located in the via hole. 10. The array substrate according to claim 1, wherein the pixel electrode is divided into a first pixel electrode and a second pixel electrode, and the scanning connection line is located between the first pixel electrode and the second pixel electrode. 11. The array substrate according to claim 10, wherein the common electrode is divided into a first common electrode and a second common electrode, and the first common electrode and the second common electrode are located on the first pixel electrode and the second common electrode respectively. outside of the second pixel electrode. 12. The array substrate according to claim 1, wherein the scanning connection line is located between the pixel electrode and the data line in the adjacent pixel area. 13. The array substrate according to claim 1, wherein the first transparent electrode and the second transparent electrode are made of indium tin oxide or zinc oxide. 14. The array substrate according to claim 1, wherein the common electrodes in adjacent pixel regions in a row are connected to each other. 15. The array substrate according to claim 1, wherein the common electrode is driven by a DC voltage. 16. The array substrate according to claim 1, wherein the gates of the thin film transistors in each row of pixel regions are electrically connected to one scanning line; the sources of the thin film transistors in each column of pixel regions are correspondingly connected to a data line. The drain is electrically connected to the pixel electrode in the pixel region. 17. A coplanar conversion type liquid crystal display device, comprising a liquid crystal layer and a color filter substrate, characterized in that it also includes an array substrate according to any one of claims 1-16, the liquid crystal layer is located between the array substrate and the between color filter substrates. 18. A method for manufacturing an array substrate, comprising: providing a substrate, the substrate is divided into a display area and a frame area surrounding the display area; Form a first metal layer in the display area, and use a first mask and photolithography to pattern the first metal layer to form a gate of a thin film transistor, a scan line connected to the gate, and a common electrode ; forming a first insulating dielectric layer; Using a second mask, etching the first insulating dielectric layer by a photolithography process to form a first via hole, the first via hole exposes the scan line; Forming an amorphous silicon layer and a doped amorphous silicon layer, and using a third mask and photolithography to etch to form the active layer of the thin film transistor; A second metal layer is formed, and the second metal layer is patterned using a fourth mask and a photolithography process to form data lines, pixel electrodes, scanning connection lines, and source and drain metals of thin film transistors, and the data lines and thin film transistors The source metal connection of the scanning connection line is directly connected to the scanning line in the first via hole; forming a second insulating dielectric layer, and etching the second insulating dielectric layer by using a fifth mask and a photolithography process to form a second via hole exposing the drain metal of the thin film transistor; The data line and the scan line divide the display area into pixel areas arranged in an array, and a first transparent electrode and a second transparent electrode are formed on the surface of the structure, and the first transparent electrode is connected to the thin film transistor in the second via hole. The drain electrode is connected, and the second transparent electrode covers the scanning connection line and the common electrode below it. 19. The method for manufacturing an array substrate according to claim 18, wherein said forming the first transparent electrode and the second transparent electrode comprises: depositing electrode material on the surface of the second insulating medium layer, using a sixth process A first transparent electrode and a second transparent electrode are simultaneously formed in the pixel area by a mask and a photolithography process. 20. The manufacturing method of the array substrate according to claim 18, wherein the material of the first transparent electrode and the second transparent electrode is indium tin oxide, or the first transparent electrode and the second transparent electrode are The second transparent electrode material is zinc oxide.