1313901 九、發明說明： 【發明所屬之技術領域】 本發明係為一種形成晶圓導電 指一種應用於無光阻製程之導電凸塊製作之良別係 【先前技術】 現今電子產品在高速處理化、小型化 晶封裝應運而生，其將設置有電子 ，下’覆 置方式安置於基板上，同時*μ 片表面，以倒 板，遂能有效縮小接至基 的能力。 寸並且θ加處理訊號 然而，傳統覆晶封裝之導電凸塊製程中 先於晶圓上形成-光阻層，其可為正光阻或者= =於5前，利用光罩進行曝光顯影製程簡導 電凸塊。頁光製程則衍生種種問題，例如； j 光顯影製程時導電凸塊之氧化 衣矛王中曝 罩層以進行導電凸塊製作需:二:用傳統之圓案化遮 影製程，光阻無法重=要，顯 時，多餘步驟將衍生之諸多製韻式複雜，同 .η, 4 ’製程不穩定使得產 口口％疋性低，產量低，並且成本高昂。 請參考第！圖、其係為習知技術之形成晶圓導電凸 衣程流程圖，以及第2Α圖〜第2Η圖，其係為習 之形成晶圓導電凸;^ -立 ' 10,曰圓意圖’包含：提供一晶圓 ，、有一正面，正面具有複數個金屬鐸墊Η(步 1313901 驟S100)，形成一凸塊下金屬層13(Under Bump Metallurgy，UBM)於晶圓1〇之正面上（步驟sn〇);設置 -圖案化遮罩層20於晶圓1〇之正面，圖案化遮罩層2〇 具有複數個開口，開口係顯露晶圓H)正面上金屬銲墊U 區域二外之凸塊下金屬層13(步驟sl2〇);形成光阻層2ι β aa ® 1 〇 H面’光阻層2}具有複數個開口，以顯露晶 圓正面金屬銲墊U上之凸塊下金屬"（步驟 S130”形成一金屬層3〇於光阻層21開口中與凸塊下金 屬層13上’其係以電鑛方式為之(步驟S140);移除光阻 層21(步驟S150);進行凸塊下金屬層13之钱刻步驟(步驟 S160);以及進行一^γ左日 产 适仃口鲜程序，以形成凸塊31(步驟 S170)。 、然而’習知技術之形成晶圓導電凸塊方法，其光阻 無法重複使用，同時，多餘步驟所衍生之諸多製程問題， ==定:所以如何找出符合製作簡便以及成本低廉 衣/以取代傳統導電凸塊製程中之黃光製盔 疑是業界亟欲解決之問％ π ^ … 時代的變革。之問喊，同時可為導電凸塊製程帶來劃 【發明内容】 有L於此，本發明遂提出一種形成晶圓導電凸 :解==無光阻製程之導電凸塊製作之方法，來 達^决d製程中曝絲影製程時導電凸 題’其係可用简決黃光製程中曝光顯影製程時導 1313901 之氧化問題，以及簡化製程的主要目的。 本發明係為一種形成晶圓導電凸塊之方法，其係應 用於無光阻製程之導電凸塊製作，形成凸塊之方法包含： 提供一晶圓，晶圓具有一正面，正面具有複數個金屬銲 墊，晶圓更包含一晶圓保護層以覆蓋部份金屬銲墊；接著 形成一凸塊下金屬層（Under Bump Metallurgy，UBM)於 晶圓之正面上；接著設置一硬質圖案化遮罩層於晶圓之正 面，硬質圖案化遮罩層具有複數個開口，硬質圖案化遮罩 層開口係顯露金屬銲墊上之凸塊下金屬層；另外，硬質圖 案化遮罩層更包含複數個支撐環，支撐環係配置於晶圓與 硬質圖案化遮罩層之間，並圍繞硬質圖案化遮罩層開口， 且硬質圖案化遮罩層開口之任何一個皆配置一個與其對應 之一支撐環，硬質圖案化遮罩層之材料係包含玻璃，而支 撐環之材料係包含聚合物；再則，設置硬質圖案化遮罩層 之步驟中，更可以包含一對位步驟，以輔助硬質圖案化遮 罩層之精準配置；接著形成一金屬層於硬質圖案化遮罩層 開口中與凸塊下金屬層上；接著移除硬質圖案化遮罩層； 另外，移除硬質圖案化遮罩層步驟，更可以進一步包含一 清洗硬質圖案化遮罩層之步驟；接著進行凸塊下金屬層之 蝕刻步驟；最後，進行一回銲程序，以形成凸塊。 本發明使用硬質圖案化遮罩層以取代傳統導電凸塊 製程中之黃光製程，可以防止於黃光製程衍生之種種問 題，例如；黃光製程中曝光顯影製程時導電凸塊之氧化問 題，其無需使用光阻，更無需顯影製程，且硬質圖案化遮 8 1313901 罩層經清洗後，可供重複使用，製作方法簡便，可省去多 餘的步驟，同時去除該些多餘步驟所衍生之製程問題，其 穩定製程，使得產品穩定性高，並且成本低廉。 有關本發明具體可行之實施方式，茲就配合圖式說 明如下： 【實施方式】 請參考第3圖，第3圖係為本發明之形成晶圓導電 凸塊製程流程圖，其係應用於無光阻製程之導電凸塊製 作，形成凸塊之方法包含： 請參考第4A圖，其係提供一晶圓10，晶圓10具有 一正面，正面具有複數個金屬銲墊11，晶圓10更包含一 晶圓保護層12以覆蓋部份金屬銲墊11(步驟S100)。 請參考第4B圖，其係形成一凸塊下金屬層13(Unde;r Bump Metallurgy , UBM)於晶圓10之正面上；而凸塊下金 屬層13之材料包含銅、鎳、金、銘、欽、I凡、及銀群組 其中之一或群組内之任意組合（步驟S110)。 請參考第4C圖〜第4D圖，其係設置一硬質圖案化遮 罩層22於晶圓10之正面，硬質圖案化遮罩層22具有複 數個開口，開口係顯露金屬銲墊11上之凸塊下金屬層 13 ;另外，硬質圖案化遮罩層22更包含複數個支撐環 23，支撐環23係配置於晶圓10與硬質圖案化遮罩層22 之間，並圍繞開口，且開口之任何一個皆配置一個與其對 應之一支撐環23，硬質圖案化遮罩層22之材料係包含玻 9 1313901 璃，而支撐環23之材料係包含聚合物，晶圓10表面具有 晶圓保護層12,晶圓10表面之晶圓保護層12位於硬質 圖案化遮罩層22與晶圓10之間（步驟S121)。 請參考第4D圖，其係設置硬質圖案化遮罩層22之 步驟中，更可以包含一對位步驟，以輔助硬質圖案化遮罩 層22之精準配置（步驟S131)。 請參考第4E圖，其係形成一金屬層30於硬質圖案 化遮罩層22之開口中與凸塊下金屬層13上，其係以電鍍 方式為之；而於硬質圖案化遮罩層22之開口中形成之金 屬層3 0材料係為無錯材料或有船材料（步驟S141)。 請參考第4F圖，其係移除硬質圖案化遮罩層22 ;另 外，移除硬質圖案化遮罩層22步驟，更可以進一步包含 一清洗硬質圖案化遮罩層22之步驟（步驟S151)。 請參考第4G圖，其係進行凸塊下金屬層14之蝕刻 步驟；而凸塊下金屬層14之蝕刻步驟係為乾式蝕刻或濕 式蝕刻（步驟S160)。 最後請參考第4H圖，其係進行一回銲程序，以形成 凸塊31(步驟S170)。 綜上所述，本發明之形成晶圓導電凸塊製作方法， 可以防止於黃光製程衍生之種種問題，例如；黃光製程中 曝光顯影製程時導電凸塊之氧化問題，其無需使用光阻， 製作方法簡便，其穩定製程，相對使得產品穩定性高，而 且成本低廉。 然而，以上所述僅為本發明其中的較佳實施例而 10 1313901 已，並非用來限定本發明的實施範圍；即凡依本發明申請 專利範圍所作的均等變化與修飾，皆為本發明專利範圍所 涵蓋。 【圖式簡單說明】 第1圖係習知技術之形成晶圓導電凸塊製程流程圖。 第2A圖、第2B圖、第2C圖、第2D圖、第2E圖、 第2F圖、第2(}圖、第2H圖係習知技術之形成 晶圓導電凸塊製程示意圖。 第3圖係本發明之形成晶圓導電凸塊製程流裎圖。 第4A圖、第4B圖、第4C圖、第4D圖、第4E圖、 第4F圖、第4G圖、第4Ή圖係本發明之形成晶 圓導電凸塊製程示意圖。 【主要元件符號說明】 10 11 12 13 14 20 21 22 23 30 31 晶圓 鲁 金屬銲塾 晶圓保護層 凸塊下金屬層 凸塊下金屬層 圖案化遮罩層 光阻層 硬質圖案化遮罩層 支撐環 金屬層 凸塊 11 1313901 步驟S100 提供一晶圓 步驟S110 形成一凸塊下金屬層（Under Bump Metallurgy， UBM)於晶圓之正面上 步驟S120 設置一圖案化遮罩層於晶圓之正面 步驟S121 設置一硬質圖案化遮罩層於晶圓之正面 步驟S130 形成光阻層於晶圓之正面 步驟S131 進行硬質圖案化遮罩層之對位步驟 步驟S140 形成一金屬層於光阻層開口中與金屬銲墊上 步驟S141 形成一金屬層於硬質圖案化遮罩層開口中與金 屬銲墊上 步驟S150 移除光阻層 步驟S151 移除硬質圖案化遮罩層 步驟S160 進行凸塊下金屬層之蝕刻步驟 步驟S170 進行一回銲程序 121313901 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for forming a wafer to be electrically conductive, which is applied to a non-resistive process. [Prior Art] Today's electronic products are processed at high speed. A small-sized crystal package has emerged, which will be equipped with electrons, placed under the 'overlay' on the substrate, and at the same time, the surface of the *μ sheet can be inverted to reduce the ability to connect to the substrate. Inch and θ plus processing signal However, in the conventional bumper package, the conductive bump process is preceded by forming a photoresist layer on the wafer, which can be positive photoresist or == before 5, using a photomask for exposure and development process Bump. The page light process is subject to various problems, for example; j light development process of the conductive bumps of the oxidized clothing spears exposed layer to make conductive bumps need: 2: using the traditional round shadowing process, the photoresist can not Heavy = want, obvious, extra steps will be derived from a variety of rhyme complex, the same. η, 4 ' process instability makes the mouth of the mouth low, low yield, and high cost. Please refer to the first! The figure is a flow chart of forming a wafer conductive embossing process according to the prior art, and a second drawing to a second drawing, which is a method for forming a wafer conductive convex; ^ -立 '10, 曰 round intention 'include Providing a wafer having a front surface and a plurality of metal crucibles on the front side (step 1339091 step S100), forming an under bump metallurgy 13 (UBM) on the front side of the wafer 1 (step Sn〇); setting-patterning the mask layer 20 on the front side of the wafer 1 , the patterned mask layer 2 〇 has a plurality of openings, the opening reveals the wafer H) the front surface of the metal pad U region 2 convex a lower metal layer 13 (step sl2); a photoresist layer 2ι β aa ® 1 〇H surface 'photoresist layer 2} having a plurality of openings to expose the under bump metal on the front surface of the wafer metal pad U " (Step S130) forming a metal layer 3 in the opening of the photoresist layer 21 and the under bump metal layer 13 'which is electrically ionized (step S140); removing the photoresist layer 21 (step S150) a step of performing the under-bump metal layer 13 (step S160); and performing a gamma-ray production process to form the bump 31 (step S170) However, the conventional technique for forming a wafer bump method cannot be reused, and at the same time, many process problems derived from redundant steps, == fixed: so how to find out that it is easy to manufacture and low cost clothing / In order to replace the traditional conductive bump process, the yellow light helmet is suspected to be the industry's ambiguous solution to the problem of the π ^ ... era. The call is shouting, and at the same time can bring the conductive bump process. [Summary of the invention] Herein, the present invention provides a method for forming a conductive bump of a wafer: a solution of a conductive bump of a solution of no photoresist, to achieve a conductive bump in the process of exposure to the shadow process. The oxidation problem of the lead 133901 during the exposure and development process in the yellow light process, and the main purpose of simplifying the process. The present invention is a method for forming a conductive bump of a wafer, which is applied to the fabrication of a conductive bump without a photoresist process. The bump method comprises: providing a wafer having a front surface and a plurality of metal pads on the front side, the wafer further comprising a wafer protective layer covering a portion of the metal pads; and then forming a bump under The Under Bump Metallurgy (UBM) is on the front side of the wafer; then a hard patterned mask layer is disposed on the front side of the wafer, and the hard patterned mask layer has a plurality of openings, and the hard patterned mask layer is opened. Exposing the under bump metal layer on the metal pad; further, the hard patterned mask layer further includes a plurality of support rings disposed between the wafer and the hard patterned mask layer and surrounding the hard patterned mask a layer opening, and any one of the hard patterned mask layer openings is provided with a support ring corresponding thereto, the material of the hard patterned mask layer comprises glass, and the material of the support ring comprises a polymer; The step of hardly patterning the mask layer may further comprise a pair of steps to assist in the precise configuration of the hard patterned mask layer; then forming a metal layer in the hard patterned mask layer opening and the under bump metal layer And then removing the hard patterned mask layer; further, removing the hard patterned mask layer step, further comprising the step of cleaning the hard patterned mask layer; An etching step of the under bump metal layer is performed; finally, a reflow process is performed to form bumps. The invention uses a hard patterned mask layer to replace the yellow light process in the conventional conductive bump process, and can prevent various problems derived from the yellow light process, for example, the oxidation problem of the conductive bumps during the exposure and development process in the yellow light process, It does not need to use photoresist, no need for development process, and the hard patterned cover 13 1313901 cover layer can be reused after being cleaned, the production method is simple, the unnecessary steps can be omitted, and the process derived from the redundant steps can be removed. The problem, its stable process, makes the product stable and low cost. The embodiments of the present invention are described as follows: [Embodiment] Referring to FIG. 3, FIG. 3 is a flow chart of forming a wafer conductive bump according to the present invention, which is applied to The method for forming the bumps of the photoresist process includes: Referring to FIG. 4A, a wafer 10 having a front surface and a plurality of metal pads 11 on the front surface, the wafer 10 is further provided. A wafer protective layer 12 is included to cover a portion of the metal pads 11 (step S100). Please refer to FIG. 4B, which forms an under bump metallurgy layer 13 (Unde; r Bump Metallurgy, UBM) on the front side of the wafer 10; and the under bump metal layer 13 material comprises copper, nickel, gold, and Any combination of one of the group, the group, the group, and the group of silver (step S110). Please refer to FIG. 4C to FIG. 4D, which are provided with a hard patterned mask layer 22 on the front side of the wafer 10. The hard patterned mask layer 22 has a plurality of openings, and the openings expose the bumps on the metal pads 11. The underlying metal layer 13; further, the hard patterned mask layer 22 further includes a plurality of support rings 23 disposed between the wafer 10 and the hard patterned mask layer 22, surrounding the opening, and opening Either one of them is provided with a support ring 23 corresponding thereto, the material of the hard patterned mask layer 22 comprises glass 9 1313901, and the material of the support ring 23 comprises a polymer, and the surface of the wafer 10 has a wafer protective layer 12 The wafer protective layer 12 on the surface of the wafer 10 is located between the hard patterned mask layer 22 and the wafer 10 (step S121). Referring to FIG. 4D, in the step of providing the hard patterned mask layer 22, a pair of bit steps may be further included to assist the precise configuration of the hard patterned mask layer 22 (step S131). Please refer to FIG. 4E, which forms a metal layer 30 on the opening of the hard patterned mask layer 22 and the under bump metal layer 13, which is electroplated; and the hard patterned mask layer 22 The metal layer 30 material formed in the opening is a non-error material or a ship material (step S141). Please refer to FIG. 4F, which removes the hard patterned mask layer 22; in addition, the step of removing the hard patterned mask layer 22 further includes a step of cleaning the hard patterned mask layer 22 (step S151). . Please refer to FIG. 4G, which is an etching step of the under bump metal layer 14; and the etching step of the under bump metal layer 14 is dry etching or wet etching (step S160). Finally, please refer to Fig. 4H, which performs a reflow process to form bumps 31 (step S170). In summary, the method for fabricating a conductive bump of the present invention can prevent various problems caused by the yellow light process, for example, the oxidation problem of the conductive bump during the exposure and development process in the yellow light process, which does not require the use of a photoresist The production method is simple and convenient, and the stable process thereof is relatively high in product stability and low in cost. However, the above description is only the preferred embodiment of the present invention and 10 1313901 is not intended to limit the scope of the present invention; that is, the equivalent variations and modifications made by the scope of the present invention are the invention patents. Covered by the scope. [Simplified Schematic Description] Fig. 1 is a flow chart of a process for forming a wafer conductive bump by a conventional technique. 2A, 2B, 2C, 2D, 2E, 2F, 2(}, and 2H are conventional schematic diagrams for forming a wafer conductive bump. Fig. 3 The flow chart of forming a wafer conductive bump of the present invention. The 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4th drawings are the present invention. Schematic diagram of the process of forming a conductive bump of a wafer. [Description of main component symbols] 10 11 12 13 14 20 21 22 23 30 31 Wafer metal foil soldering wafer protective layer under bump metal layer under bump metal layer patterned mask Layer photoresist layer hard patterned mask layer support ring metal layer bump 11 1313901 Step S100 provides a wafer step S110 to form an under bump metallurgy (UBM) on the front side of the wafer, step S120 is set The patterned mask layer is disposed on the front surface of the wafer. Step S121 is provided with a hard patterned mask layer on the front side of the wafer. Step S130: Forming a photoresist layer on the front side of the wafer. Step S131: Performing a step of the hard patterned mask layer. S140 forms a metal layer in the opening of the photoresist layer and the metal Step S141 on the solder pad forms a metal layer in the opening of the hard patterned mask layer and the metal pad. Step S150: Removing the photoresist layer. Step S151. Removing the hard patterned mask layer. Step S160: Step of etching the under bump metal layer. S170 performs a reflow procedure 12