1375501 VIT09-0001ΪΟΟ-TW 30369twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明疋有關於-種線路板及其製作方法及其晶片 封裝結構，且制是有關於—種凸制練小的線路板及 其製作方法及其晶片封裝結構。 【先如技術】 水^著積體電路之積集度的增加，晶片的封裝技術也越 二/樣化。由於覆晶接合技術（Flip chip ι愈議⑽t 二n〇1°gy)具有縮小晶#封裝_及_訊號傳輸路徑 荨優點，故目前已廣泛翻於晶片封裝領域。 ，在覆晶接合的製程中，用以接合晶片與晶片載 = 塊在受熱熔融時易受晶片所擠壓而塌陷，以導 率的下降。因此’習知技術提出-種所謂可控塌 ^ Controlled Collapse Chip Connection ^ C4 ) 來克服凸塊塌陷的問題。 的箱：H控顧晶片連接技術是在晶片上形成突出 下二二連^片的婷料凸塊。上述預凸塊的作法如 晶片驗上全面形成—種子層，其覆蓋防焊 ιίίΓΐ開口所暴露出的接塾’並在種子層上形成 於阻層’其中圖案化光阻層的多個開口分別連通 ^曰片^板上的防焊層之用以暴露出接塾的多個開口。麸 二層及電錄方式在防谭層的開口及圖案化光阻 曰的開中填入金屬以形成預凸塊。 1375501 VIT09-0001I00-TW 30369twf.doc/n 由於月j述預凸塊可在覆晶接合的製程中支撐溶融的鲜 料凸塊，故可戦胃知技術愤_銲料凸齡到晶片之 擠壓而塌陷的問題。 然而’在月述製作預凸塊的製程中，由於圖案化光阻 層的開口需與畴層的開口連通且完全暴露出防焊層的開 口 ’故在形成圖案化光阻層的開口時會受到製程上對位精 準度的限制’而使得圖案化光阻層的㈣寬度大於防焊層 的開口寬度。如一此來，不但無法縮小圖案化光阻層的開 口的尺寸，也導致預⑽與銲料凸塊的尺相及凸塊間距 (bump pitch)無法縮小。此外，由於凸塊間距無法縮小， 所以晶片上的晶片接塾間距亦對應無法縮小。 【發明内容】 本發明提供一種線路板的製作方法，可減少線路板上 的預凸塊的間距。 本發明提供一種線路板，其凸塊間距較小。 本發明提供一種晶片封裝結構，其晶片與線路板的接 點密度較高。 本發明提出一種線路板的製作方法如下所述。首先， 提供一基底、至少一頂接墊、至少一底接墊、一頂防焊層 與一底防焊層，其中頂接墊與底接墊分別配置於基底之相 對的一頂面與一底面上，且頂接墊與底接墊電性連接，頂 防4層與底防焊層分別配置於了員面與底面上，頂防焊層具 有一暴露出部分頂接墊的第一開口，底防焊層具有一暴露 5 1375501 VIT09-0001I00-TW 30369twf.doc/n 出部勿底接塾的第一開口。接著，於底面上形成一導電層， 導電層覆蓋底防焊層與底接墊，並與底接墊電性連接。然 後，於導電層上形成一阻鍍層，阻鍍層具有一第三開口， 第三開口暴露出部分導電層。之後，透過第三開口對導電 層施加一電流，以電鍍一預凸塊於頂接墊上。接著，移除 阻鑛層。然後’移除導電層。 卜 本發明更提出-種線路板，其包括—基底、至少一頂 接塾、-頂防焊層、-預凸塊、至少一底接塾以及一底防 焊層。基底具有相對的一頂面與一底面。頂接塾配置於頂 面上。頂防焊層配置於頂面上並覆蓋部分頂接塾，頂防焊 層具有-暴露出部分頂接塾的第一開口。預凸塊配置於頂 接塾上並位於第-開口中，預凸塊具有一突出於頂防谭層 的突出部’突出部的最大寬度小於或等於頂接塾的寬度。 底接塾配餘絲上，並賴至頂料。底防焊^配 置於底面上城蓋部分底雜，餘焊層具有-暴露出部 分底接墊的第二開口。 一曰本發明再提出-種晶片職結構，其包括—線路板、 -晶片以及至少一銲料凸塊。線路板包括一基底、至少一 頂接塾、-頂防焊層、—預凸塊、至少 基底具有相對的—頂面與—底面。頂接墊配置^ 右頂【ί!配置於頂面上並覆蓋部分頂接塾，頂防 谇層，、有一暴疼出部分頂接墊的第一 =上並辑1…制 曰h出部’突出部的最大寬度小於或等於頂接塾的寬 6 V1T09-0001I00-TW 30369twf.doc/n 度。底接墊配置於底面上，並電性連接至頂接墊。底防焊 層配置於底面上並覆蓋部分底接墊，底防焊層具有一暴露 出部分底接墊的第二開口。晶片配置於線路板上，且晶片 上配置有至少一位置對應預凸塊的晶片接墊。銲料凸塊配 置於晶片與線路板之間’以連接預凸塊與晶片接墊。 基於上述，本發明是利用位於基底之相對於設有接墊 的頂面的底面上的導電層作為電鍍種子層以在基底的頂面 的接塾上電鍍形成預凸塊。因此，本發明可避免習知技術 中在晶片載板之頂面上形成圖案化光阻層的開口時受到製 程上對位精準度的限制，而無法縮小圖案化光阻層的開口 的尺寸凸塊尺寸與凸塊間距的問題。如此一'來，本發明 可有效縮小預凸塊的尺寸以及凸塊間距。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例’並配合所附圖式作詳細說明如下。 【實施方式】 圖1A至圖1D繪示本發明一實施例之線路板的製程剖 面圖。首先，請參照圖1A，提供一基底11〇、多個頂接墊 122、多個底接墊124、一頂防焊層132與一底防焊層134。 頂接墊122與底接墊124分別配置於基底11〇之相對的一 頂面112與一底面114上，且頂接墊122與尨接墊124電 性連接。值得注意的是’在圖1A中’為方便說明，僅續 示一頂接墊122與一底接墊124為例。此外，使用「頂」3 與「底」的用語，僅是方便說明，其表示位於基底之相對 13755011375501 VIT09-0001ΪΟΟ-TW 30369twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board, a manufacturing method thereof and a chip package structure thereof, and the system is related to a kind of convex The invention discloses a small circuit board, a manufacturing method thereof and a chip package structure thereof. [First as technology] The increase in the accumulation of water and the integrated circuit, the packaging technology of the wafer is also more diverse. Since the flip chip bonding technology (Flip chip ι (10) t 2 n 〇 1 ° gy) has the advantages of shrinking the crystal package_and__signal transmission path, it has been widely turned into the field of chip packaging. In the process of flip chip bonding, the bonding wafer and the wafer carrier block are easily squeezed by the wafer when heated and melted, and the conductivity is lowered. Therefore, the conventional technique proposes a so-called controlled collapse Collapse Chip Connection ^ C4 to overcome the problem of bump collapse. The box: H control chip connection technology is to form a puncturing bump on the wafer to protrude the next two or two pieces. The pre-bumping method is integrally formed on the wafer as a seed layer, which covers the interface exposed by the solder resist ι Γΐ 并 opening and formed on the seed layer in the resist layer ′ where the plurality of openings of the patterned photoresist layer are respectively The solder resist layer on the board is used to expose the plurality of openings of the interface. The bran two-layer and electro-recording method fills the opening of the anti-tank layer and the opening of the patterned photoresist to form a pre-bump. 1375501 VIT09-0001I00-TW 30369twf.doc/n Since the pre-bump can support the melted fresh material bumps in the process of flip chip bonding, it can be used to know the technical indignation. And the problem of collapse. However, in the process of fabricating the pre-bumps in the month, since the opening of the patterned photoresist layer needs to communicate with the opening of the domain layer and completely expose the opening of the solder resist layer, the opening of the patterned photoresist layer may be formed. The (4) width of the patterned photoresist layer is greater than the opening width of the solder resist layer by the limitation of alignment accuracy on the process. As a result, not only can the size of the opening of the patterned photoresist layer be reduced, but also the scale of the pre-(10) and solder bumps and the bump pitch cannot be reduced. In addition, since the bump pitch cannot be reduced, the wafer pitch on the wafer cannot be reduced. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a circuit board, which can reduce the pitch of pre-bumps on the circuit board. The invention provides a circuit board having a small bump pitch. The present invention provides a chip package structure in which the density of contacts between the wafer and the board is high. The present invention provides a method of fabricating a circuit board as follows. Firstly, a substrate, at least one top pad, at least one bottom pad, a top solder resist layer and a bottom solder resist layer are provided, wherein the top pad and the bottom pad are respectively disposed on an opposite top surface of the substrate and On the bottom surface, the top pad and the bottom pad are electrically connected, and the top protection layer 4 and the bottom solder resist layer are respectively disposed on the surface of the member and the bottom surface, and the top solder resist layer has a first opening exposing a portion of the top pad The bottom solder mask has a first opening that exposes 5 1375501 VIT09-0001I00-TW 30369twf.doc/n. Then, a conductive layer is formed on the bottom surface, and the conductive layer covers the bottom solder resist layer and the bottom pad, and is electrically connected to the bottom pad. Then, a resist layer is formed on the conductive layer, and the resist layer has a third opening, and the third opening exposes a portion of the conductive layer. Thereafter, a current is applied to the conductive layer through the third opening to plate a pre-bump on the pad. Next, remove the barrier layer. Then the conductive layer is removed. The present invention further provides a circuit board comprising a substrate, at least one top via, a top solder resist layer, a pre-bump, at least one bottom tab, and a bottom solder resist. The substrate has a top surface and a bottom surface. The top raft is placed on the top. The top solder resist layer is disposed on the top surface and covers a portion of the top soldering layer, and the top solder resist layer has a first opening that exposes a portion of the top bead. The pre-bumps are disposed on the top cymbal and are located in the first opening, and the pre-bumps have a protrusion portion protruding from the top anti-tamping layer. The maximum width of the protrusion is less than or equal to the width of the top cymbal. The bottom is connected to the balance wire and depends on the top material. The bottom soldering prevention is disposed on the bottom surface of the bottom cover portion, and the residual solder layer has a second opening exposing a portion of the bottom pad. The invention further proposes a wafer structure comprising a circuit board, a wafer and at least one solder bump. The circuit board includes a substrate, at least one top via, a top solder resist layer, a pre-bump, and at least the substrate has opposing top and bottom surfaces. Top pad configuration ^ Right top [ί! Configured on the top surface and covered part of the top 塾, top anti-mite layer, there is a violent part of the top pad of the first = on the series 1 ... system 出 h out 'The maximum width of the protrusion is less than or equal to the width of the top 塾 6 V1T09-0001I00-TW 30369twf.doc/n degrees. The bottom pad is disposed on the bottom surface and electrically connected to the top pad. The bottom solder resist layer is disposed on the bottom surface and covers a portion of the bottom pad, and the bottom solder resist layer has a second opening exposing a portion of the bottom pad. The wafer is disposed on the circuit board, and the wafer is provided with at least one wafer pad corresponding to the pre-bump. Solder bumps are disposed between the wafer and the board to connect the pre-bumps to the wafer pads. Based on the above, the present invention utilizes a conductive layer on the bottom surface of the substrate opposite the top surface on which the pads are provided as a plating seed layer to form a pre-bump on the top surface of the substrate. Therefore, the present invention can avoid the limitation of the alignment accuracy on the process when forming the opening of the patterned photoresist layer on the top surface of the wafer carrier in the prior art, and cannot reduce the size convexity of the opening of the patterned photoresist layer. The problem of block size and bump spacing. In this way, the present invention can effectively reduce the size of the pre-bumps and the pitch of the bumps. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] Figs. 1A to 1D are cross-sectional views showing the process of a circuit board according to an embodiment of the present invention. First, referring to FIG. 1A, a substrate 11A, a plurality of priming pads 122, a plurality of bottom pads 124, a top solder resist layer 132 and a bottom solder resist layer 134 are provided. The top pad 122 and the bottom pad 124 are respectively disposed on a top surface 112 and a bottom surface 114 of the substrate 11 , and the top pad 122 is electrically connected to the pad 124 . It is to be noted that 'in FIG. 1A' is a convenient description, and only one top pad 122 and one bottom pad 124 are exemplified. In addition, the terms "top" 3 and "bottom" are used for convenience only, and the relative position is 1375501.
VlT〇9-〇〇〇lI〇〇-TW 30369twf.doc/n —側，並非空間上的實質限制。 詳細而S，在本實施例中，一頂線路層122&盥— 路層124a分別配置於基底m之頂φ 112與底^ ιΐ4-上， 且頂線路層122a與親路層124a %性連接。部分 路層ma構成頂接墊122，部分的底線路層ma構成底 接塾124。 一VlT〇9-〇〇〇lI〇〇-TW 30369twf.doc/n — side, not a substantial limitation in space. In detail, in this embodiment, a top circuit layer 122 & 盥 - channel layer 124a is respectively disposed on the top φ 112 and the bottom ΐ 4 of the substrate m, and the top circuit layer 122a is connected to the affinitive layer 124a. . Part of the road layer ma constitutes the top pad 122, and part of the bottom circuit layer ma constitutes the bottom pad 124. One
頂防焊層132與底防焊们34分別配置於頂面112盥 底面114上，且頂防焊層132可覆蓋部分頂線路層i22f 底防焊層134可覆蓋部分底線路層124a。頂防焊層具 ^ 一開口 132a’開口 l32a暴露出部分的頂接墊122。底防 焊層134具有一開口 134a，其暴露出部分底接墊124。 接著，凊參照圖1B，在底面114上例如以無電鍍法 (electroless plating)形成一導電層14〇，導電層刚覆蓋底 防焊層134與底接墊124，並與底接墊124電性連接。值 得注意的是，在本實施例中，導電層14〇可同時與多個底 接墊124電性連接。The top solder resist layer 132 and the bottom solder resist 34 are respectively disposed on the top surface 112 of the top surface 112, and the top solder resist layer 132 may cover a portion of the top wiring layer i22f. The bottom solder resist layer 134 may cover a portion of the bottom wiring layer 124a. The top solder mask has an opening 132a' opening l32a exposing a portion of the landing pad 122. The bottom solder resist 134 has an opening 134a that exposes a portion of the bottom pad 124. Next, referring to FIG. 1B, a conductive layer 14 is formed on the bottom surface 114 by, for example, electroless plating. The conductive layer just covers the bottom solder resist layer 134 and the bottom pad 124, and is electrically connected to the bottom pad 124. connection. It should be noted that in this embodiment, the conductive layer 14A can be electrically connected to the plurality of pad pads 124 at the same time.
然後，請再次參照圖1B，於導電層140上形成一阻鍍 層150 ’阻鍍層150具有一開口 152,開口 152暴露出部分 的導電層140。在本實施例中，形成阻鍍層15〇的方法例 如是先在導電層140上全面形成一感光材料層（未繪示）， 然後’再以曝光顯影的方式圖案化感光材料層。 之後，請參照圖1C，透過開口 152對導電層140施加 一電流’以電錄一預凸塊160於頂接墊122上。在本實施 例中’預凸塊160具有一突出於頂防焊層丨32的突出部 1375501 VIT09-0001I00-TW 30369twf.doc/n 162。相對於開口 132a的寬度W2，突出部162的最大寬 度wi可大於或等於開口 132a的寬度W2，即不小於開口 132a的寬度W2。另外，相對於頂接墊122的寬度W3， 突出部162的最大寬度W1可小於或等於頂接墊122的寬 度W3，即不大於頂接墊122的寬度W3。 值得注意的是，矣實施例利用對位於基底11〇之底面 114上的導電層14〇施加電流的方式電鍍形成預凸塊16〇。 因此，本實施例的線路板製作方法可避免習知技術中在晶 片載板之頂面上形成圖案化光阻層的開口時受到製程上對 位精準度的限制，而無法縮小圖案化光阻層的開口的尺 寸、凸塊尺寸與凸塊間距的問題。更詳細的說明是，藉由 本實施例，由於不需預留空間(如先前技術所提及，加大圖 案化光阻層的開口寬度)來完成對位，因此所形成之預凸塊 160的突出部162的最大寬度W1將不會大於頂接墊122 的寬度W3。反觀，若使用習知技術的對位技術來形成預 凸塊時，受限於對位精準度所需的參數設定，所形成之預 凸瑰的最大寬度將會大於頂接墊寬度。如此一來，本實施 例的線路板製作方法可有效縮小預凸塊16〇的尺寸以及凸 塊間距，且以本實施例的線路板製作方法所製得的線路板 可承載晶片接墊間距較小的晶片。 接著，s奮參照圖1D，移除阻鑛層150，然後，移除導 電層140。此時，已初步形成本實施例之線路板1〇〇。 之後，請再次麥照圖1D，在本實施例中，可於預凸塊 160上形成一表面處理層172,並在底接墊124之暴露於開 1375501 VIT09-0001I00-TW 30369twf.doc/n 口 134a外的部分上形成一表面處理層174。在本實施例 中，形成表面處理層172、174的方法例如是一化鎳金製 程、一化鎳鈀製程、一化鈀金製程或一化鎳鈀金製程。 以下將就圖1D中的線路板100的結構部分進行詳細 地介紹。Then, referring again to FIG. 1B, a resist layer 150 is formed on the conductive layer 140. The resist layer 150 has an opening 152, and the opening 152 exposes a portion of the conductive layer 140. In the present embodiment, the method of forming the plating resist 15 is, for example, first forming a photosensitive material layer (not shown) on the conductive layer 140, and then patterning the photosensitive material layer by exposure development. Thereafter, referring to FIG. 1C, a current ' is applied to the conductive layer 140 through the opening 152 to electrically record a pre-bump 160 on the pad 122. In the present embodiment, the pre-bump 160 has a projection 1375501 VIT09-0001I00-TW 30369twf.doc/n 162 which protrudes from the top solder resist layer 32. The maximum width wi of the protrusion 162 may be greater than or equal to the width W2 of the opening 132a with respect to the width W2 of the opening 132a, i.e., not less than the width W2 of the opening 132a. In addition, with respect to the width W3 of the susceptor pad 122, the maximum width W1 of the protrusion 162 may be less than or equal to the width W3 of the susceptor pad 122, i.e., not greater than the width W3 of the susceptor pad 122. It is to be noted that the 矣 embodiment utilizes a manner in which a current is applied to the conductive layer 14 on the bottom surface 114 of the substrate 11 to form a pre-bump 16 电镀. Therefore, the circuit board manufacturing method of the embodiment can avoid the limitation of the alignment accuracy on the process when forming the opening of the patterned photoresist layer on the top surface of the wafer carrier in the prior art, and cannot reduce the patterned photoresist. The size of the opening of the layer, the size of the bumps, and the problem of the pitch of the bumps. In more detail, with the present embodiment, since the alignment is not required (as mentioned in the prior art, the opening width of the patterned photoresist layer is increased), the alignment is performed, and thus the pre-bump 160 is formed. The maximum width W1 of the protrusion 162 will not be greater than the width W3 of the top pad 122. In contrast, if the prior art alignment technique is used to form the pre-bumps, the maximum width of the pre-curvature formed will be greater than the width of the padding pad, limited by the parameter settings required for alignment accuracy. In this way, the circuit board manufacturing method of the embodiment can effectively reduce the size of the pre-bumps 16 以及 and the bump pitch, and the circuit board prepared by the circuit board manufacturing method of the embodiment can carry the wafer pad spacing. Small wafers. Next, referring to FIG. 1D, the barrier layer 150 is removed, and then the conductive layer 140 is removed. At this time, the wiring board 1 of this embodiment has been initially formed. Thereafter, please again view the photo of FIG. 1D. In this embodiment, a surface treatment layer 172 can be formed on the pre-bump 160 and exposed to the opening pad 124 at 1375501 VIT09-0001I00-TW 30369twf.doc/n A surface treatment layer 174 is formed on a portion outside the port 134a. In the present embodiment, the method of forming the surface treatment layers 172, 174 is, for example, a nickel-gold process, a nickel-palladium process, a palladium-gold process, or a nickel-palladium-gold process. The structural portion of the circuit board 100 in Fig. 1D will be described in detail below.
線路板100包括一基底110、多個頂接墊122、一頂防 焊層132、多個預凸塊160、多個底接墊124以及一底防焊 層134。基底no具有相對的一頂面112與一底面114，且 頂接墊122配置於頂面112上，底接墊124配置於底面114 上。值得注意的是，在圖1A中，為方便說明，僅繪示一 頂接墊122與一底接墊124為例。此外，使用「頂」與「底」 的用語’僅是方便說明，其表示位於基底之相對二側，並 非空間上的實質限制。 砰細而言’在本實施例中 巷泜ιιυ包括The circuit board 100 includes a substrate 110, a plurality of top pads 122, a top solder resist layer 132, a plurality of pre-bumps 160, a plurality of bottom pads 124, and a bottom solder resist layer 134. The substrate no has a top surface 112 and a bottom surface 114, and the top pad 122 is disposed on the top surface 112, and the bottom pad 124 is disposed on the bottom surface 114. It should be noted that, in FIG. 1A, for the convenience of description, only one of the top pads 122 and one of the bottom pads 124 are illustrated. In addition, the terms "top" and "bottom" are used merely for convenience of explanation, and are indicated on the opposite sides of the substrate, and are not substantially limited in space. In detail, in this embodiment, the lane 泜 ι υ includes
116、一核心導電通道118、一上介電層D1、一上導電立 I C1 下；丨電層D2以及一下導電通道c)。 核心層116具有相對的一上表面肠盘 :。核心導電通道118貫穿核心層ιΐ6。上介電層' 廿带於上表面版上。上導電通道01貫穿上介電声曰D1 並電性連接核心導電通道丨 / a 配置於下表面⑽上。下導電通了下介電層D 並電性連接核心導電通道118^广^^牙下二電⑽ 在本實施例中，頂接塾〗2?7球、_ 24。由刖述可知 電通道…與下導電通道二 ==厂 1375501 VIT09-0001IOO-TW 30369twf.doc/n 在本實施例中，線路板100包括一配置於頂面112上 的頂線路層122a，且部分的頂線路層122a構成頂接墊 122。此外，頂線路層122a不具有與形成預凸塊16〇有關 的電鍍線，因此當訊號於線路板100中傳遞時，可以減少 因額外配置電鍍線而對訊號品質所造成的影響。頂防焊層 132配置於頂面112上並覆蓋部分頂線路層122a，頂防焊 層132具有一暴露出部分頂接墊122的開口 132^ 預凸塊160配置於頂接墊122上並位於開口 132a中， 預凸塊160具有一突出於頂防焊層132的突出郜162。相 對於開口 132a的寬度W2 ’突出部162的最大寬度W1可 大於或等於開口 132a的寬度W2，即不小於開口 132a的 寬度W2。另外，相對於頂接墊122的寬度W3，突出部 162的最大寬度wi可小於或等於頂接墊122的寬度W3， 即不大於頂接墊122的寬度W3。 在本實施例中，突出部162具有一凸弧面162a，凸弧 面162a是朝向遠離頂接墊122的方向凸出，突出部162 與頂防焊層132的接觸角0實質上小於90度。詳細的說明 是’藉由本實施例所形成之預凸塊160，由於不需如先前 技術所提及利用圖案化光阻層來形成預凸塊，因此其突出 部162會具有凸弧面162a’使得突出部162與頂防焊層132 的接觸角Θ實質上會小於90度。預凸塊160可直接接觸頂 接塾122以及開口 132a的内壁’預凸塊160例如為一導電 凸塊，其材質例如是金屬。在一實施例中，預凸塊例 如為一銅凸塊。預凸塊160的材質例如為溶點大於配置於 11 1375501 VIT09-0001I00-TW 30369tw£doc/n 預凸塊160上的銲料（未繪示）之熔點的一導電材質，亦 即預凸塊160與銲料具有不同的溶點。在本實施例中，為 避免突出部162氧化或受到外界環境污染，可在突出部162 上配置一表面處理層172,表面處理層172的材質包括鎳、 金、鈀以及其組合之合金或是有機保焊劑（〇rganic Solderability Preservative，0SP)。 在本實施例中，線路板100包括一配置於底面114上 的底線路層124a’且部分的底線路層124a構成底接墊 124。此外，底線路層124a不具有與形成預凸塊160有關 的電鍍線’因此當訊號於線路板100中傳遞時，可以減少 因額外配置電鍍線而對訊號品質所造成的影響。底防焊層 134配置於底面114上並覆蓋部分底線路層124a，底防焊 層134具有一暴露出部分底接墊124的開口 134a。在本實 施例中’為避免底接墊124氧化或受到外界環境污染，可 在底接墊124之暴露於開口 134a外的部分上形成一表面處 理層174，表面處理層174的材質包括鎳、金、鈀以及其 組合之合金或是有機保焊劑（0SP)。 圖2繪示本發明一實施例之晶片封裝結構的剖面圖。 請參照圖2，晶片封裝結構包括一線路板丨〇〇、一晶片 210以及多個銲料凸塊220 ’值得注意的是，在圖2中，為 方便說明，僅繪示一銲料凸塊220為例》線路板1〇〇的結 構與圖1D的線路板1〇〇的結構相同，故於此不再贅述。 晶片210配置於線路板1〇〇上，且晶片21〇上配置有多個 位置對應預凸塊160的晶片接墊212。 12 1375501 VIT09-0001I00-TW 30369twf.doc/n 銲料凸線220配置於晶片210與線路板100之間，以 連接預凸塊160與晶片接塾212。此外，銲料凸塊220斑 預凸塊160可以具有不同的炫點。在本實施例中，可在晶 片接墊212上設置一凸塊底金屬層23〇 (Under Bump Metallurgy，UBM)，以增加銲料凸塊220與晶片接墊212 的暮食隹，且銲料凸塊220可配置於凸塊底金屬層23〇上 並包覆預凸塊160的突出部162。在本實施例中，可在底 接墊124上設置至少一銲球24〇,以與其他的電子元件（未 繪示）電性連接。 綜上所述，本發明是利用位於基底之相對於設有接墊 的頂面的底面上的導電層作為電鍍種子層，以在基底的頂 面的接塾上電鑛形成預凸塊。因此，本發明可避免習知技 術中在晶片载板之頂面上形成圖案化光阻層的開口時受到 製程上對位精準度的限制，而無法縮小圖案化光阻層的開 口的尺寸、凸塊尺寸與凸塊間距的問題。如此一來，本發 明可有效縮小預凸塊的尺寸以及凸塊間距。 雖二本發明已以實施例揭.露如上，然其並非用以限定 本^明，任何所屬技術領域中具有通常知識者，在不脫離 月之精神和範圍内，當可作些許之更動與潤飾，故本 毛明之保魏B t視後附之申請專職圍所界定者為準。 【圖式簡單說明】 圖1A至圖1D繪示本發明一實施例之線路板的製程剖 面圖。 13 1375501 VIT09-0001I00-TW 30369twf.doc/n 圖2繪示本發明一實施例之晶片封裝結構的剖面圖。 【主要元件符號說明】 100 :線路板 110 :基底 112 :頂面 114 :底面 116 :核心層 116a :上表面 116b :下表面 118 .核心導電通道 122 :頂接墊 122a :頂線路層 124 :底接墊 124a :底線路層 132 :頂防焊層 132a :開口 134a :開口 134 :底防焊層 140 :導電層 150 :阻鍍層 152 :開口 160 :預凸塊 162 :突出部 14116, a core conductive channel 118, an upper dielectric layer D1, an upper conductive I C1; a germanium layer D2 and a lower conductive channel c). The core layer 116 has an opposing upper surface intestine disk:. The core conductive path 118 extends through the core layer ι6. The upper dielectric layer' is attached to the upper surface plate. The upper conductive channel 01 penetrates the upper dielectric sonar D1 and is electrically connected to the core conductive channel 丨 / a on the lower surface (10). The lower conductive layer D is electrically connected to the lower dielectric layer D and electrically connected to the core conductive channel 118. The second sub-electrode (10) is in the embodiment, and the top layer is 22-7 balls, _24. It can be seen from the above description that the electrical channel ... and the lower conductive channel two == factory 1375501 VIT09-0001IOO-TW 30369twf.doc/n In this embodiment, the circuit board 100 includes a top wiring layer 122a disposed on the top surface 112, and A portion of the top wiring layer 122a constitutes the landing pad 122. In addition, the top wiring layer 122a does not have an electroplating line associated with the formation of the pre-bumps 16〇, so that when the signal is transmitted in the wiring board 100, the influence on the signal quality due to the additional arrangement of the electroplating lines can be reduced. The top solder resist layer 132 is disposed on the top surface 112 and covers a portion of the top wiring layer 122a. The top solder resist layer 132 has an opening 132 that exposes a portion of the topping pad 122. The pre-bump 160 is disposed on the topping pad 122 and located In the opening 132a, the pre-bump 160 has a protruding protrusion 162 protruding from the top solder resist layer 132. The maximum width W1 of the protrusion 162 with respect to the width W2' of the opening 132a may be greater than or equal to the width W2 of the opening 132a, i.e., not less than the width W2 of the opening 132a. In addition, the maximum width wi of the protrusion 162 may be less than or equal to the width W3 of the susceptor pad 122, that is, not greater than the width W3 of the susceptor pad 122, with respect to the width W3 of the susceptor pad 122. In this embodiment, the protruding portion 162 has a convex curved surface 162a, and the convex curved surface 162a protrudes away from the topping pad 122. The contact angle 0 between the protruding portion 162 and the top solder resist layer 132 is substantially less than 90 degrees. . The detailed description is 'pre-bump 160 formed by the present embodiment. Since the pre-bump is formed without using the patterned photoresist layer as mentioned in the prior art, the protrusion 162 may have a convex curved surface 162a'. The contact angle Θ of the protrusion 162 to the top solder resist layer 132 is substantially less than 90 degrees. The pre-bump 160 can directly contact the top cymbal 122 and the inner wall of the opening 132a. The pre-bump 160 is, for example, a conductive bump, the material of which is, for example, metal. In one embodiment, the pre-bump is, for example, a copper bump. The material of the pre-bump 160 is, for example, a conductive material having a melting point larger than the melting point of the solder (not shown) disposed on the 11 1375501 VIT09-0001I00-TW 30369 tw/doc/n pre-bump 160, that is, the pre-bump 160. Has a different melting point than solder. In this embodiment, in order to prevent the protrusion 162 from being oxidized or contaminated by the external environment, a surface treatment layer 172 may be disposed on the protrusion 162. The surface treatment layer 172 is made of nickel, gold, palladium and a combination thereof or保rganic Solderability Preservative (0SP). In the present embodiment, the circuit board 100 includes a bottom wiring layer 124a' disposed on the bottom surface 114 and a portion of the bottom wiring layer 124a constitutes the bottom pad 124. In addition, the bottom wiring layer 124a does not have a plating line associated with the formation of the pre-bumps 160. Therefore, when signals are transmitted in the wiring board 100, the influence on the signal quality due to the additional arrangement of the plating lines can be reduced. The bottom solder resist layer 134 is disposed on the bottom surface 114 and covers a portion of the bottom wiring layer 124a. The bottom solder resist layer 134 has an opening 134a exposing a portion of the bottom pad 124. In the present embodiment, in order to prevent the bottom pad 124 from being oxidized or contaminated by the external environment, a surface treatment layer 174 may be formed on a portion of the bottom pad 124 exposed to the outside of the opening 134a. The surface treatment layer 174 is made of nickel, Alloys of gold, palladium and combinations thereof or organic solder resists (0SP). 2 is a cross-sectional view showing a wafer package structure in accordance with an embodiment of the present invention. Referring to FIG. 2, the chip package structure includes a circuit board 丨〇〇, a wafer 210, and a plurality of solder bumps 220. It is noted that, in FIG. 2, for convenience of description, only one solder bump 220 is illustrated. The structure of the circuit board 1 相同 is the same as that of the circuit board 1 图 of FIG. 1D, and thus will not be described again. The wafer 210 is disposed on the wiring board 1 and the wafer 21 is provided with a plurality of wafer pads 212 corresponding to the pre-bumps 160. 12 1375501 VIT09-0001I00-TW 30369twf.doc/n The solder bump 220 is disposed between the wafer 210 and the wiring board 100 to connect the pre-bump 160 and the wafer interface 212. In addition, the solder bumps 220 pre-bumps 160 can have different glare points. In this embodiment, a bump bottom metal layer 23 (UBM) may be disposed on the wafer pad 212 to increase the solder bumps of the solder bumps 220 and the wafer pads 212, and the solder bumps. 220 may be disposed on the bump bottom metal layer 23 and cover the protrusion 162 of the pre-bump 160. In this embodiment, at least one solder ball 24A may be disposed on the bottom pad 124 to be electrically connected to other electronic components (not shown). In summary, the present invention utilizes a conductive layer on the bottom surface of the substrate opposite the top surface on which the pads are provided as a plating seed layer to form a pre-bump on the top surface of the substrate. Therefore, the present invention can avoid the limitation of the alignment accuracy of the process when forming the opening of the patterned photoresist layer on the top surface of the wafer carrier in the prior art, and cannot reduce the size of the opening of the patterned photoresist layer. The problem of bump size and bump spacing. In this way, the present invention can effectively reduce the size of the pre-bumps and the pitch of the bumps. Although the present invention has been described in the above embodiments, it is not intended to limit the scope of the invention, and any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the month. Retouching, so this is the definition of the application of the full-time enclosure. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a process of a circuit board according to an embodiment of the present invention. 13 1375501 VIT09-0001I00-TW 30369 twf.doc/n FIG. 2 is a cross-sectional view showing a wafer package structure according to an embodiment of the present invention. [Main component symbol description] 100: circuit board 110: substrate 112: top surface 114: bottom surface 116: core layer 116a: upper surface 116b: lower surface 118. core conductive path 122: top pad 122a: top circuit layer 124: bottom Pad 124a: bottom wiring layer 132: top solder resist layer 132a: opening 134a: opening 134: bottom solder resist layer 140: conductive layer 150: resist plating layer 152: opening 160: pre-bump 162: protrusion 14