1313098 九、發明說明： 【發明名稱】：具有用於輕載操作的節能電路之軟切献電源轉換器 【發明所屬之技術領域】 本發明關於-種電_換n，特別是關於__種電源轉換器的控制電路。 【先前技術】 φ 冑源轉換器是用於將一未調節之電源轉換為-恒定電壓源。電源轉換器通常 包括-變壓②’其包括用以提供絕緣的—初級繞組（primarywinding)以及一次級 繞組（secondary winding)。一切換裝置連接到初級繞組，以控制從初級繞組至 次級繞組之能量轉換。雖然較高的操作頻率可令電源轉換器具有較小的尺寸和重 量，然而，切換損耗、元件應力以及電磁干擾都是其固有的問題。在近期的發展 中’ 一種常見的軟切換式（soft switching)相移（phase shift)設計被提出，用以 減少南頻功率轉換的切換損耗。在這些發展中，全橋准諧振（quasi_res〇nant) zvs 技術描述如後：即由 Christopher、P. Henze、Ned Mohan 以及 John G. Hayes 於 1989 年8月8曰在美國專利第4,855,888號所提出之“以零電壓切換的恒定頻率諧振電源 • 轉換器（c〇nstant Frequency Resonant Power Converter with Zero Voltage Switching)’’ ；由 Guichao C. Hua和 Fred C. Lee於 1995 年 8 月 15 曰在美國專利第 5,442,540號所提出之“軟切換式脈寬調變轉換(soft_switching pwM C()nvertei_s),，； 還有Yungtaek Jang和Milan M. Jovanovic於2002年3月12日所提出之“軟切換式 全橋轉換器(Soft-switched Full-bridge Converters)”。用於順向式（forwar(j) ZVS 電 源轉換器之主動箝位（active clamp)技術揭示於下文之中，例如有F. Don 丁姐於 1999年10月26曰在美國專利第5,973,939號所提出之“具脈寬調變軟切換之雙順 向式轉換器(Double Forward Converter with Soft-PWM Switching)，，；由 Simon Fraidlin 5 1313098 和Anatoliy Pdikarpov於2001年2月20日在美國專利第6，191，96〇號所提出之“主 動箝位絕緣的M、轉換H以及其操作方法(Aetive aamp丨遍ed p。而 andMethodofOpemtingTh⑽D”。對於半橋技術來說，開發了一種用於zvs的非 對稱設計’即由Rui Liu於2000年5月30日在美國專利第6,〇69,798號所提出之“非 t^#^H^*#^^^(Assymmetrical Power Converter and Method of Operation Thereof)”。在各種不同的zvs轉換器中，使用變壓器之寄生漏電感 (P_hC leakage inductance)以及額外的磁性元件作為諧振電感器（__ inductor)或開關，用於產生環電流以達到零電壓的切換。 第1圖說明-現有的主動箝位電源轉換器。第1A圖〜第1D圖說明上述電源 轉換器的四個操作階段。第1A圖說明當__第_訊號&導通電晶體仏，其用以將 能量從電源轉換器的-輸人經由—麵器Τι傳遞到電源轉換㈣_輸出上。如第 1B圖所示，當電晶體Ql截止時，器Τι的能量將經由一寄生二極體仏流入一 電容器cj。同時，-第二訊號S2將導通一電晶體&，因而達到電晶體仏之軟 切換。如帛1C圖所示’當變壓器Tl 量完全釋放後，電容器Q將透過導通的 電晶體Q2開始對變壓器1進行充電。第1D圖說明第四個操作階段，其中第二訊 號S2停用以截止電晶體Q2，因此切斷流經變壓器T】和電容器C1之間的電流。其 間’儲存於籠器Tl中的能量會產生—環電流，因而將電晶體^的寄生電容器1313098 IX. Invention Description: [Invention Name]: Soft-cut power converter with energy-saving circuit for light-load operation [Technical Field of the Invention] The present invention relates to a type of electricity_for n, especially for __ The control circuit of the power converter. [Prior Art] The φ 胄 source converter is used to convert an unregulated power supply to a constant voltage source. The power converter typically includes a transformer 2' which includes a primary winding for providing insulation and a secondary winding. A switching device is coupled to the primary winding to control energy conversion from the primary winding to the secondary winding. Although higher operating frequencies allow the power converter to have a smaller size and weight, switching losses, component stress, and electromagnetic interference are inherent problems. In the recent development, a common soft switching phase shift design has been proposed to reduce the switching loss of the south frequency power conversion. In these developments, the full-bridge quasi-resonant (quasi_res〇nant) zvs technique is described in the following: by Christopher, P. Henze, Ned Mohan, and John G. Hayes, August 8, 1989, in U.S. Patent No. 4,855,888. "c〇nstant Frequency Resonant Power Converter with Zero Voltage Switching" by Guichao C. Hua and Fred C. Lee on August 15, 1995 in US Patent The soft-switching pulse width modulation conversion (soft_switching pwM C() nvertei_s), as described in No. 5, 442, 540, and the "soft-switching full" proposed by Yungtaek Jang and Milan M. Jovanovic on March 12, 2002 Soft-switched Full-bridge Converters. The active clamp technique for the forward (forwar(j) ZVS power converter is disclosed below, for example, by F. Don Ding at October 26, 1999, in U.S. Patent No. 5,973,939. "Double Forward Converter with Soft-PWM Switching", proposed by Simon Fraidlin 5 1313098 and Anatoliy Pdikarpov on February 20, 2001 in US Patent No. 6 , 191,96 nicknamed "active clamping insulation M, conversion H and its operation method (Aetive aamp丨 ed p. and MethodofOpemtingTh (10) D". For the half bridge technology, developed a non-zvs non "Symmetric design" is the "Assymmetrical Power Converter and Method of Operation Thereof" proposed by Rui Liu on May 30, 2000 in U.S. Patent No. 6, 〇69,798. In various zvs converters, the transformer's parasitic leakage inductance (P_hC leakage inductance) and additional magnetic components are used as resonant inductors (__ inductors) or switches for generating ring currents to achieve zero voltage switching. 1 illustrates the existing active clamp power converter. Fig. 1A to Fig. 1D illustrate four operational stages of the above power converter. Fig. 1A illustrates the use of the _____ signal & To transfer energy from the power converter to the power converter (four)_ output. As shown in Figure 1B, when the transistor Ql is turned off, the energy of the device will pass through a parasitic diode.仏 flows into a capacitor cj. At the same time, the second signal S2 will turn on a transistor &, thus achieving soft switching of the transistor 。. As shown in Fig. 1C, 'When the amount of transformer Tl is completely released, the capacitor Q will pass through. The transistor Q2 begins to charge the transformer 1. Figure 1D illustrates a fourth stage of operation in which the second signal S2 is deactivated to turn off the transistor Q2, thus cutting off the current flowing between the transformer T] and the capacitor C1. During this time, the energy stored in the cage T1 will generate a ring current, thus the parasitic capacitor of the transistor ^
Cj放電。為了導通寄生二極體Dl而達到電晶體仏的軟切換，寄生電容器Cj的電 荷必須先完全釋放完畢。 為達到轉換的標準須符合下列條件： ///(2χΙρ)>^.χ^2/2 其中LP是變壓器Tl之初級繞組的電感，Ιρ是變壓器初級繞組的電流，而KM 是電源轉換器之輸入電壓。 1313098 諧振頻率fr如下式所示： fr =1/(2^-X xCy) 用於完成軟切換之相移（phaseshift)的—延遲時間TD1 ’如下式所示： = ^xLpXC./2 第2圖說明-傳統的非對稱半橋順向式電源轉換器，其中訊號^和^的操作 與第i騎示之電源轉換。雜上賴電源轉換魏夠完絲切換，以減 低在重載下的切換損耗’但是，其缺點在於在輕載下功率雜仍然偏高。 【發明内容】 本發明之目的是提供—軟浦式《、轉換H，由此而減少在輕載下的功率 消耗。 此軟切換式電源轉換器包括—電容器和一變壓器。為進行軟切換操作，電容 盗連接到麵β。-第來切觀壓器，由此將轉從電源轉換器的一輸 入’傳遞到電轉翻的-輸出。_第二開_來將電容器量城到變壓器， 由此產生f電㈨以&成第—開關的軟切換操作。―控制電路連接到電源轉換 盗的輸出，以接收-回授訊號。控制電路依據回授訊號產生—第—訊號和一第二 訊號，用以調節電源轉換器的輪出。帛—訊號和—第二訊號，分雜接到第一開 關和第二開關，以進行切換操作。回授訊號的—第—範圍代表—重載狀況，隨著第 Λ號之啟用時間（on_time)的減少，第二訊號的啟用時間將增加。啟用時間 (on-time)疋義為-個訊號處於啟用狀態的時間區間。在第—開關截止後與第二 訊號啟用前，將產生-第_延遲時間。而在第二開_止後與第—訊號啟用前， 將產生帛L遲時間。第二延遲時間於回授訊號的第一範圍内為恒定。而第二 1313098 延遲時間於回授訊號的一第二範圍内為可變的，其中第二延遲時間依據回授訊號 的減少而比例地延展。回授訊號的第二範圍，代表一輕載狀況。控制電路包括— 臨界，用以定義回授訊號的第一範圍及第二範圍。此外，控制電路更包括一輸入 端子和一可程式端子。輸入端子用於編程回授訊號第一範圍的第二延遲時間。可 程式端子是為編程臨界而開發。 上述說明僅是本發明技術方案的概述，為了能夠更清楚瞭解本發明的技術手 段，並可依照說明書的内容予以實施，以下以本發明的較佳實施例並配合附圖詳 細說明如後。 【實施方式】 第3圖是根據本發明-實酬所繪权軟切換式魏轉換㈣電路圖。其 包括一磁性裝置(如變壓器30)。變壓器30和一電容器3S串聯連接。電容器沾用Cj discharge. In order to turn on the parasitic diode D1 to achieve soft switching of the transistor, the charge of the parasitic capacitor Cj must be completely released first. To achieve the conversion criteria, the following conditions must be met: ///(2χΙρ)>^.χ^2/2 where LP is the inductance of the primary winding of transformer T1, Ιρ is the current of the primary winding of the transformer, and KM is the power converter The input voltage. 1313098 The resonant frequency fr is as follows: fr =1/(2^-X xCy) The phase shift used to complete the soft shift phase shift (delay time TD1 ' is as follows: = ^xLpXC./2 2 Figure illustrates a conventional asymmetric half-bridge forward power converter in which the operation of the signals ^ and ^ is switched to the power supply of the i-th riding. Miscellaneous power conversion Wei can be switched to reduce the switching loss under heavy load. However, the disadvantage is that the power miscellaneous is still high under light load. SUMMARY OF THE INVENTION It is an object of the present invention to provide a soft-pull type, a conversion H, thereby reducing power consumption at light loads. The soft-switching power converter includes a capacitor and a transformer. For soft switching operations, the capacitor is connected to the surface β. - The first to cut the pressure gauge, thereby transferring the transfer from an input of the power converter to the output of the electric turn-over. _ second open _ to measure the capacitor to the transformer, thereby generating f power (nine) to & into the first switch soft switching operation. The control circuit is connected to the output of the power conversion thief to receive-receive the signal. The control circuit generates a -signal and a second signal according to the feedback signal to adjust the turn-off of the power converter. The 帛-signal and the second signal are connected to the first switch and the second switch to perform the switching operation. The -first range of the feedback signal represents the overload condition. As the activation time (on_time) of the nickname decreases, the activation time of the second signal will increase. The on-time is defined as the time interval in which the signal is enabled. The -th delay time will be generated after the first switch is turned off and before the second signal is enabled. After the second open-stop and the first-signal enable, a delay time will be generated. The second delay time is constant within the first range of the feedback signal. The second 1313098 delay time is variable within a second range of the feedback signal, wherein the second delay time is proportionally extended according to the decrease of the feedback signal. The second range of feedback signals represents a light load condition. The control circuit includes a threshold for defining a first range and a second range of the feedback signal. In addition, the control circuit further includes an input terminal and a programmable terminal. The input terminal is used to program a second delay time of the first range of feedback signals. Programmable terminals are developed for programming criticality. The above description is only an overview of the technical solutions of the present invention, and the technical means of the present invention can be more clearly understood, and can be implemented in accordance with the contents of the specification. Hereinafter, the following detailed description will be made with reference to the preferred embodiments of the present invention and the accompanying drawings. [Embodiment] FIG. 3 is a circuit diagram of a soft switching type Wei conversion (four) according to the present invention. It includes a magnetic device (such as transformer 30). The transformer 30 and a capacitor 3S are connected in series. Capacitor
二範圍。回授訊號VFB的第一範圍代表一重載狀況。 fb是處於一第一範圍或處於一第 L。而回授訊號VFB的第二範圍則 8 1313098 代表一輕載狀況。第一訊號Si和第二訊號s2，係依據回授訊號vFB而產生。在回 授訊號Vfb的第一範圍中，第二訊號S2之啟用時間隨著第一訊號Si之啟用時間的 減少而增加。 第4A圖和第4B圖是第3圖所示之電源轉換器的訊號波形圖。第4A圖說 明在重載狀況下，第一訊號S!和第二訊號S2的波形。第4B圖說明在輕載狀況下， 第一訊號Si和第二訊號Si的波形。在第一開關1〇載止後與第二訊號82啟用前， 產生一第一延遲時間TD1。而在此第二開關20載止後與第一訊號Sl啟用前，產生 一第二延遲時間τΜ。第二延遲時間Td2於回授訊號Vfb的第一範圍内為恒定。而 第二延遲時間Τ〇2於回授訊號Vfb的第二範圍内為可變的，其中，第二延遲時間 Tm隨著回授訊號VFB的減少而比例地延展。 第3圖所示之控制電路1〇〇更包括一輸入端子Rp，其用以在回授訊號Vfb 的第一範圍編程第二延遲時間TD2。一電阻器56從控制電路100的輸入端子RD 連接到一接地參考，由此來編程第二延遲時間Td2。另外，一電阻器57從一可程 式端子RP連接到接地參考’由此來編程臨界。控制電路1〇〇的一電流感應端子 VS連接到一電阻器50,用以檢測變壓器3〇的一切換電流訊號Vs，以此來完成控 制電路100的脈寬調變（pulse Width Modulation，PWM)控制。 第5圖是根據本發明一實施例所繪示之控制電路1〇〇的電路圖。控制電路 100包括一振盪電路2〇〇 ’其用以產生一脈衝訊號PLS、一鋸齒訊號rmP，以及 —最大工作週期訊號MD。脈衝訊號PLS經由一反閘71供應到一正反器85中的 時脈輸入。一比較器80用以將正反器85重置。比較器80的兩個輸入分別連接到 回授端子FB以及一電路350之一輸出。此電路350將鋸齒訊號RMP和切換電流 訊號Vs相加後產生一斜坡訊號（sl〇pesignal)。一旦斜坡訊號高於回授訊號vFB， 9 1313098 4即被重置。正反器85的，物卜聊♦第三輸入，由此產 此第-訊號S”及閘91的一第二輸入和—第四輸入分別連接到反閘71的一輸 出以及最大讀週期訊號娜。—具有—時脈輪人的正反器86，經由—延遲電路 Μ反閘72而輕接到第一訊號Si。第7圖繪示延遲電路細的電路圖。延遲 電路删決定第一延遲時間Tw。因此，正反器86在第一訊號&的下降緣後經過 第L遲時間TDH|_被啟用。反閘71的輪出用於重置正反器祕。當脈衝訊號似 用時正反盗86被復位。正反器86的一輸出連接到一及閑92的一第一輸入， 由此而產生此第二訊號S2。及閘92的_第二輪人連接到反閘71的輪出。此外， 及閘92的-輸出經由一反閉76而連接到及問91的一第一輸入。及間91的一輸出 由反閘75而連接到及閘92的—第三輪入，由此形成一互斥電路（e油咖 如他），以此防止第-開㈣和第二開關2G較叉傳導以於當脈衝訊號pLs —用的時候第峨Sl和第一訊戒&係為停用，因此，隨著脈衝訊號PM的脈 寬（pulse width )之延展’將造成第一訊號&和第二訊號&的停用時間（） 跟著延展。停科_定義為-訊號處於停離態的時段。對於回授訊號％ 的第-範圍來講，電阻器56經由輸入端子RD而決定脈衝訊號pLs的脈寬。對於 回授訊號vFB的第二翻來講’脈衝訊號PLS的脈寬依據回授訊號^ B的減少而 L展因此’使得第一訊號呂^第工訊號S2的切換頻率隨著輸出負載的減少而降 低’由此減少了切換損耗。 第6圖是根據本發明一實施例所繪示之振盪電路2〇〇的電路圖。其中，比 較器201和202分別有一折點電壓（trip-point voltage) VH和一折點電壓VL。比較 器201的一負輪入與比較器202的一正輪入共接到一電容器21〇。一電流源22〇經 由一開關215對電容器210進行充電。開關216用以對電容器210進行放電。反及 閘205和206形成一鎖閂電路（latch circuit),其用以產生脈衝訊號PLS。脈衝訊 號PLS分別被比較器201和202之輪出啟用和停用。一旦電容器21〇之電壓高於 10 1313098 折點電壓VH，脈衝訊號PLS將導通開關216令電容器210進行放電。當電容器 21〇之電壓低於折點電壓VL時，脈衝訊號PLS經由一反閘211導通開關215，令 電容器210進行充電。因而使電容器210上產生鋸齒訊號RMp。一比較器2〇3包 括一參考電壓VM。比較器203的一負輸入連接到電容器21〇。比較器2〇3的一輸 出產生最大工作週期訊號MD，用以決定第一訊號Si的一最大工作週期（duty 。-運算放大器230具有一供應一參考電壓Vri的正輪入，還有一連接到 輪入端子RD的一負輸入。運算放大器23〇和一電晶體2s〇並會同電阻器％，產 生電"il bo。電晶體251和252形成一第一電流鏡（current而江沉）。電晶體254 和255形成一第二電流鏡。一流經電晶體255的電流，是由電流【说經由第一 電流鏡以及第二電流鏡鏡射而得。此電流。55更耦接到電容器21〇，並經由開關216 的導通而令電容器210進行放電。 連接到可程式端子RP的一電流源235與電阻器57，共同產成一用以決定 臨界的電壓。可程式端子RP連接到一運算放大器231。而回授端子^^連接到一 運算放大器232。運算放大器231、232，一電阻器270以及一電晶體260構成一電 壓-電流轉換器，由而生成一電流丨⑽。電流“仰如下列等式所示： ^260 = (Vth -VFb)I -^270 其中νΤΗ代表臨界的電壓值；厂m =/235 χ/?57 電流hw是在回授訊號VFB低於臨界電壓νΤΗ時而產生。電晶體261和262形 成一第三電流鏡’電流經由第三電流鏡鏡射生成一電流Iz62。電流l262進一步 耦接到電晶體255，因而決定電容器210之一放電電流iD。放電電流1〇如下列等 式所示： 1D - ^255 ~ !262 11 l3l3〇98Two ranges. The first range of the feedback signal VFB represents a heavy load condition. Fb is in a first range or at an Lth. The second range of the feedback signal VFB is 8 1313098, which represents a light load condition. The first signal Si and the second signal s2 are generated according to the feedback signal vFB. In the first range of the feedback signal Vfb, the activation time of the second signal S2 increases as the activation time of the first signal Si decreases. 4A and 4B are signal waveform diagrams of the power converter shown in Fig. 3. Figure 4A illustrates the waveforms of the first signal S! and the second signal S2 under heavy load conditions. Figure 4B illustrates the waveforms of the first signal Si and the second signal Si under light load conditions. A first delay time TD1 is generated after the first switch 1 〇 is loaded and before the second signal 82 is enabled. After the second switch 20 is loaded and before the first signal S1 is enabled, a second delay time τ 产生 is generated. The second delay time Td2 is constant within the first range of the feedback signal Vfb. The second delay time Τ〇2 is variable in the second range of the feedback signal Vfb, wherein the second delay time Tm is proportionally extended as the feedback signal VFB decreases. The control circuit 1 shown in FIG. 3 further includes an input terminal Rp for programming the second delay time TD2 in the first range of the feedback signal Vfb. A resistor 56 is connected from the input terminal RD of the control circuit 100 to a ground reference, thereby programming the second delay time Td2. In addition, a resistor 57 is connected from a programmable terminal RP to a ground reference ' thereby programming criticality. A current sensing terminal VS of the control circuit 1 is connected to a resistor 50 for detecting a switching current signal Vs of the transformer 3〇, thereby completing the pulse width modulation (PWM) of the control circuit 100. control. FIG. 5 is a circuit diagram of a control circuit 1A according to an embodiment of the invention. The control circuit 100 includes an oscillating circuit 2' for generating a pulse signal PLS, a sawtooth signal rmP, and a maximum duty cycle signal MD. The pulse signal PLS is supplied to the clock input in a flip-flop 85 via a reverse gate 71. A comparator 80 is used to reset the flip-flop 85. The two inputs of comparator 80 are coupled to feedback terminal FB and one of circuit 350 outputs, respectively. The circuit 350 adds the sawtooth signal RMP and the switching current signal Vs to generate a ramp signal (sl〇pesignal). Once the ramp signal is higher than the feedback signal vFB, 9 1313098 4 is reset. The flip-flop 85, the third input, the second input and the fourth input of the first signal and the fourth input are respectively connected to an output of the reverse gate 71 and the maximum read period signal. The positive and negative device 86 with the clock wheel is lightly connected to the first signal Si via the delay circuit Μ reverse gate 72. Figure 7 shows a detailed circuit diagram of the delay circuit. Time Tw. Therefore, the flip-flop 86 is enabled after the falling edge of the first signal & the Lth delay time TDH|_. The turn-off of the reverse gate 71 is used to reset the flip-flop. When the pulse signal is used The anti-theft 86 is reset. An output of the flip-flop 86 is connected to a first input of the idle 92, thereby generating the second signal S2. The second round of the gate 92 is connected to the reverse gate. In addition, the output of the AND gate 92 is connected to a first input of the 91 via an anti-close 76. An output of the 91 is connected to the gate 92 by the reverse gate 75. Wheeling, thereby forming a mutual exclusion circuit (e oil coffee like him), thereby preventing the first-on (four) and second switch 2G from being conducted relative to the fork so that when the pulse signal pLs - At the time of the second sl and the first squadron & is deactivated, therefore, with the extension of the pulse width of the pulse signal PM 'will cause the deactivation of the first signal & and the second signal & The time () is followed by the extension. The stop _ is defined as the period in which the signal is in the stop state. For the first range of the feedback signal %, the resistor 56 determines the pulse width of the pulse signal pLs via the input terminal RD. In the second turn of the signal vFB, the pulse width of the pulse signal PLS is reduced according to the decrease of the feedback signal ^ B. Therefore, the switching frequency of the first signal L1 is reduced as the output load decreases. 'Therefore, the switching loss is reduced. Fig. 6 is a circuit diagram of the oscillating circuit 2 绘 according to an embodiment of the invention, wherein the comparators 201 and 202 respectively have a trip-point voltage VH and A breakpoint voltage VL. A negative turn-in of the comparator 201 is coupled to a positive turn of the comparator 202 to a capacitor 21A. A current source 22 is used to charge the capacitor 210 via a switch 215. The capacitor 210 is discharged. The gates 205 and 20 are reversed. 6 forming a latch circuit for generating the pulse signal PLS. The pulse signal PLS is enabled and disabled by the rotation of the comparators 201 and 202, respectively. Once the voltage of the capacitor 21 is higher than 10 1313098, the voltage is broken. VH, the pulse signal PLS will turn on the switch 216 to discharge the capacitor 210. When the voltage of the capacitor 21 is lower than the break point voltage VL, the pulse signal PLS turns on the switch 215 via a reverse gate 211 to charge the capacitor 210. A sawtooth signal RMp is generated on 210. A comparator 2〇3 includes a reference voltage VM. A negative input of comparator 203 is coupled to capacitor 21A. An output of the comparator 2〇3 generates a maximum duty cycle signal MD for determining a maximum duty cycle of the first signal Si (duty.) The operational amplifier 230 has a positive turn-in that supplies a reference voltage Vri, and one is connected to A negative input of the terminal RD is turned in. The operational amplifier 23A and a transistor 2s are combined with the resistor % to generate an electric "il bo. The transistors 251 and 252 form a first current mirror (current and sink). The transistors 254 and 255 form a second current mirror. The current through the transistor 255 is derived from the current [speaking via the first current mirror and the second current mirror. This current 55 is further coupled to the capacitor 21电容器, and discharging the capacitor 210 via the conduction of the switch 216. A current source 235 connected to the programmable terminal RP and the resistor 57 together generate a voltage for determining the threshold. The programmable terminal RP is connected to an operational amplifier 231. The feedback terminal is connected to an operational amplifier 232. The operational amplifiers 231, 232, a resistor 270 and a transistor 260 form a voltage-current converter, thereby generating a current 丨 (10). As shown in the following equation: ^260 = (Vth -VFb)I -^270 where νΤΗ represents the critical voltage value; factory m = /235 χ/?57 current hw is below the feedback signal VFB below the threshold voltage νΤΗ The transistors 261 and 262 form a third current mirror 'current to generate a current Iz62 via the third current mirror. The current l262 is further coupled to the transistor 255, thus determining a discharge current iD of the capacitor 210. The current 1 is as shown in the following equation: 1D - ^255 ~ !262 11 l3l3〇98
4 « X W A)]-伙3 X[(/235 X 仏)〜4]/D 其中，h和k3分別是第-電流鏡和第三f流鏡的鏡射比率；〜、知、— 分別是電阻器56、57和270的電阻值。 因此’對於回授訊號vFB的第-範圍來講，電阻器56決定電流j说以及電容 器21〇的放電電流lD。而電阻器57決定臨界，由此決定了回授訊號％的第一範 圍和第二範圍。回授訊號Vfb係依據輸出負載的減少而降低。因此，對於回授訊 號vFB的第二範圍來講’依據輸出負載的減少’電容器21❶的放電電流b將比例 地降低’令苐二延遲時間Tj>2比例地延展。 由於第-開關10和第二開關20的切換頻率隨著輸出負載的減少而降低，因 此，在輕餘況下電源轉換器的功率消耗便得以降低。此外，只有第二延遲時間 “是可變的。第-訊號Sl和第二域&之時序，在域和重餘況下都保持— 樣，因此確保了軟切換式電源轉換器的正常操作。 以上所述，僅是本發明啸佳實施_已，並非對本發明作任何形式上的 限制’軸本發明已以較佳實施_露如上，—並_以限定本發明，任何 熟悉本專業的技術人員，在不脫離本發明技術方案範圍内，當可_上述揭示 的結構及技抽容作出些許的更動或修飾為等_化的等效實施例，但是凡I 未脫離本發明技術方案_容，依據本發明的技術實質對以上實施例所作的^ 何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍内。 12 1313098 【圖式簡單說明】 以下的圖表描繪出本發明的實 _並加與包含詳細規格的一部份 理。 1、’配合_細說明部分，肋轉本發明的 第2圖是—軸_半㈣階段的示意β4 « XWA)]- 伙3 X[(/235 X 仏)~4]/D where h and k3 are the mirror ratios of the first-current mirror and the third-f-flow mirror respectively; ~, know, - respectively The resistance values of resistors 56, 57 and 270. Therefore, for the first range of the feedback signal vFB, the resistor 56 determines the current j and the discharge current 1D of the capacitor 21A. The resistor 57 determines the criticality, thereby determining the first range and the second range of the feedback signal %. The feedback signal Vfb is reduced according to the reduction of the output load. Therefore, for the second range of the feedback signal vFB, the discharge current b of the capacitor 21A is proportionally lowered in accordance with the decrease in the output load, and the delay time Tj > 2 is proportionally extended. Since the switching frequency of the first switch 10 and the second switch 20 decreases as the output load decreases, the power consumption of the power converter is reduced under light conditions. In addition, only the second delay time is "variable. The timing of the -signal S1 and the second domain& is maintained in both the domain and the rest, thus ensuring the normal operation of the soft-switching power converter. The above is only the implementation of the present invention, and has not been limited to any form of the invention. The present invention has been preferably implemented as described above, and is intended to limit the present invention to any one skilled in the art. A person skilled in the art can make some modifications or modifications to the equivalent structure of the structure and technology disclosed above without departing from the technical solution of the present invention. The simple modifications, equivalent changes, and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solution of the present invention. 12 1313098 [Simplified Schematic] The following chart depicts the present invention. The actual _ is added and contains a part of the detailed specifications. 1. 'Combination _ fine description part, the rib turns to the second picture of the invention is the axis_half (four) stage of the schematic β
第第mrBr—實施騎繪示之軟切換錢源』⑽電路圖。 =4A圖和第4B圖是第3圖所示之電源轉換器的 第5圖是根據本發明一實施例所繪示之控制電路的電路圖 第6圖是根據本發明一實施例崎示之振逢電路的電路圖。 第7圖是根據本發明一實施例所纷示之延遲電路的電路圖。The first mrBr—implementing the soft-switching money source of the rider” (10) circuit diagram. FIG. 5 is a circuit diagram of a control circuit according to an embodiment of the present invention. FIG. 6 is a diagram showing a vibration of a control circuit according to an embodiment of the present invention. Every circuit diagram of the circuit. Figure 7 is a circuit diagram of a delay circuit shown in accordance with an embodiment of the present invention.
【主要元件符號說明】 10 :第一開關 30 :變壓器 50、51、52、53、56、57、270 : 65 :耦合器 80、201、202、203 :比較器 91、92 :及閘 200 :振盪電路 215、216 :開關 230、231、232 :運算放大器 250、251、252、254、255、260、 20 :第二開關 35、54、210 :電容器 【阻 60:誤差放大器 71、72、75、76、211 :反閘 85、86 :正反器 100 :控制電路 205、206 :反及閘 220、235 :電流源 261、262 :電晶體 13 1313098[Description of main component symbols] 10: First switch 30: Transformers 50, 51, 52, 53, 56, 57, 270: 65: Couplers 80, 201, 202, 203: Comparators 91, 92: and Gate 200: Oscillation circuits 215, 216: switches 230, 231, 232: operational amplifiers 250, 251, 252, 254, 255, 260, 20: second switches 35, 54, 210: capacitors [resistance 60: error amplifiers 71, 72, 75 , 76, 211: reverse gate 85, 86: flip-flop 100: control circuit 205, 206: reverse gate 220, 235: current source 261, 262: transistor 13 1313098
300 :延遲電路 FB :回授端子 PLS :脈衝訊號 RD :輸入端子 工250、工255、1260、[262 :電流 S,:第一訊號 TD1:第一延遲時間 Vfb :回授訊號 VH、VL :折點電壓 VR :參考訊號 350 :電路 MD :最大工作週期訊號 RMP :鋸齒訊號 RP :可程式端子 Id :放電電流 S2 :第二訊號 TD2 :第二延遲時間 Vin :輸入電壓 Vm、Vri :參考電壓 Vs :切換電流訊號300: Delay circuit FB: feedback terminal PLS: pulse signal RD: input terminal 250, 255, 1260, [262: current S,: first signal TD1: first delay time Vfb: feedback signal VH, VL: Breakpoint voltage VR: reference signal 350: circuit MD: maximum duty cycle signal RMP: sawtooth signal RP: programmable terminal Id: discharge current S2: second signal TD2: second delay time Vin: input voltage Vm, Vri: reference voltage Vs: switching current signal
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