TWI802082B - Dual mode flyback converter - Google Patents

Abstract

A dual mode flyback converter is disclosed. The dual mode flyback converter includes a flyback converter, a comparator, a first controller and a second controller. The flyback converter receives the input voltage and outputs the output voltage. The comparator is connected to the flyback converter and the comparator signal is output by comparing the output voltage with the reference voltage. The flyback converter includes the first switch and the second switch. The first controller is connected between the first switch and the comparator. The second controller is connected between the comparator and the second switch. When operating at light load, the flyback converter is operated in the Quasi-Resonant Mode. When operating at heavy load, the flyback converter is operated in the Active-Clamp Flyback Mode.

Description

Dual Mode Flyback Converter

The present invention relates to a dual-mode flyback converter (Flyback converter), in particular to a quasi-resonant flyback converter (Quasi-Resonant Flyback Converter) at light load and active clamp flyback at heavy load Active-Clamp Flyback Converter is a dual-mode flyback converter.

With the popularity of technology, the demand for electronic products is increasing day by day, and the importance of power converters has also increased. Power converters can be found in motors, mobile phones, computers, and LED drive circuits, and can be further applied to technical fields such as transportation tools, automation systems, and green energy industries. With the advancement of semiconductor manufacturing process, the size of power components is gradually reduced, but the requirements for specifications have not decreased but increased, such as the requirements for low on-resistance or high withstand voltage, and the requirements for specific voltages of different electronic devices. How to make a device that meets the requirements The power converter required by electronic products has become an important topic.

At present, the commonly used converter is the flyback converter, which provides circuit isolation function and simple circuit structure, and is widely used in various types of electronic devices. Flyback converters are broadly classified into quasi-resonant flyback converters and active-clamp flyback converters. Active-clamp flyback converters use two Two switching elements (one is the main switch with voltage conversion control and the other is an auxiliary switch with clamp control) pass the input voltage through Electromagnetic coupling through the inductance is converted to an output voltage. The difference between the quasi-resonant flyback converter and the active clamp flyback converter is that there is no auxiliary switch and only the resonance of the inductor and capacitor is used for valley switching, and the input voltage is converted to the output voltage through the switching of the main switch. The active clamp flyback converter has the advantage of zero-voltage switching, and its power conversion efficiency is higher than that of the quasi-resonant flyback converter at heavy loads, but it still needs to maintain a certain amount of resonant current at light loads, resulting in Power loss leads to poor power conversion efficiency of active clamp flyback at light load.

In view of the foregoing, the inventor of the present invention conceived and designed a dual-mode flyback converter in order to improve the problems of the conventional technology and further enhance the implementation and utilization in the industry.

In view of the problems described in the prior art, the object of the present invention is to provide a dual-mode flyback converter, which uses a comparator and a logic circuit to switch between quasi-resonant mode and active clamp mode at light load and heavy load, reducing power consumption. loss, and improve the problem of poor power conversion efficiency of the active clamp flyback converter at light load.

Based on the above objectives, the present invention provides a dual-mode flyback converter, which includes a flyback converter, a comparator, a first controller, and a second controller. The flyback converter receives an input voltage and outputs an output voltage according to the input voltage. The flyback converter includes a first switch and a second switch. The comparator is connected to the flyback converter, and outputs a comparison signal according to the output voltage and the reference voltage. The first controller is connected between the comparator and the first switch, and the second controller is connected between the comparator and the second switch. Wherein, when the flyback converter is under light load, the first controller and the second controller respectively turn off the first switch and conduct the second switch according to the comparison signal, so that the flyback converter operates in a quasi-resonant mode ( Quasi-Resonant Mode, QR Mode); when the flyback converter is under heavy load, the first controller and the second controller are based on The first switch is turned on and the second switch is turned off according to the comparison signal, so that the flyback converter operates in an Active-Clamp Flyback Mode (ACF Mode).

Preferably, the flyback converter may further include a current sensor, and the current sensor converts the output current into an output voltage.

Preferably, the dual-mode flyback converter may further include a first driver and a second driver, the first driver is connected between the first switch and the first controller, and the second driver is connected between the second controller and the second Between the switches, the first driver controls the conduction of the first switch according to the output of the first controller, and the second driver controls the conduction of the second switch according to the output of the second controller.

Preferably, the first controller and the second controller can respectively include a plurality of logic gates.

Preferably, the dual-mode flyback converter may further include a pulse width modulation controller, the pulse width modulation controller is connected between the first controller and the flyback converter, when the flyback converter When the load is light, the first controller outputs a reset signal to the PWM controller, and the PWM controller receives the sensing voltage of the flyback converter, and the PWM controller according to the reset signal Set signal and sense voltage output pulse signal.

Preferably, the dual-mode flyback converter may further include a frequency resonance controller, the frequency resonance controller is connected between the pulse width modulation controller and the second controller, and the frequency resonance controller outputs a delay according to the pulse signal signal to the second controller.

Based on the above, according to the dual-mode flyback converter of the present invention, it may have one or more of the following advantages:

(1) This dual-mode flyback converter can be controlled by a logic circuit, so that the converter operates in a quasi-resonant mode when it is light-loaded, and operates in an active clamping mode when it is heavy-loaded. efficiency.

(2) This dual-mode flyback converter can operate in discontinuous conduction mode at light load, so that the output rectifier diode has no reverse recovery current loss, and the power switch is also turned on when the sink-source resonates to the valley, Significantly reduce the loss when the power switch is turned on.

(3) This dual-mode flyback converter can use the active clamp design to complete the zero-voltage switching of the power switch under heavy load, reduce the switching surge and switching loss, reduce the voltage stress on the power switch, and improve the conversion the operating status of the device.

11,21,31,41: flyback converter

12,22: Comparator

13: First controller

14: Second controller

15,25: Current sensor

16,26: Pulse Width Modulation Controller

17,27: Frequency resonance controller

18,28: delay circuit

23: Controller

100,200: Dual Mode Flyback Converter

C _clamp : clamp capacitance

C _o : output filter capacitor

C _oss1 , C _oss2 : parasitic capacitance

D1: lower arm driver

D2: Upper arm drive

D _o : rectifier diode

D _RVm : delayed signal

FB: feedback circuit

L: load

L _m : Magnetizing inductance

L _r : Resonant inductance

N ₁ : Primary side

N ₂ : Secondary side

S ₁ : lower arm switch

S ₂ : Upper arm switch

V _C1 : comparison signal

V _comp : Feedback comparison signal

V _FB : Feedback signal

V _GSD1 : lower arm control signal

V _GSD2 : upper arm control signal

V _GS1 : Lower arm delay signal

V _GS2 : upper arm delay signal

V _in : input voltage

V _PWM : pulse signal

V _ref : Reference voltage

V _RESET : reset signal

V _sense1 : sense voltage

V _sense2 : output voltage

In order to make the technical features, content and advantages of the present invention and the effects it can achieve more obvious, the present invention will be described in conjunction with the following drawings: Figure 1 is a dual-mode flyback converter according to an embodiment of the present invention The schematic diagram.

Figure 2 is a schematic diagram of the first controller and the second controller of the embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a dual-mode flyback converter according to an embodiment of the present invention.

4A to 4D are schematic diagrams of quasi-resonant mode operation of an embodiment of the present invention.

FIG. 5A to FIG. 5F are schematic diagrams of the active clamp mode operation of the embodiment of the present invention.

FIG. 6 is an operation timing diagram of a dual-mode flyback converter according to an embodiment of the present invention.

In order for the Ligui Examiner to understand the technical features, content and advantages of the present invention and the effects it can achieve, the present invention is hereby combined with the accompanying drawings and described in detail in the form of an embodiment as follows, and the drawings used therein, its The purpose is only for illustration and auxiliary description, not necessarily for the implementation of the present invention Real proportions and precise configurations, therefore, should not be interpreted based on the proportions and configurations of the attached drawings, and should not limit the scope of rights of the present invention in actual implementation, and shall be described first.

Please refer to FIG. 1, which is a schematic diagram of a dual-mode flyback converter according to an embodiment of the present invention. As shown in the figure, the dual-mode flyback converter 100 includes a flyback converter 11 , a comparator 12 , a first controller 13 and a second controller 14 . The flyback converter 11 receives the input voltage V _in and outputs the output voltage V _sense2 according to the flyback converter 11. The flyback converter 11 is connected to the current sensor 15 and the load L, and the current sensor 15 converts the output current passing through the load L to is the output voltage V _sense2 , which is sent to the comparator 12 . The comparator 12 is connected to the flyback converter 11 , receives the output voltage V _sense2 , and compares it with the received reference voltage V _ref to output a comparison signal V _C1 .

The flyback converter 11 includes an upper arm switch and a lower arm switch. The first controller 13 is connected between the comparator 12 and the upper arm switch, receives the comparison signal V _C1 of the comparator 12, and outputs an upper arm control signal V _GSD2 to control the upper arm switch. ; The second controller 14 is connected between the comparator 12 and the lower arm switch, receives the comparison signal V _C1 of the comparator 12 , and outputs the lower arm control signal V _GSD1 to control the lower arm switch. When the flyback converter 11 is under light load, the first controller 13 and the second controller 14 respectively output the upper arm control signal V _GSD2 according to the comparison signal V _C1 to turn off the upper arm switch and output the lower arm control signal V _GSD1 to turn it down. The arm switch is turned on, allowing the flyback converter 11 to operate in the quasi-resonant mode. When the flyback converter 11 is under heavy load, the first controller 13 and the second controller 14 respectively output the upper arm control signal V _GSD2 to turn on the upper arm switch and output the lower arm control signal V _GSD1 to turn on the lower arm _switch according to the comparison signal V C1 . The switch is turned off, allowing the flyback converter 11 to operate in the active clamp mode.

The dual-mode flyback converter 100 may further include a pulse width modulation controller 16, a frequency resonance controller 17, and a delay circuit 18. The pulse width modulation controller 16 is connected to the first controller 13 and the flyback conversion Between the devices 11, the first controller 13 outputs a reset signal V _RESET to the PWM controller 16, and the PWM controller 16 receives the sense voltage V _sense1 of the flyback converter 11, the pulse The WWM controller 16 outputs a pulse signal V _PWM according to the reset signal V _RESET and the sense voltage V _sense1 . The frequency resonance controller 17 is disposed between the PWM controller 16 and the second controller 14 , and the frequency resonance controller 17 outputs a delay signal _DRVm to the second controller 14 according to the pulse signal V _PWM . The delay circuit 18 is connected to the frequency resonance controller 17 , and the delay circuit 18 outputs the upper arm delay signal V _GS2 to the first controller 13 according to the delay signal D _RVm , and outputs the lower arm delay signal V _GS1 to the second controller 14 .

The dual-mode flyback converter 100 may further include a feedback circuit FB disposed between the load L and the PWM controller 16, the feedback circuit FB receives the load feedback signal V _FB , and outputs a feedback comparison signal V _comp to the pulse Wavewidth modulation controller 16.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of the first controller 13 and the second controller 14 according to the embodiment of the present invention. As shown in the figure, the comparator 12 receives the output voltage V _sense2 and compares it with the received reference voltage V _ref to output a comparison signal V _C1 . The first controller 13 and the second controller 14 respectively include a plurality of logic gates. When the flyback converter 11 is under light load, the comparison signal V _C1 is at a low potential, resulting in the AND gate (AND gate) responsible for controlling the first switch ) output is low potential, so the upper arm control signal V _GSD2 will not have PWM signal input, and the upper arm switch is turned off. Another group of AND gates (AND gates) controlling the lower arm switches send the valley trigger signal back to the pulse width modulation controller 16 because the comparison signal V _C1 is reversed to a high potential through a reverse gate (NOT gate). , precisely controlling the lower arm switch to achieve valley cut, so that the flyback converter 11 is in the quasi-resonant mode in this operating range. When the flyback converter 11 is under heavy load, the comparison signal V _C1 output by the comparator 12 is a high potential, which triggers the AND gate (AND gate) responsible for controlling the upper arm switch, so that the output pulse width is complementary to that of the main switch. Modulate the signal to the upper arm switch. Another set of AND gate (AND gate) reverses its high potential through reverse gate (NOT gate), so that its input to the AND gate (AND gate) is low potential, so there will be no reset signal V _RESET at this time It is sent back to the pulse width modulation controller 16 of the main control. In this state, the function of the frequency-limiting quasi-resonant control circuit is turned off, so that the operating state of the flyback converter 11 is an active clamping mode.

Please refer to FIG. 3 . FIG. 3 is a circuit diagram of a dual-mode flyback converter according to an embodiment of the present invention. As shown in the figure, the dual-mode flyback converter 200 includes a flyback converter 21, a comparator 22, a controller 23, a current sensor 25, a load L, a pulse width modulation controller 26, a frequency resonance control Device 27 and delay circuit 28. The flyback converter 21 receives the input voltage V _in and senses the output voltage V _s2 by the current sensor 25 , transmits it to the comparator 22 , compares it with the received reference voltage V _ref and outputs a comparison signal V _C1 . The controller 23 includes a plurality of logic gates. After receiving the comparison signal V _C1 , it switches between different operation modes according to heavy load and light load. For the operation mode, please refer to the above-mentioned embodiments, and the same content will not be repeated here.

The flyback converter 21 includes a lower arm switch S ₁ , an upper arm switch S ₂ , a lower arm driver D1 and an upper arm driver D2, the upper arm driver D2 is connected between the upper arm switch S ₂ and the controller 23, and the lower arm driver D1 is connected to the controller Between device 23 and lower arm switch _S1 . The upper arm driver D2 receives the upper arm control signal V _GSD2 output by the controller 23, outputs the upper arm control signal V _GSD2 to control the conduction of the upper arm switch _S2 , and the lower arm driver D1 receives the lower arm control signal V _GSD1 output by the controller 23, and outputs the lower arm control signal V GSD1 The signal V _GSD1 controls the conduction of the lower arm switch S ₁ . The flyback converter 21 operates in a quasi-resonant mode at light loads, and operates in an active clamping mode at heavy loads. The different operating modes will be described in the following embodiments.

Please refer to FIG. 4A to FIG. 4D , which are schematic diagrams of quasi-resonant mode operation of an embodiment of the present invention. The resonant converter is a resonant circuit composed of inductors and capacitors added to the converter, and quasi-resonant refers to the use of these two to generate resonance. When the sine wave drops to zero or the lowest point, the power switch is performed at this time. Turn on or off to reduce the switching loss of the power switch. For the circuit of the overall dual-mode flyback converter, please refer to the foregoing embodiments. In this embodiment, since the upper arm switch S ₂ is turned off, the content of the upper arm switch S ₂ and the clamping capacitor C _clamp is omitted, and please also refer to Chapter 6 Fig. 6 is an operation timing diagram of a dual-mode flyback converter according to an embodiment of the present invention.

t

t₁)，下臂開關S₁導通，電流由輸入電源V_in流經變壓器，此時激磁電感L_m呈線性上升，由於變壓器初級側N₁與次級側N₂極性相反，因此輸出整流二極體D_o處於逆向偏壓，此時由輸出濾波電容C_o提供能量給負載L。 In FIG. 4A, the flyback converter 31 is in a state between t=t ₀ to t ₁ (t ₀

t

t ₁ ), the lower arm switch S ₁ is turned on, and the current flows through the transformer from the input power supply V _in . At this time, the magnetizing inductance L _m increases linearly. Since the polarity of the primary side N ₁ of the transformer is opposite to that of the secondary side N ₂ , the output rectifier two Pole body D _o is in reverse bias, at this time the output filter capacitor C _o provides energy to the load L.

t

t₂)，下臂開關S₁截止，此時變壓器上之漏感L_r所儲存的能量無法耦合至次級側N₂，該能量此時會與主開關S₁上寄生電容C_oss1諧振，此時變壓器初級側N₁與次級側N₂進行轉態，輸出整流二極體D_o同樣處於逆向偏壓，此時能量由輸出濾波電容C_o提供。 In FIG. 4B, the flyback converter 31 is in a state between t=t ₁ to t ₂ (t ₁

t

t ₂ ), the lower arm switch S ₁ is turned off, at this time the energy stored in the leakage inductance L _r on the transformer cannot be coupled to the secondary side N ₂ , and the energy will resonate with the parasitic capacitance C _oss1 on the main switch S ₁ at this time, At this time, the primary side _N1 and the secondary side _N2 of the transformer are in transition, and the output rectifier diode D _o is also in reverse bias, and the energy is provided by the output filter capacitor C _o at this time.

t

t₃)，下臂開關S₁截止，變壓器中磁通方向不變，為了使激磁電感L_m上能量耦合至次級側N₂，電感電流需保持連續，導致電感電壓極性轉態，二次側電壓瞬間反向，因此輸出整流二極體D_o導通，變壓器儲存的能量進入輸出濾波電容C_o和輸出負載L。 In FIG. 4C, the flyback converter 31 is in a state between t=t ₂ to t ₃ (t ₂

t

t ₃ ), the lower arm switch S ₁ is turned off, and the direction of the magnetic flux in the transformer remains unchanged. In order to couple the energy on the magnetizing inductance L _m to the secondary side N ₂ , the inductance current must be kept continuous, resulting in a polarity transition of the inductance voltage, and the secondary The side voltage is instantly reversed, so the output rectifier diode D _o is turned on, and the energy stored in the transformer enters the output filter capacitor C _o and the output load L.

t

t₄)，變壓器中的能量已經完全傳遞至二次側，次級電流I_D下降至零，電路即進入不連續模式，此區間有一空檔時間存在，導致激磁電感L_m與寄生電容C_oss1產生了諧振現象，而返馳式轉換器31便是利用諧振時電壓降到波谷時，將功率開關導通，來降低導通時損失提高效率。此時能量由輸出濾波電容C_o提供給負載L。 In FIG. 4D, the flyback converter 31 is in a state between t=t ₃ and t ₄ (t ₃

t

t ₄ ), the energy in the transformer has been completely transferred to the secondary side, the secondary current _ID drops to zero, and the circuit enters the discontinuous mode. There is a gap time in this interval, resulting in the excitation inductance L _m and the parasitic capacitance C _oss1 The resonance phenomenon occurs, and the flyback converter 31 uses the voltage drop to the valley during resonance to turn on the power switch to reduce the loss during turn-on and improve the efficiency. At this time, the energy is provided to the load L by the output filter capacitor C _o .

Please refer to FIG. 5A to FIG. 5F , which are schematic diagrams of the active clamp mode operation of the embodiment of the present invention. The active clamp flyback converter uses an auxiliary switch and a clamp capacitor to replace the traditional damping circuit, which can not only eliminate the high-voltage surge on the power switch, but also absorb the leakage inductance energy, so that the two power switches can reach zero. voltage switching. Please refer to FIG. 6 at the same time. FIG. 6 is an operation timing diagram of a dual-mode flyback converter according to an embodiment of the present invention.

t

t₆)，下臂開關S₁導通，上臂開關S₂截止，此時激磁電感L_m與諧振電感L_r皆呈線性充電，激磁電感電流等於諧振電感電流(i_Lr(t)=i_Lm(t))，變壓器一次側電壓約等於輸入電壓(V_pri(t)

V_in)，由於變壓器初級側N₁與次級側N₂極性相反，因此輸出整流二極體D_o處於逆向偏壓，此時由輸出濾波電容C_o提供能量給負載L。 In FIG. 5A, the flyback converter 41 is in a state between t= _t5 to _t6 ( _t5

t

t ₆ ), the lower arm switch S ₁ is turned on, and the upper arm switch S ₂ is turned off. At this time, the magnetizing inductance L _m and the resonant inductance L _r are charged linearly, and the magnetizing inductance current is equal to the resonant inductor current (i _Lr (t)=i _Lm ( t)), the transformer primary side voltage is approximately equal to the input voltage (V _pri (t)

V _in ), since the polarity of the primary side N ₁ of the transformer is opposite to that of the secondary side N ₂ , the output rectifier diode D _o is in reverse bias, and the output filter capacitor C _o provides energy to the load L at this time.

t

t₇)，下臂開關S₁截止，為了使iLm續流，採以LC串聯諧振方式對寄生電容C_oss1充電，此時V_DS(S1)跨壓由零充電至V_in+V_clamp，此時上臂開關S₂之寄生電容C_oss2會對激磁電感L_m與諧振電感L_r放電，且諧振電感L_r與激磁電感L_m能量遠大於寄生電容C_oss2上的能量，故上臂開關S₂之寄生電容C_oss2電壓被放電至零，因電感電流必須連續，此時上臂開關S₂之寄生二極體(Body Diode)導通，而箝位電容C_clamp能量遠大於諧振電容，原先儲存在激磁電感L_m與諧振電感L_r的能量將沿著上臂開關S₂之本質二極體流向箝位電容C_clamp充電，此時輸出整流二極體D_o尚未導通，此時由輸出濾波電容C_o提供能量給負載L。 In FIG. 5B, the flyback converter 41 is in a state between t= _t6 to _t7 ( _t6

t

t ₇ ), the lower arm switch S ₁ is turned off. In order to make iLm continue to flow, the parasitic capacitor C _oss1 is charged by LC series resonance. At this time, V _DS(S1) is charged from zero to V _in +V _clamp , and At this time, the parasitic capacitance C _oss2 of the upper arm switch S ₂ will discharge the excitation inductance L _m and the resonant inductance L _r , and the energy of the resonant inductance L _r and the excitation inductance L _m is much greater than the energy of the parasitic capacitance C _oss2 , so the upper arm switch S ₂ The voltage of the parasitic capacitor C _oss2 is discharged to zero, because the inductor current must be continuous, at this time the parasitic diode (Body Diode) of the upper arm switch S ₂ is turned on, and the energy of the clamp capacitor C _clamp is much greater than the resonant capacitor, which was originally stored in the excitation inductance The energy of L _m and resonant inductance L _r will flow along the essential diode of the upper arm switch S ₂ to charge the clamp capacitor C _clamp . At this time, the output rectifier diode D _o is not turned on, and it is provided by the output filter capacitor C _o Energy is given to the load L.

t

t₈)，上臂開關S₂導通，下臂開關S₁截止。因在前一狀態三時上臂開關S₂的本質二極體被導通，此時將上臂開關S₂導通，即可實現上臂開關S₂達成零電壓切換。在此狀 態下，諧振電路由諧振電感L_r與箝位電容C_clamp所構成，諧振電感電流i_Lr對箝位電容C_clamp充電。此時變壓器一次側電壓為V_pri，因變壓器極性轉態使次極側N₂的輸出整流二極體D_o導通，傳遞能量給二次側的輸出電容C_o與負載L。 In Fig. 5C, the flyback converter 41 is in a state between t= _t7 to _t8 ( _t7

t

t ₈ ), the upper arm switch S ₂ is turned on, and the lower arm switch S ₁ is turned off. Since the essential diode of the upper arm switch _S2 is turned on in the previous state three, turning on the upper arm switch _S2 at this time can realize zero-voltage switching of the upper arm switch _S2 . In this state, the resonant circuit is composed of the resonant inductor L _r and the clamping capacitor C _clamp , and the resonant inductor current i _Lr charges the clamping capacitor C _clamp . At this time, the voltage on the primary side of the transformer is V _pri . Due to the polarity transition of the transformer, the output rectifier diode D _o on the secondary side N ₂ is turned on, and energy is transferred to the output capacitor C _o on the secondary side and the load L.

t

t₉)，上臂開關S₂持續導通，因上一狀態諧振電感L_r已將能量傳給箝位電容C_clamp，此時箝位電容電流i_clamp=0，因上臂開關S₂導通，故箝位電容C_clamp將能量回傳給諧振電感L_r，由於轉換器操作於不連續導通模式(DCM)，故諧振電感電流會由正值轉為負值，此狀態持續直到上臂開關S₂截止。 In FIG. 5D, the flyback converter 41 is in a state between t=t ₈ to t ₉ (t ₈

t

t ₉ ), the upper arm switch S ₂ is continuously turned on, because the resonant inductance L _r has transferred energy to the clamping capacitor C _clamp in the previous state, at this time, the clamping capacitor current i _clamp =0, because the upper arm switch S ₂ is turned on, so the clamp The bit capacitor C _clamp transfers energy back to the resonant inductor L _r . Since the converter operates in discontinuous conduction mode (DCM), the resonant inductor current will change from a positive value to a negative value. This state lasts until the upper arm switch S ₂ is turned off.

t

t₁₀)，下臂開關S₁與上臂開關S₂都已截止，此時諧振電感電流i_Lr依然為負值，因此諧振電感L_r以串連諧振方式對下臂開關S₁之寄生電容C_oss1放電，同時諧振電感L_r對上臂開關S₂之寄生電容C_oss2充電，當激磁電感電流i_Lm下降至等於諧振電感電流i_Lr時，輸出二極體D_o將會截止。 In FIG. 5E, the flyback converter 41 is in a state between t=t ₉ to t ₁₀ (t ₉

t

t ₁₀ ), the lower arm switch S ₁ and the upper arm switch S ₂ are both turned off. At this time, the resonant inductor current i _Lr is still negative, so the resonant inductor L _r acts on the parasitic capacitance C of the lower arm switch S ₁ in a series resonance manner. _oss1 discharges, and at the same time, the resonant inductance L _r charges the parasitic capacitance C _oss2 of the upper arm switch _S2 . When the exciting inductance current i _Lm drops to equal to the resonant inductance current i _Lr , the output diode D _o will be cut off.

t

t₁₁)，此時下臂開關S₁、上臂開關S₂與輸出二極體D_o截止，下臂開關S₁之寄生電容C_oss1會以LC串聯諧振方式持續對諧振電感L_r與激磁電感L_m放電，直到電壓下降至零，讓下臂開關S₁達成零電壓導通的條件，同時上臂開關S₂電壓將充電。由於下臂開關S₁之寄生電容C_oss1放電至零，因電感電流i_Lr連續，因此使下臂開關S₁之本質二極體(Body Diode)導通，下臂開關S₁在t=t₁₁時導通，具有零電壓切換的效果，其動作點又回到t₅開始循環。 In FIG. 5F, the flyback converter 41 is in a state between t=t ₁₀ to t ₁₁ (t ₁₀

t

t ₁₁ ), at this moment, the lower arm switch S ₁ , the upper arm switch S ₂ and the output diode D _o are cut off, and the parasitic capacitance C _oss1 of the lower arm switch S ₁ will continue to affect the resonant inductance L _r and the magnetizing inductance in the form of LC series resonance L _m discharges until the voltage drops to zero, allowing the lower arm switch _S1 to achieve zero-voltage conduction conditions, and the upper arm switch _S2 voltage will be charged at the same time. Since the parasitic capacitance C _oss1 of the lower arm switch S ₁ is discharged to zero, the inductor current i _Lr is continuous, so the intrinsic diode (Body Diode) of the lower arm switch S ₁ is turned on, and the lower arm switch S ₁ is at t=t ₁₁ When it is turned on, it has the effect of zero voltage switching, and its action point returns to t ₅ to start the cycle.

Please refer to FIG. 6. FIG. 6 is an operation timing diagram of a dual-mode flyback converter according to an embodiment of the present invention. As shown in the figure, at light load, the flyback converter operates in quasi-resonant mode, and its operation sequence is from t=t ₀ to t ₄ , including the energy storage area, the inductor providing energy to the load, and the quasi-resonant area . When turning to heavy load, the flyback converter operates in active clamping mode, and its operation timing is between t=t ₅ to t ₁₁ . Through the dual-mode switching, the flyback converter has the advantage of zero-voltage switching, and can optimize the conversion efficiency of the input voltage at light load.

The above descriptions are illustrative only, not restrictive. Any equivalent modification or change made without departing from the spirit and scope of the present invention shall be included in the scope of the appended patent application.

11: flyback converter

12: Comparator

13: First controller

14: Second controller

15: Current sensor

16: Pulse Width Modulation Controller

17: Frequency resonance controller

18: Delay circuit

100: Dual Mode Flyback Converter

D _RVm : delayed signal

FB: feedback circuit

L: load

V _C1 : comparison signal

V _comp : Feedback comparison signal

V _FB : Feedback signal

V _GSD1 : lower arm control signal

V _GSD2 : upper arm control signal

V _GS1 : Lower arm delay signal

V _GS2 : upper arm delay signal

V _in : input voltage

V _PWM : pulse signal

V _ref : Reference voltage

V _RESET : reset signal

V _sense1 : sense voltage

V _sense2 : output voltage

Claims (6)

A dual-mode flyback converter, which includes: a flyback converter that receives an input voltage and outputs an output voltage according to it, the flyback converter includes a first switch and a second switch; a comparison device, connected to the flyback converter, and outputs a comparison signal according to the output voltage and a reference voltage; a first controller, connected between the comparator and the first switch; and a second controller, connected between the comparator and the second switch; wherein, when the flyback converter is under light load, the first controller and the second controller respectively turn off the first switch according to the comparison signal and the second switch are turned on to make the flyback converter operate in a quasi-resonant mode; when the flyback converter is under heavy load, the first controller and the second controller respectively make the The first switch is turned on and the second switch is turned off, so that the flyback converter operates in an active clamp mode. The dual-mode flyback converter as claimed in Claim 1 further comprises a current sensor, and the current sensor converts an output current into the output voltage. The dual-mode flyback converter as claimed in claim 1, further comprising a first driver and a second driver, the first driver is connected between the first switch and the first controller, the second driver connected between the second controller and the second switch, the first driver controls the conduction of the first switch according to the output of the first controller, and the second driver controls the conduction of the first switch according to the output of the second controller The conduction of the second switch. The dual-mode flyback converter as claimed in claim 1, wherein the first controller and the second controller respectively include a plurality of logic gates. The dual-mode flyback converter as claimed in claim 1, further comprising a pulse width modulation controller connected between the first controller and the flyback converter , when the flyback converter is under light load, the first controller outputs a reset signal to the pulse width modulation controller, and the pulse width modulation controller receives the flyback converter A sensing voltage, the pulse width modulation controller outputs a pulse signal according to the reset signal and the sensing voltage. The dual-mode flyback converter as claimed in item 5, further comprising a frequency resonance controller, the frequency resonance controller is connected between the pulse width modulation controller and the second controller, the frequency resonance The controller outputs a delay signal to the second controller according to the pulse signal.

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