1311350 97-06-10 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝的測試方法，且特別 是有關於一種球格陣列式(BGA)封裝的測試方法。 【先前技術】 電子工業是近年來發展速度最快之重要的工業之 一 ’它逐漸地改變世界並且提供許多影響我們日常生活的 產例如丫了動電g舌、電腦、視聽產品等產品，爲了達到 輕、薄、短、小的趨勢，所使用的主要電子元件均以半導 體封裝爲主流，而上述關鍵技術之一就是電子構裝 (Electronic Packaging)，因此諸多高密度、高效能的半 導體封裝結構也就因應而生。其中，特別是以具有面陣列 (area array)之球格陣列式（Ball Grid Array，BGA)封裝結 構或針格陣列式(Pin Grid Array，PGA)封裝結構，爲目前半 導體封裝結構的主流。 以球格陣列式(BGA)封裝結構而言，常見以有機基板 (organic substrate)或陶瓷基板（ceramic substrate)作爲晶片 之承載器(carrier)，而晶片配置於承載器之後，晶片之電子 訊號可藉由承載器之內部線路而向下繞線（routing)至承 載器之底面，最後經由承載器之銲球(s〇lder bal1)而傳遞至 外界的電子裝置。由於承載器具有佈線密集、訊號傳輸路 徑短、電氣特性良好等優點，因此廣泛成爲晶片封裝結構 之構件之一，且銲球係以面陣列的方式形成於承載器之底 5 1311350 97-06-10 面，因此一直是高腳位(High pin count)半導體元件常用的 封裝結構。 一般而言，在完成晶片與承載器之封裝製程之後，會 依照所指定的各項測試流程，對封裝完成之成品進行成品 測試(Final test)，以檢測出不符合品質要求之半導體封裝成 π口。其中’成品測試之流程包括產品外觀品質檢測(incoming Quality Assurance，IQA)、功會g性測試（Function Test)、老化 測試（Burn-in Test)以及開路/通路測試（Open/Short Test) 等。下文針對習知球格陣列式(BGA)封裝的測試方法作進一 步的說明。 請同時參考第1A〜1B圖，其中第1A圖繪示習知球格 陣列式封裝之測試方法的流程方塊圖，而第1B圖繪示習知 球格陣列式封裝之測試方法的示意圖。首先如步驟S10所 市，提供一球格陣列式封裝成品的待測物（Device Under Test，DUT)100，並以目測或影像檢測的方式，對球格陣列 式封裝成品之待測物100進行產品外觀品質檢測(IQA)，以 初步篩選合格之待測物100，接著如步驟S20所示，針對此 待測物100進行一功能性測試，其方式例如以一探針卡 (Probe Card)10接觸待測物100之銲球110，並在常溫狀態 下讓此待測物100正常運作，最後將探針卡10所得到之測 試結果傳回測試機台(Tester)，以進行待測物100之電性特 性的分析以及偵錯。 接著如步驟S30所示，對此待測物100進行一老化測 試，其方式例如在高溫(攝氏約I25度)的環境中進行，並且 外界提供超過待測物1〇〇工作電壓、電流的電功率。由於 1311350 97-06-10 待測物100在超出其正常運作之環境下進行測試’因此會 加速待測物100之電性特性、工作速度的老化。最後’可 藉由老化測試所得到的數據來推斷出此待測物100之正常 工作壽命。當完成老化測試之後’接著如步驟S40所示’ 對此待測物100進行一開路/通路測試’其方式係將待測物 100於一通電狀態下，以確定待測物100之內部線路的開路 狀態或通路狀態是否正常。 同樣請參考第1B圖，在進行BGA封裝成品之待測物 100的成品測試時，先將待測物100放置於老化插座(burn-in socket)20上，且探針卡1〇係以多個陣列排列之爪型探針 12來分別夾持待測物1〇〇之銲球11〇 ’其中銲球11〇例如 爲錫鉛（Sn/Pb)合金。値得注意的是，錫鉛合金具有低熔點 的特性，可作爲絕佳的焊接材料’然而在進行老化測試時， 係在攝氏125度的高溫環境下進行’且高功率負載之晶片 120更使待測物100內部產生高熱，致使錫鉛銲球110在環 境高溫以及高功率所產生之高熱下，其溫度非常接近錫鉛 合金的熔點(約180度）。一方面，銲球11〇的硬度隨溫度升 高而降低，另一方面，銲球110受到爪型探針12之夾持而 產生變形，以至於完成老化測試之後，銲球110因變形而 損傷，並影響後續製程之良率，更不利於此BGA封裝成品 與外界電子裝置如電路板、主機板等結合之可靠度。 【發明内容】 因此，本發明的目的就是在提供一種球格陣列式封裝 的測試方法，用以解決銲球因老化測試而變形，進一步改 善其後續製程之良率及可靠度。 7 1311350 97-06-10 爲達上述目的，本發明提出一種球格陣列式封裝的測 試方法。首先，提供一球格陣列式封裝半成品，其係由一 承載器、一晶片及一封裝材料所組成，其中承載器具有— 第一表面及對應之一第二表面，第一表面具有多個接點分 別與晶片電性連接，而第二表面具有多個銲球墊，而封裝 材料包覆晶片及部分第一表面；接著對球格陣列式封裝半 成品進行一功能性測試；接著對球格陣列式封裝半成品進 行一老化測試；將多個銲球，分別植接於這些銲球墊，以 形成一球格陣列式封裝；最後對球格陣列式封裝進行一開 路/通路測試。 爲達上述目的，本發明提出一種球格陣列式封裝的測 試方法。首先，提供一球格陣列式封裝半成品，此球格陣 列式封裝半成品包括一承載器、多個晶片以及一封裝材 料。其中’承載器具有多個封裝單元，而承載器具有一第 一表面及對應之一第二表面，每一封裝單元之第一表面具 有多個接點’而第二表面具有多個銲球墊，這些接點分別 與銲球墊電性連接。晶片係分別配置於這些封裝單元，並 與對應的這些封裝單元之接點電性連接。封裝材料係分別 包覆晶片及封裝單元的部分第一表面。接著對球格陣列式 封裝半成品進行一功能性測試；接著對球格陣列式封裝半 成品進行一老化測試；接著將多個銲球，分別植接於這些 靜球墊’以形成多個球格陣列式封裝；最後將這些球格陣 列式封裝分離’以形成個別獨立的球格陣列式封裝。 依照本發明的較佳實施例所述，上述之功能性測試之 前還包括進行一產品外觀品質檢測。此外，老化測試係以 8 1311350 97-06-10 多個探針，分別接觸這些銲球墊’以進行測試。另外’開 路/通路測試係以多個爪型探針’分別夾持這些銲球’以進 行測試。 本發明因以BGA封裝半成品爲待測物’以進行功能 性測試以及老化測試，並在完成老化測試之後’再植接銲 球於承載器之銲球墊上，由於銲球於老化測試之後才形 成，因此銲球不會受到損傷，故可提高後續製程之良率， 更可改善BGA封裝成品與外界電子裝置如電路板、主機板 等結合之可靠度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 請同時參考第2圖及第3A〜3C圖，其中第2圖繪示依 照本發明一較佳實施例之一種球格陣列式封裝的測試方法 的流程方塊圖，而第3A〜：3C圖依序繪示本發明之球格陣列 式封裝之測試方法的示意圖。 首先如步驟sίο所示，提供一球格陣列式(BGA)封裝 半成品的待測物2〇〇，其係由一承載器210、一晶片22〇及 一封裝材料23〇所組成。晶片2;2〇配置於承載器21〇之第 一，面212上，而封裝材料23〇係可包覆晶片22〇以及部 份第一表面以2。此外，承載器21〇之第一表面212具有多 女點2U分別與晶片22〇電性連接，且承載器21〇之第 一表面2U具有多個銲球墊以8。上述在完成晶片22〇與承 9 1311350 97-06-10 載器210之封裝製程之後，會依照所指定的各項測試流程’ 對此待測物200進行測試。其中，測試的流程包括產品外 觀品質檢測(IQA)、功能性測試(Function Test)、老化測試 (Birni-in Test)以及開路/通路測試(Open/Short Test)等。下文 針對本發明之球格陣列式封裝的測試方法作進一步的說 明。 値得注意的是，由於待測物200之第二表面216暴露 出銲球墊218，且銲球墊218尙未配置銲球，因此本發明可 藉由平面格陣列(Land Grid Array)封裝所使用之探針卡來 進行步驟S20所示之功能性測試。如第3A圖所示，其方式 係以一探針卡30之多個探針32來接觸銲球墊218,而探針 32的頂端分別接觸待測物200之銲球墊218，並在常溫狀 態下讓此待測物200正常運作，最後經由探針卡30所得到 之測試結果傳回測試機台（Tester)，以進行待測物200之電 性特性的分析以及偵錯。 接著如步驟幻0所示，對待測物200進行一老化測 試，其方式如第3A圖所示，先將待測物200放置於一插座 (socket)20上，在高溫(攝氏約125度)的環境中進行，並且 外界提供超過待測物200工作電壓、電流的電功率，以進 行老化測試。接著請同時參考步驟S4〇及第3B圖，完成老 化測試之後，再將多個銲球240，分別植接於承載器210 之銲球墊218上’以形成一球格陣列式(BGA)封裝的成品 2〇2。値得注意的是，由於銲球24〇於老化測試之後才形成， 因此銲球240不會產生變形，故可提高後續之製程的良率。 接著請同時參考步驟S5〇及第3C圖，進行一開路/通 .1311350 97-06-10BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a test method for a semiconductor package, and more particularly to a test method for a ball grid array (BGA) package. [Prior Art] The electronics industry is one of the fastest growing industries in recent years. 'It gradually changes the world and provides many products that affect our daily lives, such as electric power, computers, audio-visual products, etc. Achieving the trend of light, thin, short and small, the main electronic components used are mainly semiconductor packaging, and one of the above key technologies is electronic packaging, so many high-density, high-performance semiconductor packaging structures It is also born in response. Among them, in particular, a Ball Grid Array (BGA) package structure or a Pin Grid Array (PGA) package structure having an area array is the mainstream of the current semiconductor package structure. In the case of a ball grid array (BGA) package structure, an organic substrate or a ceramic substrate is generally used as a carrier of the wafer, and after the wafer is disposed on the carrier, the electronic signal of the chip can be It is routed down to the bottom surface of the carrier by the internal wiring of the carrier, and finally transmitted to the external electronic device via the solder ball of the carrier. Because the carrier has the advantages of dense wiring, short signal transmission path, good electrical characteristics, etc., it is widely used as one of the components of the chip package structure, and the solder ball is formed in the surface array on the bottom of the carrier. 5 1311350 97-06- 10 faces, so it has always been a common package structure for high pin count semiconductor components. Generally, after the wafer and carrier packaging process is completed, the finished product is subjected to a final test in accordance with the specified test procedures to detect a semiconductor package that does not meet the quality requirements. mouth. Among them, the process of finished product testing includes the incoming quality assurance (IQA), the function test, the burn-in test, and the open/short test. The following is a further description of the test method for a conventional ball grid array (BGA) package. Please refer to FIG. 1A to FIG. 1B, wherein FIG. 1A is a flow block diagram of a conventional ball grid array package test method, and FIG. 1B is a schematic view showing a test method of a conventional ball grid array package. First, as shown in step S10, a device under test (DUT) 100 of a ball grid array package is provided, and the object to be tested 100 of the ball grid array package is subjected to visual inspection or image detection. The product appearance quality test (IQA) is used to initially screen the qualified test object 100, and then, as shown in step S20, perform a functional test on the test object 100, for example, by using a probe card 10 The solder ball 110 of the object to be tested 100 is contacted, and the object to be tested 100 is normally operated under normal temperature conditions. Finally, the test result obtained by the probe card 10 is transmitted back to the tester (Tester) to perform the object to be tested 100. Analysis of electrical characteristics and debugging. Then, as shown in step S30, an aging test is performed on the object to be tested 100, for example, in an environment of high temperature (about 125 degrees Celsius), and the external power is supplied to exceed the operating voltage and current of the object to be tested. . Since the 1310350 97-06-10 test object 100 is tested in an environment beyond its normal operation, the electrical characteristics of the test object 100 and the aging of the working speed are accelerated. Finally, the normal working life of the test object 100 can be inferred from the data obtained from the burn-in test. After the aging test is completed, 'there is an open circuit/path test for the object to be tested 100 as shown in step S40'. The method is to place the object to be tested 100 in an energized state to determine the internal line of the object to be tested 100. Whether the open state or the path status is normal. Please also refer to FIG. 1B. When performing the finished product test of the BGA packaged finished object 100, the object to be tested 100 is first placed on the burn-in socket 20, and the probe card 1 is mostly The array of claw probes 12 are arranged to respectively hold the solder balls 11' of the object to be tested, wherein the solder balls 11 are, for example, tin-lead (Sn/Pb) alloys. It is worth noting that tin-lead alloys have a low melting point and can be used as an excellent soldering material. However, in the aging test, the high-power load of the wafer 120 is performed at a high temperature of 125 degrees Celsius. The inside of the object to be tested 100 generates high heat, so that the temperature of the tin-lead solder ball 110 is very close to the melting point of the tin-lead alloy (about 180 degrees) under the high temperature generated by the high temperature and high power. On the one hand, the hardness of the solder ball 11 降低 decreases as the temperature increases, and on the other hand, the solder ball 110 is deformed by the clamping of the claw probe 12, so that the solder ball 110 is damaged due to deformation after the aging test is completed. And affect the yield of subsequent processes, which is not conducive to the reliability of the combination of BGA packaged products and external electronic devices such as circuit boards and motherboards. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a ball grid array package test method for solving the deformation of a solder ball due to an aging test, and further improving the yield and reliability of the subsequent process. 7 1311350 97-06-10 To achieve the above object, the present invention provides a test method for a grid array package. First, a ball grid array package semi-finished product is provided, which is composed of a carrier, a wafer and a packaging material, wherein the carrier has a first surface and a corresponding one of the second surfaces, the first surface has a plurality of connections The points are electrically connected to the wafer, and the second surface has a plurality of solder ball pads, and the encapsulating material covers the wafer and a portion of the first surface; then performing a functional test on the ball grid array package semi-finished product; The packaged semi-finished product is subjected to an aging test; a plurality of solder balls are respectively implanted on the solder ball pads to form a ball grid array package; and finally, an open circuit/pass test is performed on the ball grid array package. To achieve the above object, the present invention provides a test method for a grid array package. First, a ball grid array package semi-finished product is provided. The ball array package semi-finished product includes a carrier, a plurality of wafers, and a package material. Wherein the carrier has a plurality of package units, and the carrier has a first surface and a corresponding one of the second surfaces, the first surface of each package unit has a plurality of contacts and the second surface has a plurality of solder ball pads. These contacts are electrically connected to the solder ball pads, respectively. The wafers are respectively disposed on the package units, and are electrically connected to the contacts of the corresponding package units. The encapsulating material respectively covers a portion of the first surface of the wafer and the package unit. Next, a functional test is performed on the ball grid array package semi-finished product; then an aging test is performed on the ball grid array package semi-finished product; then, a plurality of solder balls are respectively implanted on the static ball pads to form a plurality of ball grid arrays. Packages; these ball grid array packages are finally separated 'to form individual independent ball grid array packages. According to a preferred embodiment of the present invention, the functional test described above also includes performing a product appearance quality test. In addition, the aging test was performed by contacting multiple probes with 8 1311350 97-06-10 probes respectively. In addition, the 'open/pass test is performed by sandwiching these solder balls with a plurality of claw probes' for testing. The invention adopts the BGA package semi-finished product as the object to be tested to perform the functional test and the aging test, and after the aging test is completed, the ball is re-planted on the solder ball pad of the carrier, and the solder ball is formed after the aging test. Therefore, the solder ball is not damaged, so the yield of the subsequent process can be improved, and the reliability of the combination of the BGA packaged product and external electronic devices such as a circuit board and a motherboard can be improved. The above and other objects, features, and advantages of the present invention will become more apparent and understood. 3A to 3C, wherein FIG. 2 is a block diagram showing a method for testing a ball grid array package according to a preferred embodiment of the present invention, and FIGS. 3A to 3C are sequentially showing the present invention. Schematic diagram of the test method for the grid array package. First, as shown in the step sίο, a ball grid array (BGA) packaged semi-finished object to be tested is provided, which is composed of a carrier 210, a wafer 22, and a package material 23A. The wafer 2; 2 is disposed on the first surface 212 of the carrier 21, and the encapsulating material 23 is coated on the wafer 22 and the first surface of the portion is 2. In addition, the first surface 212 of the carrier 21 has a plurality of female points 2U electrically connected to the wafer 22, and the first surface 2U of the carrier 21 has a plurality of solder ball pads 8 . After the completion of the packaging process of the wafer 22 and the carrier 21 210, the test object 200 is tested according to the specified test procedures. Among them, the testing process includes product appearance quality inspection (IQA), functional test (Function Test), aging test (Birni-in Test) and open/short test (Open/Short Test). The test method of the ball grid array package of the present invention is further described below. It should be noted that since the second surface 216 of the object to be tested 200 exposes the solder ball pad 218, and the solder ball pad 218 is not provided with solder balls, the present invention can be packaged by a Land Grid Array. The probe card used in step S20 is used for the functional test. As shown in FIG. 3A, the solder ball pad 218 is contacted by a plurality of probes 32 of a probe card 30, and the top ends of the probes 32 respectively contact the solder ball pads 218 of the object to be tested 200 at room temperature. The test object 200 is normally operated in the state, and finally the test result obtained by the probe card 30 is transmitted back to the test machine (Tester) for analyzing and detecting the electrical characteristics of the test object 200. Then, as shown in step illusion 0, the aging test is performed on the object to be tested 200 in the manner shown in FIG. 3A, and the object to be tested 200 is first placed on a socket 20 at a high temperature (about 125 degrees Celsius). The environment is carried out, and the external power is supplied to exceed the working voltage and current of the object to be tested 200 for the aging test. Then, referring to steps S4 and 3B, after the aging test is completed, a plurality of solder balls 240 are respectively implanted on the solder ball pads 218 of the carrier 210 to form a ball grid array (BGA) package. The finished product is 2〇2. It is noted that since the solder balls 24 are formed after the aging test, the solder balls 240 are not deformed, so the yield of subsequent processes can be improved. Then please refer to steps S5〇 and 3C at the same time for an open circuit/pass. 1311350 97-06-10
路測S式，將BGA封裝之成品202於一通電狀態下，並且婷 球240可分別以一探針卡40之多個爪型探針42夾持，以 進行測試，用以確定此BGA封裝之成品2〇2的內部線路的 通路狀憩或開路狀態是否正常。此時，由於銲球240在常 溫下不會因爪型探針42夾持而變形，因此有利於改善BGA 封裝之成品2〇2與外部電子裝置如電路板或主機板連接時 之可靠度。 請參照第4A〜4C圖，其繪示依照本發明—較佳實施例 之另一種球格陣列式(BGA)封裝的測試方法的示意圖。請參 考4A圖，以目前生產與製作流程而言，爲符合大量生產之 求以及簡化承載器之製作’通常在單一片大面積之承載 器310上先製作多個封裝單元31〇a(僅繪示其二），而每一 封裝單兀310a之第一表面3丨2具有多個接點314，且第二 表面316具有多個銲球墊3 18,這些接點314可藉由封裝單 兀310a內部之線路而分別電性連接至這些舞球墊318。之 後再將多個晶片320以及封裝材料do配置於承載器31〇 上’其中晶片320分別與封裝單元310a之接點314電性連 接，而封裝材料330係分別包覆這些晶片32〇及封裝單元 310a的部份第一表面312。上述在完成晶片320與承載器 3 10之封裝製程之後，會依照所指定的各項測試流程，對此 球格陣列式封裝半成品的待測物3〇〇進行測試。其中，測 試的流程包括產品外觀品質檢測（IQA)、功能性測試 (Function Test)、老化測試(Burn-in Test)以及開路/通路測試 (Open/Short Test)等。 値得注意的是，由於待測物300之第二表面316暴露 11 1311350 97-06-10 出銲球墊318，而銲球墊318尙未配置銲球，因此本發明可 藉由平面格陣列(Land Grid Array)封裝所使用之探針卡來 進行一功能性測試，其測試方法如上所述，如第4A圖所 不’同樣以一探針卡40之多個探針42來接觸封裝單元310a 之銲球墊318。接著對待測物3〇〇進行一老化測試，其方式 同樣在高溫(攝氏約I25度）的環境中進行，並且外界提供超 過待測物工作電壓、電流的電功率，以進行老化測試。接 著請參考第4B圖，完成老化測試之後，再將多個銲球“ο， 分別植接於承載器310之銲球墊318上，以形成多個球格 陣列式(BGA)封裝3〇2。最後如第4C圖所示，再進行切單 (singulation)的步驟’將球格陣列式封裝3〇2分離，以形成 個別獨立的BGA封裝之成品304。 此外’請參考第3D圖’在分離這些BGA封裝之成品 304之後，還可對每一 BGA封裝的成品3〇4進行一開路/ 通路測試，其方式係將BGA封裝之成品304於一通電狀態 下，並且銲球340可分別以一探針卡50之多個爪型探針52 夾持，以進行測試，用以確定此BGA封裝之成品3‘〇4之內 部線路的開路狀態或通路狀態是否正常。 綜上所述，本發明之球格陣列式封裝的測試方法乃是 藉由成品測試之分析測試結果，來判斷出不符合要求之封 裝產品’其中於功能性測試以及老化測試之後，再將靜球 植接於球格陣列式封裝半成品的銲球墊上，接著再進行開 路/通路測試。由於銲球在老化測試之後才形成於銲球墊 上，因此在後段的開路/通路測試過程中，銲球不會因爪型 探針夾持而產生變形，故可提高後續製程之良率，且改善 12 1311350 97-06-10 球格陣列式封裝之成品與外界電子裝置結合之可靠度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1A圖繪示習知球格陣列式封裝之測試方法的流程 方塊圖。 第1B圖繪示球格陣列式封裝之測試方法的示意圖。 第2圖繪示依照本發明一較佳實施例的一種球格陣列 式封裝的測試方法的流程方塊圖 第3A〜3C圖依序繪示本發明之球格陣列式封裝之測 試方法的示意圖。 第4A〜4C圖繪示依照本發明一較佳實施例之另一種 球格陣列式封裝的測試方法的示意圖。 【主要元件符號說明】 10、30、40、50 :探針卡 12、32、42、52 :探針 20 :插座 100、200、300 :待測物 110 :銲球 120 __晶片 202、302 :球格陣列式封裝 13 1311350 97-06-10 210、310 :承載器 212 ' 312 :第一表面 214、314 :接點 216、316 :第二表面 218、318 :銲球墊 220、320 :晶片 230、330 :封裝材料 240、340 :銲球 310a :封裝單元 S10、S20 ' S30、S40、S50 :步驟 14The road test S type, the BGA packaged product 202 is in an energized state, and the Ting ball 240 can be clamped by a plurality of claw probes 42 of a probe card 40 for testing to determine the BGA package. Whether the channel-like or open state of the internal circuit of the finished product 2〇2 is normal. At this time, since the solder ball 240 is not deformed by the claw type probe 42 at normal temperature, it is advantageous in improving the reliability of the connection of the finished product 2〇2 of the BGA package to an external electronic device such as a circuit board or a motherboard. Please refer to FIGS. 4A-4C for a schematic diagram of a test method for another ball grid array (BGA) package in accordance with the present invention. Please refer to FIG. 4A. In order to meet the requirements of mass production and simplify the manufacture of the carrier in the current production and production process, a plurality of package units 31〇a are usually fabricated on a single-chip large-area carrier 310. Show second), and the first surface 3丨2 of each package unit 310a has a plurality of contacts 314, and the second surface 316 has a plurality of solder ball pads 3 18, which can be packaged by a single unit The wires inside 310a are electrically connected to the dance pads 318, respectively. Then, the plurality of wafers 320 and the package material do are disposed on the carrier 31, wherein the wafers 320 are electrically connected to the contacts 314 of the package unit 310a, respectively, and the package material 330 respectively covers the wafers 32 and the package units. A portion of the first surface 312 of 310a. After completing the packaging process of the wafer 320 and the carrier 3 10, the object to be tested of the ball grid array package semi-finished product is tested according to the specified test procedures. Among them, the test process includes product appearance quality inspection (IQA), functional test (Function Test), burn-in test (Burn-in Test) and open/short test (Open/Short Test). It should be noted that since the second surface 316 of the object to be tested 300 exposes 11 1311350 97-06-10 out of the solder ball pad 318, and the solder ball pad 318 is not provided with solder balls, the present invention can be planar array (Land Grid Array) The probe card used for the package is used for a functional test. The test method is as described above. As shown in FIG. 4A, the probe unit is also contacted by a plurality of probes 42 of a probe card 40. Solder ball pad 318 of 310a. Then, an aging test is performed on the object to be tested, in the same manner in an environment of high temperature (about 125 ° C), and the external power is supplied to exceed the operating voltage and current of the object to be tested for the aging test. Next, please refer to FIG. 4B. After the aging test is completed, a plurality of solder balls are erected on the solder ball pads 318 of the carrier 310 to form a plurality of ball grid array (BGA) packages. Finally, as shown in FIG. 4C, the singulation step is further performed to separate the ball grid array package 3〇2 to form a separate independent BGA package finished product 304. In addition, please refer to FIG. 3D. After separating the finished products 304 of the BGA package, an open/pass test can be performed on the finished product 3〇4 of each BGA package by placing the finished product 304 of the BGA package in an energized state, and the solder balls 340 can be respectively A plurality of claw probes 52 of a probe card 50 are clamped for testing to determine whether the open circuit state or the path state of the internal circuit of the finished product 3'〇4 of the BGA package is normal. The test method of the inventive grid array package is to judge the non-compliant package product by the analysis test result of the finished product test, wherein after the functional test and the aging test, the ball is implanted in the ball grid. Array-packaged semi-finished products On the solder ball pad, the open/pass test is performed. Since the solder ball is formed on the solder ball pad after the aging test, the solder ball is not clamped by the claw probe during the open/path test in the latter stage. Deformation, so as to improve the yield of the subsequent process, and improve the reliability of the combination of the finished product of the 12 1311350 97-06-10 ball grid array package and the external electronic device. Although the invention has been disclosed above in a preferred embodiment, It is not intended to limit the invention, and the scope of the invention is defined by the scope of the appended claims, without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1A] FIG. 1A is a block diagram showing a test method of a conventional grid array package. FIG. 1B is a schematic diagram showing a test method of a grid array package. FIG. 3A to 3C are diagrams showing a test method of a ball grid array package according to the present invention in a flow chart of a method for testing a ball grid array package according to a preferred embodiment of the present invention. 4A to 4C are schematic diagrams showing a test method of another ball grid array package according to a preferred embodiment of the present invention. [Description of main component symbols] 10, 30, 40, 50: probe card 12, 32, 42, 52: Probe 20: socket 100, 200, 300: object to be tested 110: solder ball 120 __ wafer 202, 302: ball grid array package 13 1311350 97-06-10 210, 310: carrier 212 ' 312 : first surface 214 , 314 : contact 216 , 316 : second surface 218 , 318 : solder ball pad 220 , 320 : wafer 230 , 330 : encapsulation material 240 , 340 : solder ball 310a : package unit S10 , S20 ' S30, S40, S50 : Step 14