TWI310101B - Substrate for liquid crystal display (lcd) panel and method of manufacturing the same - Google Patents

Description

V. INSTRUCTIONS (1) 'The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and a non-crystalline slab film substrate and a potting system for the LCD panel. The pole drive is integrated into the undoped non-junction 2 电 film transistor substrate. In the future of the society of information, an electronic display == want. All kinds of electronic displays are widely used in the field of bamboo flooring industry. The electronic display technology still holds, and the various electronic displays that are ready for new functions are being provided to respond to the various demands of information to the society. In the meantime, the electronic display is a device that can be used for people. That is, an electronic display can be defined as an electronic device that converts electrical information signals output by various electronic devices into optical information signals that can be visually recognized. Moreover, it can also be regarded as an electronic device in the form of a bridge connecting people and electronic devices. The electronic displays are classified into a light-emitting display, and the basin signals are displayed by a light-emitting method; and a non-light-emitting display: ... is displayed by a light modulation method such as reflection, scattering, and interference of light. Such illuminated displays - referred to as active displays, such as cathode rayers ((10)), plasma displays (pDp), light emitting diodes (10) d), electroluminescent displays (then), and the like. Non-illuminated displays are referred to as passive displays such as liquid crystal displays (LCDs), electricity (EPIDs), and the like.

The CR has been displayed as an image such as a television receiver or a monitor for the longest period of time. Due to its display quality and economic benefits, the CRT 1310101 A7 B7 V. Invention Description (2) has the highest market share, but also has many shortcomings, such as heavier weight, larger volume, and higher power consumption. At the same time, as various electronic devices have been integrated with the rapid advancement of semiconductor technology, and have been reduced in driving voltage and power consumption, they can be miniaturized and 'lightened, and are now thinner and lighter according to the needs of the new environment. A flat panel display with lower drive voltage and power consumption. Among the various flat-panel displays that have been developed, LCDs are thinner and lighter than other displays, and have lower driving voltages and power consumption. Moreover, its display quality is similar to that of a CRT. Therefore, LCDs are widely used in various electronic devices. The LCD comprises two substrates each having an electrode disposed on the inner surface and a liquid crystal layer being disposed between the two substrates. In the LCD, a voltage is applied to the electrodes to align liquid crystal molecules and control the amount of light transmitted through the molecules. Among these LCDs, a TFT-LCD which is mainly used today has an electrode provided on the two substrates, and a thin film transistor or the like which can be used to switch electric power supplied to each electrode. Usually, these thin film transistors (hereinafter referred to as TFTs) are provided on one side of the two substrates. In general, an LCD having a TFT in each unit cell region is divided into an amorphous TFT-LCD, and another polycrystalline TFT-LCD 〇 polymorph TFT-LCD has advantages. Operating speed and drive operation with low power consumption. Moreover, the TFTs of the pixel elements and the semiconductor device of the driving circuit can also be fabricated together. However, the driving circuit of the polycrystalline TFT-LCD needs to be in the non-crystal 6 (please read the back of the page and fill in the page). The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1310101 A7 —_______ B7_ V. OBJECT DESCRIPTION OF THE INVENTION (3) After Shi Xi is/child, an amorphous annealing process is used to convert amorphous yttrium into polycrystalline stone. This will limit the material of the substrate. In other words, if a glass substrate is used, the glass substrate may be deformed by the annealing process. Further, because of the structure in which the pole drive member has a complementary metal oxide semiconductor (CMOS), the n-channel transistor and ? The channel transistors are formed together on the same substrate. In this regard, the process of the polymorphic TFT_LCD is more complicated and difficult if it is compared with the process of an amorphous TFT-LCD having only a single channel type of electric crystal. Conventionally, a substrate provided with a TFTsiLCD is manufactured by photolithography using a mask. Currently, seven to nine masks are used. The more the number of photolithography processes is increased, the more the manufacturing cost and the probability of failure will increase. Therefore, in the process of manufacturing a TFT substrate of a color LCD panel, a technical development capable of reducing the number of masks is inevitably required. The first object of the present invention is to provide an LCD panel substrate made of amorphous enamel which can reduce the number of reticle by placing a plurality of components made of the same material on the same film layer. . A second object of the present invention is to provide a method for producing a non-crystalline lithographic lcd panel substrate which can reduce the number of reticle by placing a plurality of elements made of the same material on the same film layer. A third object of the present invention is to provide an LCD panel substrate, wherein a gate driving member is provided at one side edge or both side edges of the TFT substrate, and the fourth object of the present invention is provided. A method for fabricating an amorphous crystallized lcd panel substrate, which can be formed by combining a gate of a first transistor with a source and a drain of a second transistor without increasing the fabrication of the pixel electrode This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm)

.-...--------丨-L pen...: (Please read the notes on the back and fill out this page) ., can | -Φ- !31〇1〇1 V. Invention description (4 more a plurality of contact processes 'the second electro-crystalline system is adjacent to the first transistor, and the first and second transistors are combined to form a shift register of a gate driver, thereby simplifying the TFT The substrate of the substrate. In order to achieve the above object of the present invention, an LCD panel substrate is provided. In the LCD panel substrate, the open-polar line includes-the interpolar line is disposed on a transparent insulating substrate. One of the pixel area and the peripheral area, and the -electrode electrode protrudes from the inter-pole line branch. A pole insulating film is disposed on the interpole, the path and the substrate are provided with an active pattern The gate insulating film, and the 3th impurity region, the second impurity region, and the channel region are disposed between the first and the impurity regions. The data trace is disposed on the active trace and the gate insulating film The upper surface of the 5th Beibei texture system includes a gate electrode contacting the first impurity region '-the source electrode is in contact with the second impurity region, and a data line is connected to the electrodeless electrode. First The edge interposer is disposed on the data trace and the gate insulating film. The first insulating interposer includes a first contact hole for partially exposing the electrodeless electrode, and a second contact hole for exposing the periphery a gate electrode of the first driving transistor of the region, and a third contact hole for exposing the source/drain electrode of the second driving transistor of one of the peripheral regions. An electrode trace portion is disposed in the first insulating interlayer The electrode trace portion includes a first electrode trace connected to the drain electrode of the pixel region via a first contact hole, and a second electrode trace is connected via the second and third contact holes The exposed gate electrode of the first driving transistor and the exposed source/no-polar electrode of the second driving transistor. The invention also provides an LCD panel substrate, wherein a gate pattern includes a gate The polar line is set in a pixel area of a transparent insulating substrate and a paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 5. The invention (5) has a pole on the surrounding area. The electrode protrudes from the closed line branch. The edge film is disposed on the closed-pole line and the substrate. An active pattern is provided on the closed-end insulating film to include a first impurity region and a second impurity, and the two-channel region is disposed on the first and second impurities. Between the zones.—The data (4) is placed on the active trace and the gate insulating film, and the drain electrode includes the first impurity region 'the source electrode contacts the second impurity region' and the data line is connected to a first electrode-insulating interposer is disposed on the data track and the closed-pole insulating film. The first insulating interposer includes a first contact hole to partially expose the source electrode' - the second contact hole is Partially exposing the electrodeless electrode of the pixel region and the third contact hole may expose the peripheral region - the closed electrode of the first driving transistor and a fourth contact hole may expose the peripheral region One of the source/drain electrodes of the second drive transistor. An electrode land portion is provided on the first insulating interposer. The electrode trace portion includes a first electrode trace connected to the source electrode of the pixel region via a first contact hole, and a second electrode trace is connected to the gate electrode of the pixel region via the second contact hole, and The third electrode trace is connected to the exposed gate electrode of the first driving transistor and the exposed source/gate and the electrode of the second driving transistor via the third and fourth contact holes. To achieve the second and fourth objects of the present invention, a method of manufacturing an LCD panel substrate is provided. In the method, a gate trace includes a gate line which is further disposed on a pixel region and a peripheral region of a transparent insulating substrate, and a gate electrode is extended from the gate line branch. A gate insulating film, an undoped amorphous layer, a doped amorphous layer, and a metal layer are sequentially disposed on the gate trace and the substrate. A paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 public service) 1310101 V. Invention Description (The case is formed on the metal layer. The photoresist pattern corresponds to the source electrode and the drain electrode The portion of the channel region is thinner than the portion corresponding to the source electrode and the drain electrode. The metal layer, the doped amorphous layer, and the amorphous layer 7 may be utilized by the photoresist. The pattern is patterned as a mask, and the metal layer of the channel region is removed, and a data line is formed to directly include the source electrode, the gate electrode is spaced apart from the source electrode, and a data line is connected to the drain electrode The electrode is perpendicular to the gate line. The photoresist pattern and the doped amorphous layer of the pass-through region are removed. A first insulating interposer is disposed on the structure of the substrate. The insulating interposer may be partially etched to form a first contact hole to partially expose the electrode electrode of the cell region, and the second contact hole may expose one of the peripheral regions. The gate electrode of the crystal, and the third contact hole can be exposed to the periphery a source/drain electrode of the second transistor of the domain. A conductive film is disposed on the first insulating spacer layer having the first, second, and third contact holes. The conductive germanium is patterned to form - a first electrode trace and a second electrode trace. The first electrode and the electric trace are connected to the pixel electrode region via the first contact hole. The second electrode trace is connected via the second and third contact holes. A portion of the first transistor is exposed to the exposed electrode and the exposed source/battery electrode of the second transistor. The invention also provides a method of fabricating an LCD panel substrate. Wherein a gate trace comprises a gate line respectively disposed on a pixel region and a peripheral region of a transparent edge substrate, and a gate electrode extending from the gate line branch. A gate insulating film, An undoped amorphous V layer, a doped amorphous germanium layer, and a metal layer are successively disposed in the fifth aspect of the invention (7): pole: way and the substrate. - photoresist a pattern will be formed on the metal layer'. The photoresist pattern corresponds to the source electrode and the drain electrode The thin-metal layer corresponding to the source electrode and the drain electrode, the doped amorphous layer, and the amorphous layer can be utilized in the U-region. Patterning as a reticle, and removing the channel "Meng's layer" sub-formation - data texture comprising the source electrode, the electrodeless electrode is spaced apart from the source electrode. The photoresist pattern and the channel region are replaced The hetero-amorphous layer will be removed. A first insulating interposer will be placed on the opening/forming structure of the base. The first insulating interposer will be partially engraved. The first contact hole may partially expose the drain electrode of the pixel region, the second contact hole may partially expose the source electrode of the pixel region, and the third contact hole may expose the periphery The inter-electrode electrode of the first transistor and the fourth contact hole of the region can expose the source/dot electrode of the second transistor in the peripheral region. A conductive film is disposed on the first insulating spacer having the first, second, third, and fourth contact holes. The conductive film is patterned to form a second electrode-electrode pattern, a second electrode pattern, and a third electrode pattern. The first electrode trace is connected to the source electrode of the pixel region via the first contact hole, and the second electrode trace is connected to the gate electrode of the pixel region via the second contact hole. The exposed gate electrode of the first transistor and the exposed source/drain electrode of the second transistor are connected via the third and fourth contact holes. Further, the present invention also provides a method of manufacturing an LCD panel substrate. In the method, a gate trace includes a gate line which is disposed on a transparent insulating substrate - like an area and a peripheral region, and has a --electrode electrode 1310101. One sticks out. A pole insulating film is disposed between the interpole pattern and the substrate - the active (four) is disposed on the interlayer insulating film. The active first::-the second impurity region, and the -channel region are interposed between the first-disc region. a data line includes - a drain electrode is disposed at the first - contact, a contact - a source electrode is disposed on the second impurity region and a "and a lean line is connected to the source electrode And perpendicular to the gate ', the % edge of the interposer is set on the data line and the gate insulating film. The layer will be partially engraved, and a first contact hole may be formed to partially expose the area... And the pole electrode, the second contact hole can be exposed to one of the edge regions, the gate electrode of the driving transistor and the third contact hole can expose the circumference of the second driving transistor Source/dot electrode. - The conductive film will be on the insulating interposer with a first, first, and third contact holes. The v film will be patterned to form a first electrode trace and a first a second electrode pattern. The first electrode pattern is connected to the gate electrode of the pixel region via the first contact hole. The second electrode pattern is connected to the first driving transistor via the second and third contact holes. The exposed gate electrode and the exposed source/drain electrode of the second driving transistor. Furthermore, the present invention also provides The method for manufacturing an LCD panel substrate. In the method, the gate gate line includes a gate line respectively disposed on a pixel region and a peripheral region of a transparent insulating substrate, and a gate electrode is provided by the gate a gate line is extended. A gate insulating film is disposed on the gate trace and the substrate. An active trace is disposed on the gate insulating film. The active trace includes a first impurity region, a first impurity region, And a channel region between the first and second impurity regions. A data pattern includes a drain electrode disposed on the first paper scale applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (9) The impurity region is in contact with the upper region, a source electrode is disposed on the second impurity region, and the contact and data lines are connected to the source electrode and perpendicular to the gate line. The first insulating interposer is disposed on the data trace and the interposer insulating film. The first insulating interposer is partially etched to form a first contact hole to partially expose the source of the pixel region The electrode, the first contact hole, can partially expose the gate electrode of the pixel region A third contact hole can expose the gate electrode of the first transistor in the region of the week, and a fourth contact hole can expose the source/drain electrode of the first transistor of the peripheral region. And being disposed on the first insulating interposer having the first, second, third, and fourth contact holes. The conductive film is patterned to form a first electrode trace, a second electrode trace, and a first a three-electrode effect. The first electrode trace is connected to the source electrode of the pixel region via the first contact hole, and the second electrode trace is connected to the drain electrode of the pixel region via the second contact hole, first The electrode, the path is connected to the exposed gate electrode of the first transistor and the exposed source/drain electrode of the second transistor via the second and fourth contact holes. According to the invention, the area of the gate driving region is minimized 'the number of masks used to form the TFT can be reduced to four or five. BRIEF DESCRIPTION OF THE DRAWINGS The above and other advantages and advantages of the present invention will become more apparent from the detailed description of the preferred embodiments of the appended claims. 2 is a plan view of a 1.85 hour panel of a single source drive circuit portion having a transfer gate (TG) structure;

This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1310101 A7 " ------— B7_ V. Invention———-- 苐3 is a simplified circuit diagram of Figure 2. 4 is a simplified plan view of a 85-time panel of a single-drive circuit portion having a double gate (DG) structure; FIG. 5 is a simplified circuit diagram of FIG. 4; FIG. 6 is a simplified embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a cross-sectional view of a non-crystalline 矽tft substrate according to a preferred embodiment of the present invention; FIG. 8 is a circuit diagram of a shift register of one of the gate driving regions; A cross-sectional view of an amorphous germanium substrate according to another preferred embodiment of the present invention; and FIGS. 9 to 14 are plan views of a unit pixel region and its adjacent portions in the a_Si TFT substrate of FIG. 7; Figure 23 is a cross-sectional view along the first line in Figures 9 to 14; Figures 24 to 29 are each a cross-sectional view along the second line in Figures 9 to 14; Figure 30 is a plan view The gate driving region and the adjacent pixel region are shown; the 31st to 35th drawings are used for each unit system in order to make the structure of the third drawing. Figure 36 is a plan view of a unit pixel area and adjacent portions of Figure 3; and Figures 37 to 41 are partial plan views showing the unit pixel area and adjacent portions of each process; Figure 42 is a partial plan view of the gate drive region of Figure 30; Figures 43 to 47 show the local paper scale for the gate drive area of each process for the China National Standard (CNS) A4 specification (210X 297 Chu)

.*tr— (Please read the precautions on the back and fill in this page) .Φ, 1310101 11 V. Invention description plan; (Please read the note on the back and then fill in this page) Figure 48 is a better example of the present invention. A plan view of a sealing portion of a gate driving region in the embodiment; Fig. 49 is a plan view showing a contact portion of a gate driving region in a preferred embodiment of the present invention; and Fig. 50 is a gate of a preferred embodiment of the present invention A plan view of the signal line connection structure of the pole drive region; and Fig. 51 is a plan view of the data signal line ' and a switching portion taken from the source drive circuit portion for the DE1 and DE2 lines. Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Figure 1 is a plan view of a 1.85 inch LCD panel. Referring to FIG. 1, the LCD panel comprises a thin film transistor (TFT) substrate 100 as a lower substrate, and a color filter substrate 2 is sandwiched between the upper substrate and a liquid crystal layer (not shown). The TF τ substrate is between the substrate 滤 and the color filter substrate 2 〇〇. A flexible printed circuit (FPC) connector 3 is fixedly coupled to the TFT substrate 1 沿着 along one side edge of the LCD panel. The TFT substrate 1 is divided into a pixel region and a peripheral region. In the pixel area, there are pixel electrodes arranged in a matrix. A thin film transistor or the like as a switching element is bonded to the pixel electrodes. In Fig. 1, the symbol DA indicates the display area. A source driving circuit portion 400 and a gate driving circuit portion 500 are provided in the peripheral region. The source driving circuit unit 4 divides the external image signal input by the FPC connector 300 into a gate driving signal and a data.

5, 1310101, invention description (l2 drive signal, and the separate lift signal is supplied to the data line search. The gate drive circuit portion 500 will be n. „„. ^ Broken source drive circuit unit 400 The gate driving signal is supplied to the gate line, etc. The source driving circuit portion 4 is formed of a "L 5 γ ρ 半导体 wafer formed on a glass (COG) type FT substrate 1 。. The structure of the source driving circuit unit 4 夕 夕 如 如 夕 夕 夕 。 。 。 。 。 。 。 。 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 具有 具有 具有^ m #早—Source drive circuit. Plan the layout between the panels. Please refer to Figure 2, where there are two switching sections to accommodate the data signals from the source drive circuit section. The data line of the pixel area, etc. The circuit diagram of the switching unit 600 is shown in Fig. 3. There is another line, the data line, etc., which is taken by the source driving circuit unit 400 and the switching unit _ The planar structure is shown in Fig. 51. Fig. 4 is a U5 time surface of a single source driving circuit portion having a double gate (DG) structure. A simplified plan view of the board' and Fig. 5 is a simplified circuit diagram of Fig. 4. Please refer to Figs. 4 and 5'. In the double gate structure, the gate drive circuit J 500 is named [the both sides of the CD panel For example, a first gate driving circuit portion 5 is disposed on the left side, and a gate signal can be supplied to the gate electrode 8 connected to the odd pixel electrode, and a second gate driving circuit portion 5 〇ι is set to the right side and can send the gate signal to the TFTs connected to the even pixel electrodes. The LCD panels shown in the first to fifth figures all have a gate driving circuit including a plurality of shift registers. The figure 6 shows that the paper scale of these shift registers is applicable to the Chinese National Standard (〇jS) A4 specification (21〇χ297 公爱〉)

(Please read the precautions on the back and fill in this page) -Book · V. Inventions (u) Circuit diagram. In the embodiment of the invention, the gate driving circuit portion has the following characteristics. As shown in Fig. 48, a sealing line can be used to join the TFT substrate and the color-passing substrate, and is designed to be partially separated from the gate driving circuit. When the sealing line is insulated from the gate driving circuit portion When the interposer is defective, it can prevent possible short-circuit of the connection line. Again, as shown in Fig. 49, the number of electrical contacts is minimized, and the drive circuit is designed to have a minimum area. In other words, the first and second transistors having a wide width are directly connected to the output terminal (?τ), and the remaining third to ninth transistors ΝΤ3 to ΝΤ9 and the like are arranged in the middle portion. As shown in Fig. 50, the signal line 113 and the like are arranged outside the cell region and the gate driving region. Moreover, the range in which the pixel electrode is used is limited to the contact portion so that the circuit characteristics do not have to depend on the type of electrode used. Furthermore, if the sensitivity to the resistance becomes large, the width of the connection line increases. (Voff > VCK1 = VCK2 > Vst) Embodiment 1 Fig. 7 is a cross-sectional view showing a non-crystalline germanium thin film transistor substrate of a preferred embodiment of the present invention, showing the structure in the pixel region and the peripheral region. The peripheral region includes a pad area and a gate drive area. Please refer to FIG. 7 'The gate lines 112a, 112b, 112c, 112d, 112e, 112f, etc. are disposed in a pixel region and a peripheral region of a transparent insulating substrate, that is, the pad region and the gate Drive area and other parts. Gate pattern --------- This paper scale applies to China National Standard (CNS) A4 specification (210X297 mm) 1310101 No. 90120732 Patent application specification revision page 97.10.20 ^7 years (1) month · 1^ repair (Fully rli suppresses the shell ------- 5. Inventive Note (14) 1____ | 112a to 112f include a gate line and a gate electrode branched from the gate lines, etc. The gate pattern 112b and 112e is respectively disposed at the pixel area and the peripheral area to form a lower electrode of the storage capacitor. The gate lines 112a to 112f are in a single layer structure having a thickness of 2500 A, and preferably in a double layer. In the structure, there is a lower layer of Cr having a thickness of about 5 〇〇 A, and an upper layer of an A1Nd alloy having a thickness of about 2 〇〇〇 A. The pad region is disposed between the pixel region and the gate driving region. a gate pad 1212 made of the gate material of the gate pattern is disposed in the pad region. A line extending from the gate line in the cell region is electrically connected thereto. a gate pad 112c. The gate surface of the substrate 1 including the gate lines U2a to 112f is provided with a gate insulation 1 i 4. The gate insulating film 114 is preferably made of tantalum nitride (SiNx) or tantalum oxide having a thickness of about 4500 A. The pixel region and the gate driving region on the gate insulating film 114. The history has an active layer texture including first impurity regions 1183 and 11 and a second impurity region 18b/, 118d, and channel regions 116 & and 1161) respectively disposed in the first impurity regions 118a, 118c and the second impurity Between areas U8b and U8d. The channel regions 116a, 116b are formed of approximately 2000 A thick intrinsic non-cyanite. The first and second impurity regions U8a to 11d are made of an extrinsic amorphous material in which n-type impurities are highly doped in a thickness of about 500 Å. A pattern of textures is provided on the active patterns 118a to 118d, 116a, 116b. The source lines are included in the source lines 12a and 12b, respectively.

V. Description of the Invention (15) An impurity region 118a, 118c, a drain electrode curb, I20f respectively contact the second impurity regions 118b, 118d, and a data line are perpendicular to the gate line. As shown in Fig. 7, the source electrode 120e of the TFT and the gate electrode 12f and the like in the gate driving region are preferably formed into a finger-like interdigitated structure having a plurality of channels. In other words, the even number of source electrodes 12 〇 e are alternately arranged between the odd gate electrodes 120f. An upper storage electrode 120g is provided on the gate insulating film stack 14. The upper reserve

The storage electrode 120g overlaps the storage electrode 112e with the insulating film interposed therebetween. In the pad region between the cell region and the gate driving region, a data pad 120d is formed which is formed by the same film layer of the data lines 120a to 120g of the gate driving region.

A passivation film 130 is disposed on the substrate including the data lines 12〇a to i20g, and a first contact hole 111 is disposed to expose a portion of the pixel region of the pixel electrode 120b. The two contact holes 5^ can expose the contact gate traces 112f, and the third contact holes H3 can expose the contact traces 120h of the gate drive region. Hereinafter, the gate trace 2f is referred to as ''contact gate pattern'' and the data pattern is referred to as "contact data pattern". Further, in the pad region of the passivation film 130, fourth and fifth contact holes H4 and H5 are provided, and a portion of the pad pad 12c and the data pad 120d are respectively exposed. The passivation film 130 is made of tantalum nitride and has a thickness of about #85 # m. On the passivation film 13〇 containing the first to fifth contact holes ^11 to 115, ΓC; l· Λ* ul 19 1310101 A7 B7 5. Description of the invention (l6 ° has electrode lines, its application A pixel electrode (or first electrode trace) 140 is connected to the gate electrode 120b of the pixel region via the first contact hole m, and a second electrode trace 142 is via the second and third contact holes H2 and H3. The exposed contact gate pattern 112f and the data line 丨20h electrically connected to the gate driving region, and a third electrode line 丨43 are electrically connected via the fourth and fifth contact holes Η 4 and Η 5,. The gate pad 丨i 2 c of the pad region and the data pad 120d, wherein the second electrode trace 142 of the gate drive region and the third electrode trace 143 of the pad region are considered to be electrically connected thereto A part of the gate trace and a part of the data trace can be regarded as the contact terminal of the same function type. β (Please read the note on the back and then fill in the page) Order · Details of the contact terminal parts The structure is shown in Fig. 49. Please refer to Fig. 49, the contact gate pattern 112f One end is exposed by the second contact hole ^^, and one end of the contact data line 12011 is exposed by the third contact hole. The contact gate pattern 112f and the contact data pattern 12〇h are borrowed from the second electrode line 142. Preferably, they are designed such that one of the first and second contact holes H2 and H3 is one of the contact gate lines U2f and the contact data lines 12〇1! The longer 4/(zm; and the width of the second electrode trace 142 is larger than the width of the contact gate trace 112 and the contact data trace 120h, which is larger by 5 // m from the edge line, or larger overall 10 When the TFT substrate of the present invention is applied to a transmissive lcd, all of the first electrode lines 140, the second electrode lines 142, the third electrode lines 143, and the like are made of a transparent material such as indium. Tin oxide (IT〇) or

1310101 A7 (17) ~~ ---·-~- Indium zinc oxide (ΙΖ〇) and so on. As listed above, if the gripping substrate is used for a reflective LCD, they can be made of Cl^A1Nd. That is, when the reflective electrode of the reflective LCD has - not flat - there will be - a green organic insulating film having an uneven surface is used as a secret region. (4) Photosensitive organic (4), at least one patterning procedure for making contact holes and uneven surfaces can be omitted. Embodiment 2 FIG. 8 is a cross-sectional view showing a non-junction thin film transistor substrate according to a second embodiment of the present invention. Comparing FIGS. 7 and 8 , the structures of the data lines are different from each other. In FIG. 8, A data line M4 and a pixel electrode are disposed on the purification film 130 and separated from the pixel electrode 14 at a predetermined interval. In other words, the data line 144 is not disposed on the formed substrate. In the meta-region, the substrate is formed to include active layer patterns n8a to n8d, and only the source electrode 12Qa including the contact-first impurity region 118a and the drain electrode contacting the second impurity region 118b are provided. a data pattern of the electrode 丨2〇b, etc. The passivation layer is provided on the formation substrate containing the data pattern, wherein the first contact hole H1 is provided to expose a portion of the source electrode region 120a of the pixel region a second contact hole H2 can expose a portion of the pixel electrode region of the pixel electrode 120b, and a second contact hole H3 can expose a portion of the gate drive region of the contact | contact gate pattern 112f' and - The four contact holes can expose the contact data pattern 120h of the gate driving region. Also, in the junction area of the purification film 130 In, is provided with fifth and sixth contact holes H5 and H6, respectively, while the exposure is now part of the gate pad Shu〗 2c and scale information in this paper applies China National Standard (CNS) A4 size (210X297 public Chu)

Order - (Please read the notes on the back and fill out this page) Φ, 1310101

DESCRIPTION OF THE INVENTION Pad 120d. The passivation film no is made of Shiyan nitride and has a thickness of about 85 Å. (4) The passivation film 130 including the first to sixth contacts - H6 is provided with an electrode land portion. The electrode trace portion includes a data line (or first electric=grain) 144' connected to the source electrode 12A of the image 4 via the first contact hole H1; and the photo electrode (or the second electrode trace (10) The data line 144 is separated from the data line 144 by a predetermined interval, and is electrically connected to the electrode of the electrodeless region i via the second contact hole H2; and the third electrode pattern 142 is contacted by the second and the fourth contact with the H4. And the exposed contact gate pattern 112f of the gate driving region is electrically connected to the data texture road; and the fourth electrode pattern (4) is thinned through the fifth and sixth contact holes, and the interface region is The gate pad 112c and the data pad 12〇 are electrically connected. The third electrode trace 142 of the (four) drive region and the fourth electrode trace (4) of the interface region are considered to be electrically connected. The inter-polar traces and the partial data traces can be regarded as contact terminals of the same function type. Since the other components except the above components are constructed as an embodiment, the description thereof will not be redundant. The first and second embodiments, the contact surface in the peripheral region The accumulation is minimized, so that the gate driver can be integrated in the smallest area. Moreover, since the pixel electrode in the gate driving region is used only in the contact portion, its circuit characteristics are not affected. The influence of the type of electrode, so a stable circuit can be obtained. The paper scale applies to the Chinese national standard ((10)) A4 specification (21〇χ297 public)) Please read the back page to order 22 V. Invention description (l9) Example 3 Figures 9 to 14 each show a unit image area and its adjacent portion in the a_si TFT substrate of Fig. 7; the 15th to 23th drawings are the first of the first to the 9th to 14th A cross-sectional view of the cut line; the 14th to 29th views are cross-sectional views of the second cut lines in the figures 9 to 14. Specifically, Fig. 15 is a cross-sectional view taken along line 15-15 of Fig. 9, and The circle 24 is a cross-sectional view taken along the line 24_24 in Fig. 9. Referring to Figures 9, 15 and 24, a light-shielding film (not shown) having an oxide is provided on a transparent substrate 202. The substrate 2〇2 is made of an insulating material such as glass, quartz or sapphire. A shutter is provided on the light shielding film. The gate line includes a gate line 212a, a gate electrode 2i2d is branched by the gate line 212a, and a lower storage electrode pattern anddUbdUc is extended by the gate electrode 212d, and has an open loop structure, wherein The lower storage electrode lines 2 i2d, 212b, and 212c enclose an edge portion of a unit pixel area. Although not shown in the drawing, the gate pad may be provided in the peripheral area by an external integrated circuit. (IC) receiving a scan signal and a contact gate and a trace together with a gate trace of the pixel region. The gate pad and the contact gate trace are formed by the same film layer as the gate trace of the pixel region. Producer. The gate trace has a single layer structure, such as aluminum (aluminum or AlNd aluminum alloy, or a multilayer structure in which an aluminum or AlNd alloy system is superimposed on the & film. The gate trace system will have the above single A film of a layer structure or a multilayer structure is deposited on the substrate to a thickness of about 2000 to 3000 A, and is patterned by using a conventional photo-mechanical method to pattern the deposited film (first mask). 1310101 丨 丨 日 日 ( ( ( ( ( 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 -25, a sectional view of the cut line. In the figures 10, 16, and 25, the gate insulating film 214 is deposited on the substrate including the gate traces 2i2a to 212d in sequence, and a nitride insulating film (SiNx) is deposited. The amorphous iridium (a-Si:H) film 216 is not doped with impurities, and an extrinsic amorphous ruthenium (!1+3_3 丨) film 218 in which impurities are highly doped. The three film layer 214 216, 218, etc. are made by plasma enhanced chemical vapor deposition (PECVD), which is a kind of chemical vapor deposition (CVD). For example, the nitridation The film 214 is formed to a thickness of about 4500 A, the intrinsic amorphous film 216 is about 2000 A thick, and the non-essential amorphous film 2 18 is about 500 A thick. On the entire surface of the non-essential amorphous film. Then, a metal layer 220 as a source/drain electrode is formed by physical vapor deposition method such as sputtering. The metal layer 220 of the source/bold electrode and the bottom three layers 218, 216, 214 The system uses a movable mask to form a pattern at one time. In detail, please refer to Fig. 17, a positive photoresist film 250 is applied over the entire surface of the metal layer 220 of the source/drain electrode to a predetermined thickness 'and then a mask 240 is calibrated over the photoresist film. The mask 240 has a light transmissive region 240b and an opaque region 240a aligned with the source region and the drain region. Above the channel region. In particular, the portion of the light-transmitting region 240b between the channel region and the source region and between the channel region and the drain region has a slit structure. It is diffracted, so it is designed to make 24 rpt丨〇 of the same slit.

, invention description (21) 1310101 interval is slightly smaller than the spacing of the channel area. If ultraviolet light is used as the illumination light, the ultraviolet light passing through the slits is diffracted to expose the channel portion of the photoresist film. At the same time, the remaining exposed photoresist film is also exposed to the ultraviolet light. The exposed photoresist film will be developed to form a mask pattern 250e' wherein the channel portion will be removed to a predetermined depth.

Referring to Fig. 19, the exposed metal layer 220 not covered by the mask pattern 25〇e, the underlying non-essential amorphous film 2丨8 and the intrinsic amorphous film 216 will be removed. At this time, at least one of the exposed metal layer 22, the non-essential amorphous ruthenium film 218, the essential amorphous ruthenium film 2丨6, etc., is removed by dry etching, and the channel portion is made. The portions of the photoresist pattern b are removed together. In other words, since the photoresist pattern 25〇e of the portion of the channel region becomes thin during development, it is removed together during dry etching. Then, the exposed metal film 220 of the channel region and the underlying non-essential non-crystalline germanium film 218 are removed by a selective etching method, and the essential amorphous film 216 is removed by a predetermined thickness.

Then, the photoresist pattern 25A of the source/drain region is removed. (Second mask process) Fig. 12 is a plan view showing the state in which the second mask process is completed, Fig. 21 is a cross-sectional view taken along line 21-21 of Fig. 12, and Fig. 27 is along line 12. A cross-sectional view of the cut line 2 7 - 2 7, of the figure. Referring to Figure 12'2b, the active traces 216, 218 of the source region extend perpendicular to the gate line 212a and overlap the data line 22A. The insulating film 214 is interposed between the data line 220 and the active lines 216 and 218. The width of each of the active lines 216 and 218 is smaller than the data line 22〇. Therefore, the 25 1310101 bamboo year inferior day repair (/:?! ΐ·- replacement page 5, invention description (22) extended active lines 216 and 218 to prevent the data line 220 from forming a gap 'and The electric resistance of the data line 220 can be lowered. Fig. 13 is a plan view showing a state in which a passivation film 222 of tantalum nitride is deposited on a substrate of 1.58 / / m thick on the substrate of Fig. 12, and Fig. 22 is a view along the same A cross-sectional view of the 22-22' section line, and a 28th section of the section taken along line 28-28 of Fig. 13. Referring to Figs. 13, 22, 28, a predetermined portion of the passivation film 222 is provided. The first contact hole 223 can expose a selected portion of one of the drain electrodes 220d. However, although not shown in the drawing, there is a second contact hole for exposing the gate trace of the gate driving region, and A third contact hole exposing the data trace of the gate drive region is also formed together with the first contact hole 223. (Third mask) Next, please refer to Figures 14, 23 and 29, with a metal film It will be deposited by sputtering method on the entire surface of the substrate by about i 5 〇〇 A. As shown in Fig. 23, the deposited metal film will be utilized. The four masks form two conductive pattern patterns. In other words, they form a pixel electrode (or first electrode pattern), and the gate electrode 220d is contacted via the first contact hole of the pixel region. Shown in the figure, but it also forms a second electrode pattern 'via the second and third contact holes to connect the gate lines extending from the gate electrodes of the first transistor, and from adjacent to The data pattern of the source/drain electrode of the second transistor of the first transistor is extended. The patterned pixel electrode 224 has the purified film 222 and the gate as shown in the cross-sectional views of FIGS. 23 and 28. The pole insulating film 214 is used as a dielectric layer, and the dielectric layer is interposed between the pixel electrode 224 and the lower storage electrode, 1310101, and the invention is described (Μ " the electrical layer is interposed between the pixel electrode 224 and the lower layer. The electrode 21 is between 2 and 2. The pixel electrode 224 is shaped like an upper electrode of the storage capacitor. By the upper = configuration, the phase of the liquid crystal can be stably maintained until the subsequent operation is completed. The manufacturing method of the TFT substrate disclosed in the third embodiment is applied to the transmission type (10)' The first electrode trace 224 and the second electrode trace are made of a transparent conductive material to form, for example, indium tin oxide (ITO) or indium oxide (ΙΖΟ). Conversely, if the potential is right, the method is For a reflective LCD', the pixel electrode can be made of an electrically impermeable material such as a core or a bismuth alloy. In particular, when the reflective electrode of the reflective LCD has a fixed electrode When the uneven surface is used, a photosensitive organic insulating film having an uneven surface can be used as the passivation film. ~ Since the photosensitive organic insulating film does not require a process to form a mask pattern thereon Therefore, at least the patterning process for making contact holes and irregular surfaces can be reduced. According to the present invention, the active traces, the source electrodes, the drain electrodes, and the like are all completed by a mask process, and the contact between the first TFTs and the source of the second TFTs. The contact data lines extending from the electrode electrodes are simultaneously completed when the pixel electrodes are patterned. Therefore, the number of masks used to make 5 mega TFTs can be reduced to four. Embodiment 4 Four•T: (Please read the note on the back side and fill in the page), MW, in a method similar to that described in the second embodiment of FIG. 8, this embodiment discloses a TFT substrate. The manufacturing method, in which the data line is only used in this paper scale, is applicable to the Chinese national standard A4 specification (21〇><297 public luxury: upper 1310101 five, invention description (24) piece mask to be made in the passivation film As shown in FIG. 15, a first mask can be used to form a gate pattern including a gate electrode, a gate line, a lower storage electrode, etc. 嗣, a closed-end insulating film is formed at the base The entire surface of the material is deposited to a predetermined thickness. In the same manner as shown in FIGS. 17-21, an active grain including the first and second impurity regions and the channel region, and - including the second electrode and the electrodeless electrode : The data trace of the pole will be made, but the data line formed with the source electrode will not be placed in the pixel area. (Second mask) Next, please refer to Figures 22 and 8. On the substrate containing the active lines and the data lines, a passivation film of tantalum nitride is provided. Then, a first contact hole hi such as a source electrode 12 of the pixel region of the exposed portion, and a second contact hole H2 of the drain electrode 12〇b of the pixel region of the exposed portion may be exposed, The third contact hole H3 of the contact gate pattern 丨丨 2f of the gate driving region and the fourth contact hole H4 of the contact data pattern 12 sen of the exposed gate driving region may be formed. In the passivation film no. (third photomask), in the junction region of the AI purification film 130, the fifth and sixth contact holes H5 and H6 are also provided, and the portions can be respectively exposed. The gate pad 2c and the data pad 120d. On the passivation film 130 including the first to sixth contact holes H1 to H6, a metal film as a pixel electrode is deposited to a predetermined thickness. The metal film is patterned by using a fourth photomask to form an electrode trace portion. The electrode trace portion includes the data line (or first electrode trace) 144' which is connected via the first contact hole H1. The source paper size of the pixel area applies to the Chinese National Standard (CNs) A4 specification (210X297 public) (please first Read the precautions on the back and fill out this page. Order · -1, 28 V. Inventive Note (25) Electrode! 21 This photocell electrode (or second electrode trace) 14〇, which is electrically connected via the second contact hole H2 An electrode pattern connected to the pixel region is electrically connected to the contact gate pattern U2f and the data pattern (10) exposed by the third and fourth contact portions through the third and fourth contact portions. The 143 is electrically connected to the f-contact pair via the fifth and sixth contact holes and the H6. The first electrode strip 142 of the gate drive region is connected. The fourth electrode lines (4) of the art area, etc., can be regarded as contact terminals of the same function type because they will partially connect the closed-circuit lines to the damaged bead material and the track. As in the foregoing embodiments, if the manufacturing method of the TFT substrate disclosed in the fourth embodiment is used in a transmissive lcd, the first electrode traces 144 and the second electrode traces 14 由 are transparently conductive. The material is made of, for example, indium tin oxide (IT0) or bismuth zinc oxide (IZ〇). Conversely, if the manufacturing method is used for a reflective LCD', the photocell electrode is made of an opaque conductive material such as Cr or AINd alloy. In particular, when the reflective electrode of the TFT substrate of the reflective LCD has a specific uneven surface, a photosensitive organic insulating film having an uneven surface can be used as the passivation film. Since the photosensitive organic insulating film does not require a process for forming a mask pattern thereon, at least the patterning process for forming the contact hole and the uneven surface can be reduced. According to the present invention, the five scales of the paper, the source electrode and the electrodeless electrode are applicable to the national standard (CNS) A4 specification (210X297 mm) 1310101. The invention is described (the mask process is formed to form 'and The contact of the gate of the -m gate and the contact data of the source/drain electrode of the second TFT are formed at the same time when the pixel electrode is patterned. The number of masks forming the TFT can be reduced to four. Embodiment 5 Once, this embodiment has the characteristics of a layout design of a pattern texture, and can reduce the contact points in the interpole driving region. The circuit is completed in a minimum area. The figure 30 is a plan view partially showing the open driving area and its adjacent parts. 凊 Refer to the 30th and 6th figures as the gate line driving transistor. The first and second transistors NT1 and NT2 are disposed in a portion close to the pixel region; and the external signal lines CKB, CK, VDD, vss, ST, etc. are located at the farthest from the display region. The third to ninth transistors NT3 to ΝΤ9, which are control transistors, are The gate electrode (c) is disposed between the first gate line driving transistor θ1 and the second gate line driving transistor NT2. The capacitor includes a lower electrode disposed at an extension of a bottom of the gate electrode of the first driving transistor NT1, and an upper electrode disposed at a top of the gate electrode of the second driving transistor NT2. And a gate insulating film of a SiNx is disposed between the upper electrode and the lower electrode. FIGS. 31 to 35 are diagrams showing patterns in each unit process for forming the structure of the third drawing. The cross-sectional structure of Fig. 8 corresponds partially to the third 〇30

舂明# m 13 101 (Identification page of patent application specification of ^1〇90120732 Revision date: May 27, 1993) The plane structure of the figure. Figure 36 is a detailed plan view of a unit pixel area and its adjacent parts, and Figures 37 to 41 are partial detailed plan views of the 3G figure. Fig. 42 is a partial detailed plan view of the gate driving region in Fig. 30, and Figs. 43 to 47 are partial detailed plan views showing the respective unit processes in the peripheral region. Referring to Figures 31, 37, 43 and 7, a gate pattern U2 is formed on the pixel area of a transparent insulating substrate 110. The gate trace ι 2 has an aluminum (A1), or a single layer structure containing an aluminum alloy such as A1Nd, or a two-layer structure in which & or Mo is stacked on A1. (First photomask) The gate trace 112 of the pixel region includes gate lines U2g and the like arranged in parallel with each other in the horizontal direction, and the lower capacitance line 11211 is disposed between the two parallel gate lines 112g, and the lower capacitance trace 112丨 overlaps with the lower capacitance line U2g and is disposed in a unit pixel area, and a gate electrode 112& is branched from the gate line 112g. As shown in Fig. 31, a gate pad 112 is provided between the pixel region and the gate driving region, and is connected to one end of the gate line 12g. The gate pad of the output terminal OUT 112c receives the scan signal from an external information processing device and supplies it to the gate line Π 2g. The first drive transistor NT1 and the gates 112d-1 and 112d-2 of the second drive transistor NT2 are ' The width is greater than the gates of the third to ninth transistors NT3 to NT9 shown in Fig. 43. Further, the gate electrode 112d-1 of the first driving transistor NT1 includes the lower memory trace 112e toward the gate electrode 112d-1. The second transistor NT2 gate electrode 112d-2 is extended. After the patterning process of the gate pattern shown in Fig. 31 is completed, the nitride paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). )

------------------..... (Please read the notes on the back and fill out this page), τ. 1310101 A7 ----- —_______ V. Disclosure of the Invention (28) The gate insulating film 114 of Shi Xi will be provided on the entire surface of the substrate. As shown in Fig. 7, active stripes n6a, 116b, 118a, 118b, 11 8c, 118d and the like are formed on the gate insulating film 114. (Second Light Leather) The figures 32, 38, and 44 are plan views showing the state in which the active lines 116 and 118 are provided in the pixel area on the gate insulating film 114. Please refer to Figures 32 and 38, in which the first to third active lines are provided. The active lines include a first active track 18e perpendicular to the gate line i! 2g'. A second active track 117 partially overlaps the gate electrode ι 2 & and the first active track Π 8f is provided at the first The selected portion of the active pattern 1 i.8e is 'over the overlap with the lower capacitance line 112h. The second active trace 117 includes a second impurity region 118a (or a non-polar region) 'a second impurity region 丨 18b (or a source region), and a channel region 116a is interposed between the first impurity region 118a and the second region Between impurity areas U8b. Referring to Figures 32 and 44, the active traces 118 of the first and second gate drive transistors NT1 and NT2 (Μ and U8e_2, etc. are connected to the output terminals of the interpole drive region, and have a third to the third The active width of the nine-electrode crystal is larger. In the active texture shown in Figure 32, the patch shown by the symbol "sp" is used as a dummy trace to protect the source of the gate trace of the lower layer. Polar lines. These dummy lines reduce the surface slope of the surface that will form one of the source lines and prevent the top source metal lines from breaking. As shown in Figure 33, on the substrate containing the active lines. a source/dip metal pattern 120 (third mask) is provided. The source/drain metal pattern 12 is deposited on the entire surface of the substrate by a film of about 15 〇〇A thickness.丨__ This paper scale applies to Chinese National Standard (CNS) μ specification (2) 〇χ 297 mm) ' --

.*trl (Please read the precautions on the back and fill out this page) i, 1310101 A7 -----Ξ___ V. Inventive Note (29) The Cr film is patterned by conventional photolithography. Please refer to Figures 33, 39 and 45, in which the data line 12〇i and the like are perpendicular to the gate line 1 22i and the like, and overlap with the first active line 丨丨 8e in the pixel area. The source electrode 120a is branched from the data line 120i, and the electrodeless electrode 12〇b separated from the source electrode 12〇a by a pre-turn distance is formed together with the data line 120i and the like. In the unit pixel area, they are brought into contact with the first and second impurity regions 丨丨仏 and 丨 18b of the second active trace 117. As shown in Fig. 39, the drain electrode 12〇b overlaps with the lower capacitor trace 112i shown in Fig. 31 to ensure a sufficient storage capacitance. Referring to Figure 33, the source/drain pads 丨]!^ (or data pads) are placed close to the gate pads 丨12c in the gate drive region. The source/drain pad 120d and the gate pad 112c are electrically connected to each other by a contact grain formed by the pixel electrode of the pixel region, as shown in FIG. 3 >"> ° The source and the drain electrode of the first and second driving transistors Ντ丨 and Ντ 2 are arranged in a finger-like interdigitated structure. In other words, the even number of source electrodes 12〇e and the like are commonly connected to the left source pad 12〇d, and the odd-numbered drain electrodes 120f are commonly connected to the right-side source electrode such as the gate electrode The 120e alternate wheel is disposed between the odd gate electrodes 12〇f. One of the first odd-numbered drain electrodes u〇f of the first driving transistor NT1 extends in the width direction thereof and overlaps with the lower storage electrode 112e of the first driving transistor NT1. Therefore, the first-odd number 汲The electrode electrode 形成 forms an upper electrode of the capacitor C connected between the source electrode 12〇e and the gate electrode 112d of the first driving transistor NT1.

♦- (Please read the notes on the back and fill out this page) i, 1 1-- 2 This paper scale applies to Chinese National Standard (CNs) A4 specification (210 X 297·^^ ------ 1310101 V. DESCRIPTION OF THE INVENTION (3〇) The interdigitated structure ' applied to the source and drain electrodes of the first and second driving transistors NT1 and NT2 will increase the channel width of the driving transistor, and thus is made of amorphous 矽The fabricated TFTS is capable of ensuring sufficient driving capability. When the source/drain metal pattern 2 shown in FIG. 3 is completed, the passivation film 130 is disposed on the formed substrate, as described in 7 shows that the passivation film 130 is made of an inorganic insulating material, and examples of the inorganic insulating material are, for example, cerium oxide, cerium nitride, a mixture thereof, etc., and then 'as shown in Fig. 34' The contact holes H1 to H5 and the like are formed in the purification film by a conventional photo-inscription method. (Fourth mask) Specifically, the first contact hole 1 is provided in the pixel region, and The first contact hole Η1 partially exposes the drain electrode 丨2〇b. The second contact hole H2 and the third contact hole are provided at the gate In the driving area, the second contact hole H2 exposes the contact gate pattern, and the third contact hole exposes the contact data pattern. In addition to the second and third contact holes H2 and H3, The fourth and fifth contact holes H4 and H5 are also disposed in the gate driving region. Like the second and third contact holes H2 and H3, the fourth and fifth contact holes ^^ and ^^ are divided into one. The first group of the contact gate lines and the second group of the contact data lines can be exposed, wherein the contact holes of the poles 112C can be exposed, etc. In the second contact hole group, the contact hole or the like which can expose the data interface 120d is included in the third contact hole group. As shown in FIG. 35, a pair of adjacent contact holes ^^ and ^ ^ is electrically connected to each other by an electrode pattern 144, which is provided on the display

1310101 V. INSTRUCTION DESCRIPTION (31) In other words, in order to electrically connect the signal lines including the gate metal lines and the source lines, the contact holes are provided in the passivation film, and then by the pixel electrode lines Contact lines and the like made of the same material are provided on the passivation film containing the contact holes. Specifically, when the contact holes are formed, a metal film as a pixel electrode is deposited on the passivation film containing the contact holes. The deposited metal film tantalum is patterned by conventional photolithography. (Fifth Light Army) Fig. 35 is a plan view showing that the pixel electrode pattern is formed on the passivation film including the contact hole, and Fig. 41 is a detailed plan view of the pixel electrode pattern shown in Fig. 35, and Fig. 47 is a plan view showing that the electrode trace is provided in the gate driving region. As shown in Fig. 35, the pixel electrode (or first electrode pattern) 140 in the pixel region contacts the gate electrode 120b via the first contact hole provided in the passivation film 13A. The pixel electrode trace (or second electrode trace) 144 disposed in the gate drive region of the peripheral region passes through the second and third contact holes 112 and 113 to expose the exposed gate trace 112f and the data trace 12〇h are electrically connected to each other. Further, a pixel electrode pattern (or third electrode pattern) 143 in the pad region of the peripheral region is electrically connected to the exposed data pad 12?d and the pad pad 112c. As in the foregoing embodiments, if the manufacturing method of the TFT substrate disclosed in the fifth embodiment is applied to a transmissive LCD, the first electrode traces 144 and the second electrode traces 140 may be made of a transparent conductive material. It is made, for example, of indium tin oxide (ITO) or indium zinc oxide (IZ〇). Conversely, 35 1310101 V. Inventive Note (32) is, for example, indium tin oxide (ITO) or indium oxide (IZO). Conversely, if the 6-inch manufacturing method is used in a reflective LCD, the first and second electrode patterns are made of an opaque material such as Cr or AINd alloy. In the case of a transmissive LCD, since the transparent conductive film is used as a contact grain and has a lower conductivity than the metal grain, the contact hole or the like which is connected to each other via the electrode lines can preferably be provided. As close as possible, the electrical characteristics of the gate drive circuit can be minimized due to the contact resistance. Further, in order to avoid an increase in contact resistance or a failure of contact due to a calibration error, it is preferable that the size margin of the contact grain is ensured to a sufficient extent to sufficiently cover the contact hole. Meanwhile, when the reflective electrode of the FT FT substrate as the reflective LCD has a specific uneven surface, a photosensitive organic insulating film having an uneven surface can be used as the passivation film. Since the photosensitive organic insulating film does not need to have a process for forming a mask pattern thereon, at least one patterning process for forming the contact hole and the irregular surface can be reduced. According to a fifth embodiment of the present invention, the contact closed-end trace is extended by the inter-electrode electrode of the first TFT of the inter-polar drive region, and the contact data trace is extended by the source/pole electrode of the second TFT. Both will be formed simultaneously when the pixel electrode is patterned. Therefore, the number of masks used to fabricate the TFT can be reduced to five. The number of contact points in this peripheral area is minimized. Because of the size of the panel, a pole drive circuit can be integrated into the small area of the paper ruler _ _ _ fresh 1310101 five, invention description (33). Further, since the range of use of the pixel electrode in the polarity driving region is limited to the contact portion, the circuit characteristics are not affected by the type of use, and a stable circuit can be obtained. Embodiment 6 Fig. 8 is a cross-sectional view showing a non-crystalline (tetra) T substrate of the present invention. Comparing Figures 8 and 7' the construction of these data lines should be valued. In other words, as shown in FIG. 8, the data lines H4 and the pixel electrodes 14 are formed on the passivation film 13A, and are separated from the pixel electrodes 14 by a predetermined distance, specifically, As shown in FIG. 3-2, the gate trace 112, the gate insulating film ι4, the active traces 118a to 118d, the data lines, and the like are not provided in the pixel region on the substrate, but the data trace is included. The source electrode 12A of the first impurity region 118a is contacted, and the electrode electrode 120b of the second impurity region (10) is contacted. By depositing a metal film such as & on a substrate containing the active tracks to a thickness of about 1500 Å, and patterning the metal film by conventional light buttoning, the data texture is Will be formed, as shown in Figure 32. (Third mask) As shown in Fig. 8, a tantalum nitride passivation film 13 of about 1.85 #m thick is provided on the substrate containing the data pattern.嗣, the contact holes H1 to H4 are formed in the passivation film 130 by a conventional photolithography method. In detail, the first contact hole is set in the pixel area, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm).

Clothing - f Please read the precautions on the back and fill the nest page.) • Order — 37 V. Inventive Note (34) The source electrode 120a can be partially exposed. The second contact hole H2 is also disposed in the pixel area, and the gate electrode 12〇b can be partially exposed. The third contact hole is provided in the gate driving region, and the contact gate pattern U2f can be exposed. The fourth contact hole H4 is also disposed in the gate driving region, and the contact data pattern 120h can be exposed. In addition, fifth and sixth contact holes are provided in the pad region, and the pad pads U2c and the data pads 120d are partially exposed. (Fourth Photomask) Then, on the passivation film 130 containing the first to sixth contact holes {_11 to 1-6, a transparent conductive film having a thickness of about 15 Å is provided. The transparent conductive film is patterned by conventional photolithography. (fifth mask) for Ω, which is provided with the data line (or first electrode pattern) 1 connected to the source electrode of the pixel region via the first contact hole H1, the pixel electrode The texture (or second electrode trace) 140 is connected to the gate electrode 12〇b of the pixel region via the second contact hole H2, and the third electrode trace 142 is gated via the second and fourth contact holes H3 and H4. The exposed gate trace 112f of the pole drive region is electrically connected to the data trace 12〇h, and a fourth electrode trace Mg is connected to the gate pad of the pad region by the fifth and sixth contact holes H5 and H6. 112c is electrically connected to the data pad 120d. Here, the third electrode traces 142 and the fourth electrode traces 143 can be regarded as the same type of contact terminals because they electrically connect part of the gate lines and a part of the data lines. According to the sixth embodiment of the present invention, the contact area in the peripheral region is minimized. Therefore, compared to the size of the panel, a gate drive 1310101 V. Description of the invention (% of the dynamic circuit can be integrated in - the smallest area command. The range used only by the pixel electrode in the gate (four) region Kind of the contact portion, so that the circuit characteristics are not affected by the type of electrode used, and a stable circuit can be obtained. = According to the present invention, the contact area in the peripheral region is reduced to * small Therefore, the closed-circuit driving circuit can be integrated into the -minimum surface. In addition, since the range of use of the pixel electrode in the inter-polar driving region is limited to the contact portion, The circuit characteristics are not affected by the type of electrodes used, and a stable circuit can be obtained. Furthermore, the active lines, the source electrodes and the electrodeless electrodes are formed by a single optical process and are formed by the first TFT. The contact between the gate electrode and the contact (four) grain extending from the source/nob electrode of the second TFT are formed at the same time when the pixel electrode is patterned. The number of masks that make up the TFT can be reduced to four Moreover, since the data line is formed together with the pixel electrode, it is possible to avoid the short circuit or breakage of the data lines due to the complexity of the data texture in the image area. The first gate electrode of the gate driving region protrudes from the contact gate pattern 'and the contact grain line extended by the source/nopole electrode of the second TFT, etc., and the pixel electrode is patterned At the same time, the number of masks used to form the TFT can be reduced to five. Further, since the passivation film is made of an acrylic-based photosensitive organic material, the process of forming a contact hole is formed. The number of steps can be reduced, and the simplified procedure is obtained. Although the invention has been described in detail, it should be understood that many variations, alternatives, and modifications can be implemented. The spirit and scope of the invention as defined in the scope of the patent application is not exceeded. 40. 40 (Please read the note on the back and fill out this page) This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1310101

(Invention) (37) 100"_TFT substrate 110···transparent insulating substrate 112a~f···gate gate 112a_··gate electrode 112c...gate pad 112d···gate 112e... The electrode 112f...contacts the gate trace 112g_"the gate line 112h...the lower capacitance line 112l···the gate line 113···the signal line 114···the gate insulating film 116a,b...the channel region 117·" the second Active lines 118a, c···first impurity regions 118b, d···second impurity regions 118e...first active traces 118f...third active traces 120a,e...source electrodes 120b,f...thin electrodes 120d... Data pad component label control 120g...upper storage electrode 120h...contact data pattern 120l···data line 130···passivation film 140...pixel electrode 142...electrode grain 143...electrode grain 144...data line 2〇〇...filter Color substrate 202...transparent substrate 212a...gate line 212d··.gate electrode 212b,c,cl···lower storage electrode pattern 214...gate insulator 216...essentially amorphous 矽film 218...extrinsic Amorphous ruthenium film 220...metal layer 220d... no electrode 222...passivation film 223...contact hole 224... Pixel electrode 250"·Photoresist film 41 1310101 A7_B7 V. Inventive description (38) 240... Cover screen 300... FPC connector 400... Source drive circuit portion 500, 501... Gate drive circuit portion 6 0 0... Switching portion 42 (Please read the notes on the back and fill out this page.) This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm).

Claims (1)

Patent application No. 90120732 Patent application application Patent scope revision 97 years 1 month 1. A substrate for a liquid crystal display panel, comprising: a gate line, which is disposed in a pixel area and a In the peripheral region, the peripheral region has a closed-cell driving region and a pad region, and the inter-polar trace has an inter-polar line and a gate electrode of one of the first driving transistors of the peripheral region, and the pixel region And the peripheral region is disposed on an insulating substrate; an active trace is insulated from the gate trace and disposed on the gate trace, the active trace includes a semiconductor layer; a data trace, and the active trace a part of the electrical connection, and the edge material line comprises a data electrode and a second data electrode of one of the second driving transistors in the peripheral region; a first insulating interposer is disposed on the data track, and the The first insulating interposer is provided with: a first contact hole for partially exposing the data electrode of the data trace; and a second contact hole for exposing the closed electrode of the interpolar strip; And a third contact hole, wherein the second data electrode of the data trace is exposed; and an electrode trace portion is disposed on the first insulating interposer and the electrode trace portion comprises: a first electrode trace, Passing through the first contact hole to contact the data electrode of the pixel area, and the second electrode trace is connected to the second and third contact holes to connect the first part of the driving transistor The current gate electrode and the exposed second data electrode of the second driving transistor. The substrate of the first aspect of the patent application, wherein the gate line is respectively shaped 1310101. The patent application scope is formed on the pixel area and the peripheral area, and the gate electrode is branched from the gate line. The substrate further includes a low capacitance electrode disposed on a pixel area of the substrate, and the first low capacitance electrode is made of the same film layer as the gate line, the low capacitance electrode system The gate line is separated from the gate line at a predetermined interval and is parallel to the gate line. The substrate of claim 1, wherein the gate line is formed on the pixel region and the peripheral region, and the gate electrode is from the gate wire cutter, and the substrate Further comprising a low capacitance electrode disposed on a gate driving region of a peripheral region of the substrate, and the low capacitance electrode is made of the same film layer as the opening line, and is closed by a line One side edge extends. The substrate of the second paragraph of the patent application of Shishen 4, wherein the active grain system is made of crystal stone. The substrate of the item i of the patent specification, wherein the data electrode comprises a -% electrode or a second electrode, and the first and second electrodes of the first and second driving transistors have an interdigitated structure. The second electrode of the two driving electromagnets has a high capacitance electrode extending toward the first electrode of the first drive: crystal. 7. The substrate of the first aspect of the patent, wherein the first insulating interlayer is made of bismuth telluride. The substrate of the first item of the θ 8 range, wherein the first insulating interposer is formed of a photosensitive organic insulating material. 9. If the patent application scope is 8^, the first insulation order layer 44 1310101 6. The patent application scope has an embossed pattern on one surface thereof. 10. The substrate of claim </RTI> wherein the first, second and second electrodes are comprised of a transparent material. The substrate of the first aspect of the patent application, wherein the transparent material comprises a tin oxide (ITO) or an indium zinc oxide (IZ0). 12. The substrate of claim </ RTI> wherein the active track and the data electrode have first and second end surfaces, respectively, and each of the first and second end surfaces has substantially the same inclination from each other. 13. A substrate for a liquid crystal display panel, comprising: a gate trace, disposed on a pixel region and a peripheral region, and a peripheral driving region and a pad region, the gate region The polar trace has a gate line and a gate electrode of one of the first drive transistors of the peripheral region, and the pixel region and the peripheral region are disposed on the substrate; an active trace and the gate trace Insulating and being disposed on the gate trace; the data trace is electrically connected to a portion of the active trace, and the data trace includes a first electrode, a second electrode, and a first electrode coupled thereto a data line and one of the second driving transistor of the peripheral region; a first insulating interposer is disposed on the data track, and the first insulating interposer comprises: a first contact hole Partially exposing the second electrode: the second electrode of the bead line; the second contact hole, which partially exposes the first electrode of the cell region; and a third contact hole, which can be applied for Patent range reveals the gate pattern The gate electrode; - the data electrode exposing the data trace; and w (four) 'the 7-way subtraction portion is disposed on the "insulation interposer, and the xenon and trace portions include: a first electrode trace, The second source electrode is patterned to be coupled to the first electrode of the pixel region through the second contact hole through a first contact f hole; and a second source electrode trace; a third electrode trace, which is connected through the third: fourth contact hole to connect the exposed idle electrode of the first driving transistor and the exposed data electrode of the second driving transistor. The substrate of the thirteenth aspect is characterized in that the gate lines are respectively formed on the pixel region and the peripheral region, and the drain electrode is branched from the gate line, and the substrate further includes __low The capacitor electrode is disposed on the pixel area of the substrate, and the low capacitance electrode is made of the same film layer as the gate line, and is separated from the gate line by a predetermined interval and parallel to the gate line 15. The substrate of claim 13 wherein the gate line is The gate electrode is formed on the pixel region and the peripheral region, and the gate electrode is branched from the closed line. The substrate further includes a low capacitance electrode, and the gate is disposed in the peripheral region of the substrate. In the pole drive region, the low capacitance electrode is made of the same film layer as the gate line and protrudes from one side edge of the gate line. 16. The substrate according to claim 13 of the patent, wherein the active The pattern is made of a non-crystalline crucible. 17. The substrate of claim 13, wherein the first and second driving 1310101. The first and second electrodes of the patented scope have an interdigitated structure. 18. The substrate of claim 17, wherein the second electrode of the two drive transistors has a high capacitance electrode that extends toward the first electrode of the first drive transistor. 19. The substrate of claim π, wherein the first insulating interposer is made of tantalum nitride. The substrate of claim 13, wherein the first insulating interposer is composed of a photosensitive organic insulating material. 21. The substrate of claim 2, wherein the first insulating interposer is provided with a relief pattern on a surface thereof. 22. The substrate of claim 13 wherein the first The second and second electrode patterns are all made of the same material. 23. A method for manufacturing a substrate, comprising: forming a gate including a gate line on a pixel region and a peripheral region of an insulating substrate; a gate line and a gate electrode forming a second driving transistor of the peripheral region, the gate electrode is branched from the gate line; and subsequently forming a gate on the gate line and the insulating substrate a first amorphous crystalline layer, a second amorphous layer and a metal layer; a photoresist pattern formed on the metal layer, the photoresist pattern having a first electrode and a first - a portion corresponding to one of the channel regions of the electrode, and being thinner than the other portions corresponding to the first electrode and the second electrode; using the "Heil resistance diagram" as a mask to expose the aforementioned exposed metal ΓC ; 1 1310101 Γ: • 2·1310101 6. The patent application scope is to form a photoresist film on the metal layer; the second film exposes a portion of the second electrode region on the metal layer, and a portion of the second electrode region and the second portion The - part of the electrode area will be exposed to - the full degree of exposure, and a second part will be exposed to - below the first - deep household's clothing - depth 'this second part contains the first a portion of the second electrode region and the first electrode region, the second electrode region and the first electrode region; and Φ develop and remove the first and second portions of the exposed green film. 25.: Application: Patent Range The method of claim 24, wherein the first amorphous layer, the second amorphous crystalline layer, and the metal layer are formed by the _pecvd method. The method of claim 24, wherein the light (four) is a positive-type first resist film' and the photoresist pattern is formed using a mask having a light-transmitting region and an opaque region, and the mask is between the channel region and the second region and the channel region a slit is provided at a light transmissive area between the first region and the first region, as in the method of claim 24, At least one of the exposed metal layer, the second amorphous 7 layer and the first non-junction (four) layer is removed by dry button etching so that the second portion of the photoresist pattern can form the (four) grain In the step of the present invention, when the metal layer is exposed and the second amorphous layer (4) is removed from the first amorphous layer, the method of claim 23, wherein the insulating interposer is The method of claim 23, wherein the first and second electrode patterns are composed of ITO or IZO. 30. The method, wherein the first and second electrodes t S! 49 1310101 6. The patent application range is composed of an opaque metal film, and the insulating interposer is made of a photosensitive organic insulation having an embossed pattern structure. 31. A method for manufacturing an LCD panel substrate, comprising the steps of: forming a closed-pole line including a gate line and forming a first one on a pixel region and a peripheral region of an insulating substrate Drive battery B a gate electrode of the body, the closed electrode is branched from the idle line; the second amorphous layer and the gate insulating film are formed on the insulating substrate provided with the gate pattern, and a first non- Forming a ruthenium layer-metal layer; forming a photoresist pattern on the metal layer; using the photoresist pattern as a mask, the metal layer, the doped non-, the 曰 曰 layer and the amorphous layer Patterning to remove the metal layer of the channel region and to form a data pattern including a second electrode, a first electrode separated from the second electrode, and a data electrode of the second driving transistor of the peripheral region; The photoresist pattern and the second non-crystalline germanium layer of the channel region; forming a first insulating via hole on the composite structure of the insulating substrate, and insulating the first insulating interposer to form: a first contact Partially exposing the first electrode of the pixel region; a second contact hole partially exposing the second electrode of the pixel region; and a third contact hole exposing the first driving of the peripheral region a gate electrode of the transistor; a fourth contact hole, which can expose the data pattern 50. The data electrode of the patent application scope; and a conductive material formed on the first insulating interposer having the first, second, third and fourth contact holes And patterning the conductive film to form a first electrode trace, a second electrode trace, and a third electrode trace, the first electrode trace being connected to the second electrode of the pixel region through the first contact hole The second electrode trace is connected to the first electrode of the pixel region through the second contact hole, and the third electrode trace is connected to the exposed gate electrode of the first driving transistor through the third and fourth contact holes. A data electrode exposed to the second drive transistor. 32. The method of claim 31, wherein the step of forming the photoresist pattern comprises the following steps: continuously forming the gate insulating film on the gate trace and the insulating substrate, the first-non- Crystallization (4), second amorphous 7 layer and metal layer; forming a photoresist film on the 5 metal layer; exposing the photoresist film, wherein the second electrode region on the metal layer and the first electrode region The portion and the second portion of the second electrode region and the first electrode region are exposed to a first depth of full exposure and the first portion is exposed to a second ice lower than the first depth a portion of the second electrode region and the first electrode region, the second electrode region and the first electrode region; and developing and removing the first and second portions of the exposed photoresist film section. 33. The method of claim 32, wherein the first amorphous layer, the second amorphous layer, and the metal layer are produced by the _pEcvD method. Ϊ310101, Patent Application No. 3 (such as the method of claim 32, wherein the photoresist film is a positive photoresist film) and the photoresist pattern is used as a light-transmitting region and an opaque region The mask maker's and the mask is provided with a slit between the channel region and the source region and between the channel region and the drain region. 5, such as Shen Qing patent|έ围第32 The method of claim, wherein at least one of the metal layer, the second g, .-α Β曰矽 layer, and the first amorphous ruthenium layer are removed by dry etching to make the second portion of the photoresist pattern In the step of forming the data texture, when the metal layer is exposed and the second amorphous layer 11 and the first amorphous layer are removed, it is removed. The method, wherein the insulating interposer is made of an inorganic insulating material or an organic insulating material. 37. The method of claim 32, wherein the first, second, and second electrode patterns are all ΙΤΟ or ΙΖ0 39. 38. The method of claim 32, wherein the first, second and third The pattern is composed of an opaque metal, and the insulating interposer is a photosensitive organic insulating film having a embossed pattern on one surface thereof. The method for manufacturing a substrate comprises: one pixel on an insulating substrate Forming a gate trace on the region and a peripheral region, the gate trace having a gate electrode of the first driving transistor of the peripheral region; forming a gate insulating film on the insulating substrate having the gate trace Forming an active trace on the gate insulating film, the active trace comprising a semiconductor layer; Τ. i Γ: 1. 1310101 The patent application scope is formed into a data pattern, comprising: a first electrode, a second electrode, a data line coupled to the second electrode, and a data electrode of the second driving transistor of the peripheral region; Forming an insulating interposer on the data track; Partially etching the insulating interposer to form: a first contact hole that partially exposes the first electrode of the photo cell region; and a second contact hole that exposes the gate trace a gate electrode; and a second contact hole for exposing the data electrode of the data trace; forming a conductive film on the insulating interposer provided with the first, second and third contact holes; Patterning the conductive film to form a first electrode trace and a second electrode trace, the first electrode trace being listened to the first electrode ' of the pixel region via a first contact and the second electrode trace And connecting the exposed gate electrode of the first driving transistor and the exposed data electrode of the second driving transistor through the second and third contact holes. 40. The method of claim 39, wherein the gate trace comprises a gate line and a gate electrode 'the gate (four) is formed on the pixel region and the peripheral region respectively> and the gate The f-pole is branched from the gate line, and the inter-polar line is made of the same film layer as the gate line, and further includes: a first low-capacitance electrode, with a predetermined interval and the request The pole lines are separated and parallel to the gate line; and the second low capacitance electrode is disposed on a peripheral region of the insulating substrate and protrudes from the U of the gate line. 41. The method of claim 39, wherein the surrounding area comprises a Γ C | -53 - 1310101 6. The patent application area covers the closed-circuit drive area and the pad area, and the gate of the gate drive area contains the second and the first of the first and second drive transistors: The method of claim 41, wherein the first electrode of the first driving transistor of the gate driving region has a high capacitance An electrode extending toward the second electrode of the second driving transistor. The method of claim 39, wherein the active track is composed of amorphous slabs. 44. A method of manufacturing a substrate, The method comprises: forming a gate trace on the pixel region and the peripheral region of the insulating substrate, the interpolar strip having a gate electrode of the first driving transistor, and having the gate trace Forming a gate insulating film on the insulating substrate; % forming H (four) on the gate, the wire track comprising a semiconductor layer; and forming a data trace comprising a first electrode and a second electrode - face to the a data line of the source electrode, and a data electrode of the second driving transistor of the peripheral region; forming an insulating interposer on the data trace and the gate insulating film; partially engraving the insulating interposer Formed: a first contact hole, which partially exposes the first electrode of the pixel region; a second contact hole that partially exposes the first electrode of the pixel region; and a third connection 54 1310101 a patented range of contact holes for exposing the gate electrode of the gate trace; and a fourth contact hole for exposing the data electrode of the data trace; wherein the first and second electrodes are provided Forming a conductive film on the first insulating interposer of the third and fourth contact holes; and patterning the conductive film to form a first electrode trace, a second electrode trace, and a second electrode trace, the The _ electrode trace is coupled to the second electrode of the pixel region through a first contact hole, the second electrode trace is permeable to the second contact hole to the first electrode of the pixel region and the second electrode The texture is transmitted through the third and fourth The contact hole is connected to the exposed electrode electrode of the first transistor and the exposed data electrode of the second transistor. The method of claim 44, wherein the gate line comprises a pole line And a gate electrode, wherein the gate line is formed on the pixel region and the peripheral region, and the gate electrode is branched from the (four) pole line; and the gate line is connected to the gate line The same film layer is formed, comprising: a first-low capacitance electrode separated from the gate line by a predetermined interval and parallel to the secret line; and a second low capacitance electrode is disposed on the substrate The peripheral region is formed by the same film layer as the gate line and protrudes from the side of the gate line. 46. The method of claim 44, wherein the peripheral region comprises a An inter-electrode driving region and a pad region, the data pattern of the gate driving region includes second and first electrodes of the first and second driving transistors, and the second and first electrodes have a finger-like shape structure. 47. The method of claim 46, wherein the (four) pole drive region is fr: -ι. ΐ. w J 1310101 6. The patent application range * The first electrode of the driving transistor has a high capacitance electrode, the system Extending toward the second electrode of the second drive transistor. 48. A substrate for a liquid crystal display panel, comprising: a gate trace formed on a pixel region and a peripheral region, the peripheral region having a gate driving region and an interface region, the y pole The texture has a 1-pole line and a -first driving electric &quot; gate electrode of the peripheral region, and the pixel region and the peripheral region are disposed on the substrate; the moving, 'text path, is insulated from the gate line And on the gate line, the active track comprises a semiconductor layer; = the bead line is electrically connected to one of the active lines, 5 - the bead material, the text path has the peripheral area - the first a data electrode of one of the two driving transistors; and a first insulating interposer formed on the data track; wherein the cell region includes a plurality of pixels and an active pattern composed of amorphous germanium. 49. The substrate of claim 48, wherein the pixels each comprise an electrical as body, and the peripheral regions comprise a plurality of drive transistors $ to drive the first transistors of the pixels. The substrate of the 48th item of the factory/patent scope wherein the data pattern comprises a shell material, the first insulating interlayer has: a first contact hole for exposing the data pattern to the shell electrode portion a second contact hole for exposing the gate electrode, a third contact hole for exposing the data electrode of the data path; and the substrate further comprises T C-1 · 56 1310101 s. Patent Application Scope - an electrode grain portion formed on the first insulating dielectric layer, the electrode grain portion including a first contact hole through the first electrode and the data electrode of the pixel region - An electrode trace, and a second electrode trace through which the second and third contact holes are connected to the exposed gate electrode of the first driving transistor and the exposed data of the second driving transistor electrode. 51. The substrate of claim 48, wherein the first, second and third electrode traces are comprised of a transparent material. 2. The substrate of claim 51, wherein the transparent material comprises indium tin oxide (ITO) or indium zinc oxide (IZ〇).