TWI309875B - Non-voltaile memory cells, memory arrays including the same and methods of operating cells and arrays - Google Patents

Description

。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 US Patent Provisional Application No. 60/647,012, filed on Jan. 27, 2005, and U.S. Patent Application Serial No. 60/689,231, filed on June 10, 2005; Priority of the Patent Provisional Application No. 60/689,314, the entire disclosure of each of which is incorporated herein by reference. [Prior Art] Non-volatile memory (NVM) refers to a semiconductor memory that continuously stores information even when a power supply is removed from a few pieces of the NVM unit. NVM includes masked read-only memory (Mask R〇M), programmable read-only memory (PRGM), erasable programmable read-only memory (EpRQM), and electrically erasable programmable read-only memory Body (EEPROM), and flash memory. Non-swing = memory system is used in semiconductor production # and the rest is developed to prevent the loss of a type of memory. Typically, non-volatile memory can be programmed, read, and/or erased by the end user, and the stylized data can be stored for a long period of time. The unit's if-like memory element can have a variety of designs. NVM compound =: ??, - oxide-nitride-oxygen wear and erase operation. Although this; direct tunneling also occurs at low electric field strengths that may exist during the period of providing the same 681939-27U3 1309875 state. Another NVM design is NROM (nitrided read-only memory), which uses a thicker tunnel oxide layer to prevent charge loss during the hold state. However, a thicker tunnel oxide layer may affect the channel erase rate. As a result, an interband tunneling thermal tunnel (BTBTHH) erasing method can be used to inject a hole trap to compensate for electrons. However, the BTBTHH erasing method may cause some reliability problems. For example, features of NROM components utilizing the BTBTHH erase method may degrade after multiple P/E (stylization/erasing) cycles. Therefore, there is a need in the art for non-volatile memory cell designs and arrays that operate multiple times (stylized/erased/read) with improved data retention and increased operating rates. SUMMARY OF THE INVENTION The present invention is directed to non-volatile memory elements, and more particularly to non-volatile memory elements including a tunnel dielectric structure that facilitate self-convergence erase operations while also maintaining memory elements during the hold state The charge in the charge storage layer remains. A specific embodiment of the present invention includes a memory unit including: a semiconductor substrate having a source region and a drain region disposed under a surface of the substrate and separated by a channel region; a tunnel dielectric structure Provided on the channel region, the tunnel dielectric structure includes at least one layer having a small hole tunneling barrier height; a charge storage layer disposed on the tunnel dielectric structure; an insulating layer The device is disposed on the charge storage layer; and a gate electrode is disposed on the insulating layer. Another embodiment of the present invention comprises a memory unit comprising: a half of a 681939-27U3 7 1309875 conductor base hole open to the 丞 丞 — — — — — — — — — — — — — 且 且 且 且 且 且 且 且 且 且 且 且- bungee region; - multilayer tunnel dielectric junction 2: f placed on the ahai channel region, the multilayer tunnel dielectric structure comprising IW, a at least one layer of the barrier height; a charge storage layer; a dielectric structure; an insulating layer disposed on the = layer and a gate electrode disposed on the insulating layer. In some preferred embodiments, the layer provided with a small hole tunneling barrier may contain materials such as tantalum nitride (9) or oxidized (Hf2). In some preferred embodiments of the invention, the memory cells comprise a stacked dielectric dielectric structure having a plurality of layers of tunnel dielectric structures, such as hafnium oxide, tantalum nitride, and hafnium oxide. These tunnel dielectric structures provide a S0N0N0S (Shixi-Oxide-Nitride-Oxide-Oxide-Oxide-Y) or Superlattice S0N0N0S design. In some preferred embodiments of the invention, the tunnel dielectric structure can comprise at least two dielectric layers, each layer having a thickness of up to about 4 nanometers. Moreover, in some preferred embodiments of the invention, the gate electrode comprises a material having a work function value greater than Ν + polysilicon. In some preferred embodiments, the interposable dielectric structure can include a layer of material comprising a small hole tunneling barrier height wherein the material is present in the layer with a concentration gradient such that the concentration of the material is One of the deep points in the layer is the maximum. The invention also includes a non-volatile memory element comprising a plurality of memory cells (i.e., an array) in accordance with one or more embodiments described herein. As used herein, "plural" means two or more. The 681939-27U3 8 1309875 in accordance with the present invention exhibits significantly improved operability f, including increased erase rate, improved hold, and larger operational window. The invention also includes operating the non-volatile memory unit and:::: The method of operation includes resetting the memory element by applying a compact vt distribution of the self-contained cow; and reading the channel by means of channel injection And at least one of the memory elements is read by at least one of the erased state level and the stylized state level. As used herein, the quasi-name (2) 2" system causes the threshold voltage distribution in many memory cells of the array to be degraded. In general, the threshold voltage distribution is "compact" in which if the voltages are within a narrow range of each other, the operation of the array is improved over the conventional one. For example, 'in some preferred embodiments', as in the array comprising memory cells according to the invention or in the specific embodiments

The threshold voltage distribution of It's compact indicates that the threshold coatings of the various memory cells are tied to each other at G.5Vft_. In other array architectures using memory cartridges in accordance with the present invention, the "compact" threshold voltage distribution can have a range from about an upper limit to a lower limit of about 1.0 volts. a specific embodiment of the method of operation according to the present invention includes an operation according to the array of the moons, which is to reset/erase the voltage by applying a self-convergence to the substrate, and to set/erase the substrate in each memory unit and a gate electrode; stylizing the plurality of memory cells at least - the voltage between the erased state level and the stylized state level is applied by the application-in-memory memory element to read the plurality of memories At least one of the units. The invention also includes a method of forming a memory cell, comprising: providing a 681939-27U3 1309875 semi-body substrate having a source region and a drain region formed under the surface of the substrate and separated by a - pass region Forming a channel-forming dielectric structure on the =channel region, the towel forming the saddle dielectric structure comprising forming at least two dielectric layers': the at least two dielectric layers have a layer having a ratio of at least two dielectric layers The other layer also has a small hole through the barrier height; a charge storage layer is formed on the tunnel dielectric structure; an insulating layer is formed on the charge storage layer; and a gate electrode is formed on the insulating layer. For example, the phrase "small hole penetration with barrier height" is generally used to refer to the system; or it is specific to the value of the barrier height of the oxidized stone. In particular, the small hole penetration height is preferably less than or equal to about 4.5 eV. More preferably, the small hole tunneling barrier height is less than or equal to about i 9 eV. [Embodiment] The present invention and its preferred embodiments will now be described in detail, and examples thereof are illustrated in the accompanying drawings. Wherever possible, the same or similar components will be referred to in the drawings. It should be noted that the graphics are in a greatly simplified form and are not in exact proportions. With respect to this disclosure, directional nouns (such as top, bottom, left, right, top, bottom, above, below, below, after, and month) are used for the sake of convenience and clarity. The directional terminology used in the following description with reference to the accompanying drawings is not to be construed as limiting the invention in any manner that is not explicitly described in the appended claims. Although some exemplary embodiments are described herein, it is to be understood that the specific embodiments are illustrative and not limiting. It should be understood that the process steps and structures disclosed herein do not cover the complete process for fabricating the entire integrated circuit. The present invention can be implemented or developed in conjunction with various integrated circuit fabrication techniques well known in the art as 681939*27U3 10 1309875. The § memory unit according to the present invention can overcome the problem of the 之 Α 性 性 in the S〇N〇s and nr〇m elements. For example, the memory cell junction L according to the present invention allows the TM channel erasing method while maintaining a good charge retention. The specific embodiment of the BTBTHH erasing method can also alleviate the dependency and avoid the multi-P/E cycle. Degradation. The second is a barrier layer in which the tunnel dielectric structure-multilayer structure of the person i, (4), 'Ultra-thin channel dielectric or 'ultra-thin oxide layer junction 222. This provides better stress relief. After the = amount retreat, the non-volatile memory unit according to the present invention is also displayed. According to the memory unit of the present = n-channel or p-channel design can be used, and L2:: is shown. Figure 1 "Miao's invention - a specific embodiment of η: a cross-sectional view. The memory unit includes - contains at least: type = area 102 and 104... base ι〇ι, wherein each of the pushes: as shown in Figure 3 In addition, the voltage (4) is secret or bungee. For reference purposes, the doping region 102 can serve as a source impurity (he 104 can serve as a drain. The bamboo includes a channel region 106. In the pass = in: square = doping interval - step The dielectric structure 12 can be contained above the surface of the substrate 101 (on the surface of the substrate 101, the system-channel dielectric structure 120: surface). It can comprise three layers of thin structure:;;: barrier high barrier nitride layer m system Cooling under a thin oxygen dioxide; 2 = thin gasification layer 126. Memory unit (10) further includes: dao = 681939-27U3 11 1309875 structure 120 on the charge trapping (or charge storage) layer 130 (more Preferably, an insulating layer 140 (preferably comprising a barrier oxide) is disposed on the charge trapping layer 130. A gate 150 is disposed over the insulating layer 140. Figure lb depicts an embodiment in accordance with the present invention A cross-sectional view of a p-channel memory cell 200. The memory cell includes an n-type substrate 201 having at least two p-type doped regions 202 and 204, each of which The doping regions 202 and 204 may function as a source or a drain. The substrate 201 further includes a channel region 206 in the two p-type doping region. The p-channel memory cell 200 also includes a tunneling layer including a three-layer thin germanium structure. The electrical structure 220 (where a small hole tunneling barrier nitride layer 224 is sandwiched between a lower thin oxide layer 222 and the upper thin oxide layer 226), a charge trapping (or charge storage) layer 230, The insulating layer 240 and a gate 250. Therefore, as described in, for example, FIGS. 1a and 1b, the memory unit according to the present invention may include: a multilayer film tunnel dielectric structure including a first oxide layer 01, a first nitride layer N1 and a second oxide layer 02; a charge storage layer, such as a second nitride layer N2; and an insulating layer such as a third tantalum layer 03, On or above the substrate of the semiconductor body (e.g., germanium substrate). The tunneling dielectric structure allows holes to tunnel from the substrate to the charge storage layer during memory device erase/reset operations. Preferably, one of the present inventions The tunnel dielectric structure in the non-volatile memory unit has Neglected charge trapping efficiency, and more preferably no charge is trapped during memory operation. Charge storage materials such as tantalum nitride layer, HfO 2 and Al 2 〇 3 can be used as small hole tunneling in tunnel dielectric structures A barrier level layer. In some preferred embodiments of the invention 681939-27 U3 12 1309875, such as nitriding as a charge storage layer in a memory element. Preventing a storage material from being used as an insulating layer 'eg, a third oxygen cut 3 The barrier oxide unit also includes a pole or a memory electrode according to the present invention on the insulating layer. The tunnel dielectric structure and the charge storage bank "pole", for example, at least one channel region and the gate electrode on the polysilicon gate base can be formed in the pole region U system is disposed in the system. The source region and the source region are in various The memory unit of the specific embodiment includes - tunneling

10^ΐΓΓ "J" '2〇V ^^a(Vg)TT TM erasing rate. On the other hand, it can still be maintained; in some cases, it may be more than many conventional s_ electricity: the same money Γ ^ invented money unit can also avoid the use of band-to-band heat ί==: is used in the general 0M component . Avoid this band: avoiding the large loss of thermoelectric holes to introduce damage, and therefore avoiding the need to meet the demand. Referring to FIG. 21, the experimental measurement value of the voltage of the dielectric, and the mouth structure according to the present invention - (4) the real (4) channel, the display - ultra-thin 01 / Ν 1 / 〇 2 recording structure can have - negligible _ efficiency, such as The money continues to be verified by the constant threshold voltage level under the stylized pulse. In the example for the purpose of the test of 2, the thickness of 〇1/Ν1/〇2 is 3G, 3〇 and 35 Å, respectively. As shown in Figure 2, in the use of various methods of stylization (ie _FN stylization, rotten stylization and CHE (channel hot electron) stylized) in the Xuan m (four) process, the limit power Vt remains stable at near (nine) 19 volt. Therefore, this ultrathin 01/N1/02 film can be used as a -modulation tunnel dielectric structure. The results under various charge injection methods including cm, 681939-27U3 1309875 + FN and -FN all show negligible power gain. The process or component structure can be designed to minimize interface trapping so that the 01/N1 or N1/02 interface is functional. 3 shows an erase feature of a memory cell having a design of s〇N〇N〇s in accordance with an embodiment of the present invention. The memory cell of the embodiment illustrated in Figure 3 comprises a tunnel C C2, thickness of 15 angstroms, 20 angstroms and 18 angstroms, respectively. The n_MOSFET design. The memory cell of this embodiment comprises a tantalum nitride charge storage layer having a thickness of about 70 angstroms, a thickness of about 90 angstroms, a tantalum oxide layer, and a gate comprising any suitable conductive material, for example, =3⁄4 • Doped polycrystalline stone. Referring to Figure 3, a fast fn erase (e.g., within 10 strokes) can be achieved and can also be obtained - excellent self-convergent erase properties. Figure 4 shows the charge retention feature of the SONOS element of a particular embodiment of the memory cell of the present invention as described with reference to Figure 3. As shown, these = & S_s components are better, and the current value may be higher than multiple levels. (4) an energy band diagram containing at least a tunnel-like dielectric structure, wherein the at least one layer has a small dielectric hole with a barrier dielectric structure under a low electric field that may exist during memory data retention (this) In the example, the energy band diagram of MKFl U 1 /〇2 three layers) is in Ί a. It is possible to remove the band offset as shown by the dotted arrow at the low n? resistance n. Figure 5b shows that a barrier effect can be reduced by N1 and (7) so that direct wear through 〇1 can occur. Once there is a level of electric power barrier to the level of riding the dielectric can be allowed to feed 6S1939-27U3 14 1309875 effect FN erase operation. Figures 5c and 5d show another set of energy band diagrams in one example. For a preferred band offset condition in an example, the thickness of N1 may be greater than 〇ι. The energy band diagram of the valence band is plotted at the same electric field E_l4Mv/em. According to the WKB approximation, the possibility of wear is related to the shaded area. In this example, for the thickness Nl = () 1, the band offset is not completely dependent on the barrier of 02. On the other hand, for N1 > 01, the band offset can be easier to block (7). Therefore, for the thickness Ν1 > 〇1, the hole penetration current may be large under the same electric field of the (1) towel. An experiment with measured and simulated hole-through currents (shown in Figure 6) further describes the electrical-time tunneling of a pass-by-channel dielectric structure in accordance with certain embodiments of the present invention. For example, a hole penetration current of 01/m/〇2 dielectric can fall between an ultra-thin oxide and a thick oxide. In one example, under high electric fields, the hole-through current can approximate an ultra-thin oxide. However, under low electric fields, direct wear can be suppressed. As shown in Fig. 6, even in the electric field strength of only mv/cm # (four), the hole current can be detected through the thin oxide layer. The hole tunneling current is negligible through the thick oxide at a relatively high electric field strength of, for example, n_13 MV/cm. However, when high electric field strength occurs, the hole through the - ΟΝΟ dielectric structure will follow a current to a thin: oxide layer. In Fig. 6, a large current leakage due to tunneling through a thin oxide in a low electric field hole can be seen in the area 图 in the figure. In Fig. 6, the hole-through current through the -q/〇2(d)-t structure at high electric field strength can be seen in the region B in the figure. In Figure 6, the tunneling current of 681939-27U3 15 1309875, which is substantially absent through the - 01/N1/02 channel dielectric structure and thick oxide at low electric fields, can be seen in region c of the figure. The memory cell design in accordance with the present invention can be applied to a variety of memory types including, but not limited to, NOR and/or NAND type flash memory. As described above, the tunnel dielectric layer may include two or more layers, including one layer that provides a small hole tunneling barrier height. In one example, the layer providing a small hole tunneling barrier height may contain tantalum nitride. The layer can be sandwiched between the two layers of oxidized stone layers, and if the tantalum nitride is used as the intermediate layer, an O/N/O channel dielectric can be formed. In some preferred embodiments of the invention, the layers in the tunnel dielectric structure are up to about 4 nanometers thick. In some preferred embodiments, the thickness of each layer in the intervening dielectric structure can range from about 1 nm to about 3 nm. In an exemplary component, a three-layer structure may have a bottom layer (eg, a hafnium oxide layer) of about 1 Q angstrom to 30 angstroms, an intermediate layer (eg, a tantalum nitride layer) of about 1 〇 to 3 〇, And a top layer of about 1 〇 to 3 〇 (for example, another layer of yttrium oxide). In a specific example, a three-layer structure having a bottom oxide oxidized layer of -15 angstroms, an intermediate nitride layer of -2 angstroms, and a top yttrium oxide layer of 18 angstroms may be used. In one example, a thin tantalum/N/〇 three-layer structure exhibits negligible charge trapping. The theoretical energy band diagram and the follow-through current analysis described in references 5a, 5b, and 6 may suggest a tunnel dielectric structure. (eg one or less (1) Qing 02 structure), can be held during the hold = = hole directly (four). (d) 'In the high electric field, effective holes can still be allowed to wear. This may be due to the band offset, which can effectively conceal the shackles and the obstacles. Therefore, this built-in component can mention the county speed hole? _ In addition, the customary QS component protection issues. Experimental analysis shows the excellent durability and retention properties of the memory cells of the various embodiments of 681939-27U3 16 1309875 in accordance with the present invention. In some preferred embodiments, the tunnel dielectric structure includes at least one intermediate layer and two adjacent layers on opposite sides of the intermediate layer, wherein the intermediate layer and the two adjacent layers each comprise a first material and a second material Wherein the second material has a valence band level greater than a valence band level of the first material, and the second material has a conduction band level that is less than a conduction band level of the first material; and wherein the second material The concentration is higher than the intermediate layer between two adjacent layers, and the concentration of the first material is higher in the two adjacent layers than in the intermediate layer. Preferably, in a tunnel dielectric structure in accordance with this embodiment of the invention, the first material comprises oxygen and/or oxygenates and the second material comprises nitrogen and/or nitrogen containing compounds. For example, the first material can include an oxide (e.g., hafnium oxide) and the second material can include a nitride, such as Si3N4 or SixOyNz. The tunnel dielectric in accordance with this aspect of the invention may be comprised of three or more layers, all of which may contain similar elements (e.g., Si, N, and yttrium) as long as the concentration of the material having the minimum hole tunnel barrier height is intermediate The inner layer of the layer is higher than the two adjacent layers. In a tunnel dielectric structure according to a prior embodiment of the present invention, the second material may be present in the intermediate layer in a gradient concentration such that the concentration of the second material in the intermediate layer is increased from an adjacent layer/intermediate layer interface to The maximum concentration at a deep point in the intermediate layer, and from the deep point of the maximum concentration to a lower concentration at the interface of the other adjacent layer/intermediate layer. The increase and decrease in concentration is preferred to be progressive. In still another embodiment of the present invention, the tunnel dielectric structure includes at least one intermediate layer and two adjacent layers on opposite sides of the intermediate layer, wherein the two adjacent 681939-27U3 17 1309875 layers comprise a first material and an intermediate layer Including a second material, the price of the material can be higher than the first material, the material level of the material, and the second material = the energy level of the v material is less than the conduction energy of the first material. With a level; and wherein the first material is present in the intermediate layer according to a gradient concentration, such that the material/length in the intermediate layer increases from an adjacent layer/intermediate layer interface to an intermediate layer-inside point The maximum concentration, and from the deep point of the maximum concentration to the lower concentration at the other adjacent layer/intermediate interface. The increase and decrease in concentration is preferred to be progressive. Preferably, in the conventional dielectric structure according to this embodiment of the invention, the first material comprises oxygen and/or an oxygen-containing compound and the first material comprises nitrogen and/or nitrogen-containing compounds. For example, the first material may comprise an oxide (e.g., hafnium oxide) and the second material may comprise a nitride (e.g., Si3N4 or Six〇yNz). For example, in a specific embodiment of the invention in which the tunnel dielectric layer comprises a three-layer 〇N〇 structure, the bottom oxide layer and the top oxide layer may comprise two gas fossils, and the intermediate nitride layer may be, for example, nitrogen oxynitride. And the composition of the gas fossil eve, • wherein the concentration of nitrogen cut (ie, the material having a smaller hole with the height of the barrier) is not fixed in the layer, but is between the two interfaces with the sandwiched oxide layer. The maximum point is reached at some deep points in this layer. The precise point in the intermediate layer in which the material having the smallest hole penetration ρ and the height of the barrier reaches its maximum concentration is not _ as long as it occurs according to the gradient and reaches in the intervening dielectric layer at some point in the intermediate layer Its maximum concentration. Gradient concentrations of materials having small holes that follow the barrier height can be beneficial for improving various properties of non-volatile memory elements, especially those having SONONOS or SONONQS-like structures. For example, it can be reduced to maintain the shape of 681939-27U3 18 1309875 ^ electric field, can improve the hole in the high electric field (four), and to the extent possible to avoid the charge in the surface dielectric (four). Change: === Buha beneficially repair material wave change: = Legacy: Two minimum hole penetration with barrier height is shown by nitriding (4) I system through a band diagram. Intermediate layer (layer 2) Layer 2 The middle gasification sand layer (layer 1 and layer 3) is composed of sulphur dioxide eve. The level of the money towel will be materialized, (4) the valence band can be used to guide the material and the ti value. The nitrogen Γ is the highest layer 2 (4) Degree reaches the maximum gentry-g concentration; ^ is the two possible nitriding dream concentration gradients, the system's production = the variable price band and the conduction band level "sex - J le It is shown that by means of a dotted line, the three-conducting energy level in the layer 2, the level of the band, and the highest level of the dielectric structure of the embodiment can be two d::=^r The method includes, but not f1, the phase deposition process. - the intermediate 曰 with a gradient concentration of _, for example via a chemical vapor deposition method, or alternatively an excess oxide formed by the sun or the second oxide or an oxide layer on the chemical vapor phase) For example, by oxidizing as a charge storage layer of 6S1939-27U3 19 1309875, in the following example, it can be constructed on the medium. In a van storage layer. In the case of - (4), = a charge of about 5 nm to 1 G nm. H7 nanometer or thicker nitridation on the charge storage layer, for example, can make the (four) 9 nm thick oxygen layer, the at least one of the ytterbium oxide layer, and the thermal layer be used to form a suitable The material forms an oxygen cut layer. Any known or to be developed method of the m (four) layer is described herein to form or form an intervening dielectric layer, a charge storage layer and/or an insulating layer. Suitable & methods include, for example, thermal growth methods and chemical vapor deposition methods. In one example, the thermal conversion process can provide a high density or concentration interface trap that can increase the trapping efficiency of the memory element. For example, the thermal conversion of the nitride can be carried out at about 1000 〇C, while the gate flow ratio is H2: 02 = 1000: 4000 sccm. In addition, since tantalum nitride has a very low (about 19 eV) hole barrier, its tunneling to the hole can be made unobstructed under a high electric field. At the same time, the total thickness of a tunnel dielectric (e.g., germanium structure) prevents electrons from tunneling directly under low electric fields. In one example, this asymmetrical behavior can provide that the 丨 丨 元件 element not only provides fast hole tunneling erase, but also reduces or eliminates charge bubble leakage during retention. An exemplary component can be fabricated by 0.12 micron NROM/NBit technology. Table 1 shows the component structure and parameters in an example. The tunnel dielectric with an ultra-thin 0/N/0 can change the tunnel tunneling current. In one example, a thicker (7 nm) N2 layer acts as a charge trapping layer and a 3 (9 nm) layer acts as a barrier layer. Both N2 and 03 can be fabricated using NROM/NBit 681939-27U3 20 1309875 technology. Table 1 Layer Approximate Thickness (Angstrom) Bottom Oxide (01) 15 Intermediate Nitride (N1) 20 Intermediate Oxide (02) 18 Occupied Nitride (N2) 70 Barrier Oxide (03) 90 Gate: N+ Polycrystalline Length of the stone channel: 0.22 micron channel width: 0.16 micrometers In some preferred embodiments of the invention, a gate may comprise a material having a work function greater than that of the N+ polysilicon. In some preferred embodiments of the invention, the high work function gate material may comprise a metal such as platinum, rhodium, tungsten, and other precious metals. Preferably, the work function of the gate material in these embodiments is greater than or equal to about 4.5 eV. In a particularly preferred embodiment, the gate material is a high work function metal such as a start or a silver. In addition, preferred high work function materials include, but are not limited to, P+ polysilicon, and metal nitrides such as titanium nitride and tantalum nitride. In a particularly preferred embodiment of the invention, the gate material is included in white. Exemplary components having a high work function gate material in accordance with a preferred embodiment of the present invention may also be fabricated using 0.12 micron NROM/NBit technology. Table 2 shows the component structure and parameters in an example. The tunnel dielectric with an ultra-thin 0/N/0 can change the tunneling current. In one example, 681939-27U3 21 1309875 - a thicker (7 nm) layer can serve as a charge trapping layer and a (1) (9 nm) layer can serve as a barrier layer. Both N2 and 03 can be made using Saxian technology. Table 2

Bottom oxide intermediate nitride 20 intermediate oxide 18 trapping nitride asm 70 _ barrier oxide _ _______ gate channel length ~__ : turn----------- 0.22 micron channel width: 0.16 micron A memory unit having a high work function gate material exhibits much improved erase properties than other embodiments in accordance with an embodiment of the present invention. The high work function ❿ gate material suppresses the gate electron injection trapping layer. In some embodiments of the invention, the memory cell includes an N+ polysilicon gate during which the hole tunnels to the charge trapping layer and simultaneously gate electron injection. This self-convergence erase effect results in a higher threshold voltage level in the erased state, which may not meet the requirements in a -NAND application. A memory cell having a high power-function gate material embodiment in accordance with the present invention can be used in various types of memory applications, including, for example, NOR and NAND type memory. However, a memory cell having a high work function gate material embodiment in accordance with the present invention is particularly suitable for use in NAND applications where the threshold is raised in the erase/reset state. 681939-27U3 22 1309875 The voltage may not meet the requirements. The memory cell having the high work function gate material according to the present invention can be erased by a hole tunneling method and preferably by a -FN erase operation. An exemplary component having a tunneling dielectric and an N+ polysilicon gate can be programmed by conventional SONOS or NROM methods and erased by a channel FN via. Figure 7a shows an erase feature of an exemplary SONONOS component having a tunneling dielectric in an example. Refer to Figure ^' A higher gate voltage results in a faster erase rate. It also has a higher saturation Vt because the gate implant is also stronger and produces a dynamic balance (which is higher than Vt). The right hand side of the figure shows that the threshold voltage is a minimum of about 3 to about 5 volts depending on the thickness of the shoe. The hole passing current can be extracted by the transient analysis method by the curve in the differential graph h. From Figure 7a. The measured hole current system of the measured values is shown in Fig. 6 as discussed above. The two-dimensional vehicle also uses the WKB approximation to draw the simulated hole. :: Over = fruit and pre: It is reasonable. In the high electric field, wear with electricity; π 02 heap to reach the super thin, while its system is closed under low electric field. In the memory cell of the high-function-function gate material, some of which are low-intensity gate-injection, the energy is much lower, and in some cases, the threshold voltage component of the component (where the gate is based) The threshold value of the present invention - the memory structure of the specific embodiment and the channel dielectric layer including the 1 Na 1 display, the _FN erase selection system is shown in Figure 7b. As shown in the figure, during the fine-grained voltage (-18V), the component 681939-27U3 23 75

The threshold voltage can be set below _3v. Capacitance is relative to the gate voltage value. . Correspondence of the element is shown in Fig. 7c. Further, in accordance with the present invention, the retention of the 3M element of the A^liter 鬲 work function gate material embodiment has been improved. The negative retention of the memory element with platinum gate is shown in Figure 7d ^ ^ + 嘲 W W, where the capacitance is shown after the erase and the ^ 3 after 3G minutes after each operation and each operation After two hours ~ the gate is turned into a function. Observed _ minimum deviation.

According to the invention, various I* residual scheme operations are employed. For example, the memory unit of the =1 & example can use at least two points to perform the CHE stylization of the -2 bit/single = read _ type . In addition, low power + FN (mode 2) can also be used as _ 1 Α - 7 2 兀 / % element operation. Both modes can use the same hole to wear the technology & t,, h, , and method. The town type 1 is preferably used as a virtual ground array structure of the NOR type flash memory. The mold is preferably used for nand type flash memory.

The example of Fig. 8 shows the excellent durability of the virtual ground array architecture NOR type flash memory in accordance with a specific example of the present invention under mode 1 operation. Erasing degradation of such memory elements having a tunnel dielectric structure does not occur 'because hole tunneling erase (Vg = -15 V) is a uniform channel erasing method. A corresponding IV curve is also shown in Figure 9, which shows a slight degradation of the element after multiple P/E cycles. In one example, this may have good stress relief properties due to the ultra-thin oxide/nitride layer. In addition, the memory element does not suffer from the introduction of thermoelectric holes. Figure 10 is a diagram showing the durability of a NAND type flash memory in mode 2 operation in accordance with an embodiment of the present invention. For faster convergence erase time, a larger bias voltage (Vg = -16V) can be used. 681939-27U3 24 1309875 Excellent durability is also obtained in this example. SON (^rl shows the charge retention of the example 70 pieces according to this (4)-specific embodiment, in which only observed after 1GG hours

Loss of electricity. The current rating of this improvement scheme is better than the conventional 〇S. The VG Acceleration Hold Test also shows that it can be suppressed at low electric fields. 2 Tunneling. Figure 11 shows an example of a VG acceleration guarantee for a 10 ΚΡ/Ε cycle component. The charge loss is under the stress of one-sided second stress, which can suppress the direct tunneling of the hole at the small electric field. Therefore, the S0N0N0S referred to in the above example is designed to have a fast cavity (4) with excellent durability. As indicated above, the memory elements having similar or different configurations are implemented in the N=type nitride memory memory. Included in various embodiments of the array in accordance with the present invention, the read or single subtractive replacement of the learned or SONOS component in a virtual array architecture. It can be solved by using FN holes instead of ‘, , , hole holes to solve or mitigate reliability problems and eradicate degradation. Without limiting the specific structure described below, the town will describe the various methods of operation of the invisible array for the exemplary (10) pseudo-grounded array architecture. CHE or CHISEL (channel abrupt secondary electrons) stylized and reverse readouts are available for 2-bit/cell memory arrays. And the erasing method can be used for the one-two uniform channel FN hole to be erased. In one example, the array architecture can be a virtual ground array or an X array. Referring to Figures 12a-2G, a two-layer structure of two 681939-27U3 25 1309875 01/N1/02 can be used as the dielectric material, and the thickness of each layer is less than about three dimensions to provide direct tunneling of the holes. Referring to Figures 12a-20, N2 can be thicker to provide a high trapping efficiency. An insulating layer (〇3) may be a ruthenium oxide layer formed by wet oxidation, such as a wet-converted top oxide (ruthenium oxide) to provide a dense trap at the interface between 〇3 and N2. 〇3 can be about 6 nm 戍 • Thicker to prevent charge loss from this ruthenium oxide layer. Figures 12a and 12b show an example of a virtual lu ground array architecture incorporating the memory cells discussed above, such as a memory cell having a three layer germanium tunnel dielectric. In particular, Figure 12a shows an equivalent circuit 'of a portion of a memory array' and Figure 12b shows an exemplary layout of a portion of the memory array. In addition, Figure 13 shows a schematic cross-sectional view of several memory cells incorporated into the array. In one example, the buried diffusion (BD) region can be an N+ doped junction for the source or drain region of the quotient cell. The matrix can be a p-type matrix. In order to avoid the collapse of the BD0X region (the oxide on the BD) during the -FN erasing, a thick BDOX (> 50 nm) can be used in one example. Figures 14a and 14b show a possible electronic reset (RESET) scheme for incorporating an exemplary virtual ground array having the above described 2-bit/cell memory cells. All components - before experiencing further P/E cycles - can first go through an electronic "RESET". A RESET process ensures that the Vt of the memory cells in the phase-same array is consistent and the component Vt is raised to a clear erase state. For example, applying Vg = -15 V for 1 second (as shown in Figure I4a) may have the effect of injecting some charge into the charge trapping layer of tantalum nitride to achieve dynamic equilibrium conditions. With RESET, although the memory cell is unevenly charged due to, for example, the plasma charging effect in its process 681939-27U3 26 1309875, its vt can be converged. An alternative to generating a self-converging bias condition is to provide a bias voltage for both the gate and the base voltage. For example, referring to Figure 14b, Vg = -8V and P well = +7V can be applied. Figures 15a and 15b show a stylized recipe for an exemplary virtual ground array for incorporating a 2-bit/cell memory cell having the tunnel dielectric design described above. Channel hot electron (CHE) stylization can be used to program the component. For the Bit-Ι stylization shown in Figure 15a, the electrons are locally injected into the junction edges of the BLN (bitline Lu N). For the Bit-2 stylization shown in Figure 15b, the electronics are stored on the BLN-I. A typical stylized voltage for WL (word line) is typically about 3 to 7V' with a typical stylized voltage of about 6V to 12V° BL (bit line) and keeps the p well grounded. Figures 16a and 16b show a read scheme for an exemplary virtual ground array for incorporating a 2-bit/cell memory cell having the tunnel dielectric design described above. In an example, the 'reverse readout' is used to read this element to perform a 2-bit/cell operation. Referring to Figure 16a, for reading Bit-1, the BLN-I is applied with a suitable read voltage (e.g., 1.6V). Referring to Figure 16b, the read bit-2' BLN is applied with a suitable read voltage (e.g., 16 V). In one example, the read voltage can be in the range of about i to 2V. The word line and P well can be kept grounded. However, other modified read schemes can also be implemented, such as the ^L Vs reverse readout method. For example, a boost vs. reverse buy method can use Vd/Vs=1.8/0.2V for reading Bit-2, and Vd/Vs=〇.2/1.8 for reading Bit-1. Figures 14a and 14b also show a sector wipe 681939-27U3 27 1309875 division scheme for incorporating an exemplary virtual ground array of a 2-bit/cell memory cell having the tunnel dielectric design described above. In one example, a sector erase and channel hole wear erase can be applied simultaneously to erase the memory cell. The tunnel dielectric having the S〇n〇n〇S structure in the § memory cell provides a fast erase which can occur in about 1 〇 to 5 亳 亳 and in the self-converging channel erase rate. In one example, the sector erase operation condition can be similar to the RESET process. For example, referring to Figure Ma, VG = about -15V is applied simultaneously at WL and all BLs are left floating up to sector erase. And p well can be kept grounded. Alternatively, referring to Figure 14b, application of about -8V to WL and about to the well can also achieve sector erasure. In some examples, a full sector erase operation can be implemented in 100 milliseconds or less without any cells that are erased or difficult to erase. The above component design can facilitate a channel erase that provides excellent self-converging properties. λ Figure 17 shows the erase feature in the example using a SONONOS component. An example of a SONONOS component can be 〇ι/Ν1/02/Ν2/〇3 = β degrees, respectively, about 15/20/18/70/90 angstroms, with one Ν + polylithic idle pole and 1 thermal conversion The top oxide is 〇3. The erase rate for various gate voltages has been shown. A more gate voltage results in a faster erase rate. ν, However, the convergence Vt is also higher. This is more active due to the gate implant at the higher gate. In order to reduce the gate injection, a high work function ρ+ polysilicon gate or other metal gate can be used as the gate material to reduce the gate injection electrons. Drainage Figure 18 shows the durability of the SONONOS component for a virtual grounded array architecture. In some cases the durability is excellent. The enthalpy conditions for Bitq are Vg/Vd=8.5/4.4V, 0.1 microseconds for use, 2 series 681939-27U3 28 1309875

Vg/Vs-8.5/4.6V, 0] microseconds. FN 50 亳 以 以 以 以 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹 抹Because the FN erase is self-convergent and uniform. Example Li: Units that are or are not erased usually do not appear. In some erase verification or excellent durability f ’ even if not stylized,

The characteristic circle Γ2Γ: f shows the corresponding 1^ 曲 of the 1-V during the p/e cycle in an example, the degree L is in the linear scale (Fig. 19b) and the P/E cycle is followed by I. It depends on the fact that the S_N〇S family has been guided many times ((4) to degenerate, so that the limit value is oscillated.) and across the 0 Λ SON〇N〇s thermoelectric hole, and the main entry is more excellent for the long-term nature. The reason - can be unused, #11榀. In addition, an ultrathin oxide disclosed above may have better stress relief properties than a thick tunnel emulsion. , 20 1 member is not a chisel stylized scheme in an example. The stylized yak-alternative method uses the CHISEL·stylization scheme, which uses a negative base and bias-enhanced impact ionization to increase the heat carrier efficiency. The stylized current should also be reduced due to body volume. Typical conditions are shown in this figure, where the base system is applied with a negative motor (-2V) and the junction voltage is reduced to about 3'5V. For conventional NROM components and techniques, CHISEL·stylization is not applicable because it may inject more electrons near the center of the channel. And the thermal hole erase is inefficient for removing the electronic system near the center of the channel in the conventional NROM device. Figures 21a and 21b show the design of a JTOX virtual ground array in an example. The JT〇x virtual ground array provides an alternative implementation of the 681939-27U3 29 1309875 SONONOS memory unit in a memory array. In one example, the difference between the jT〇x structure and the virtual ground array is that the components in the JT〇x structure are isolated by the STI method. A typical layout example is shown in Figure 21a. Figure 2b shows a corresponding equivalent circuit that is identical to a virtual ground array.

As disclosed above, the memory cell structure in accordance with the present invention is suitable for both NOR and NAND type flash memories. Additional examples of memory programming designs and methods of operation thereof will be described below. Without departing from the scope of the present invention by the specific structure described below, various operational methods of the memory array in accordance with the present invention will be described hereinafter for an exemplary NAND architecture. As described above, an n-channel SONONOS memory element having a 〇N〇 tunnel dielectric can be used for the _memory element. An example of a NAND array architecture. Figure 2 and (10) are cross-sectional views of the exemplary memory technicians from two different directions. In some examples, the memory array can be operated by +FN stylization, self (four) reset/erase, and read methods. In addition, circuit operation methods may be included in some examples to avoid stylized interference. In addition to the early block gate structure, the gods are set again. In addition to f, an array of spm-gates may be used, such as an array of coffee cells using S〇N〇N〇S elements between the two poles adjacent to the source/no-polar regions. In this example, the split gate design can be adjusted to reduce the number of fingers, and these components can be designed to obtain the coupling effect between the dynamic gates, or - "second"; sinfulness to reduce or remove the ocean #达达] ° As revealed above, —SONON〇s, the hidden parts can be used for excellent self-receiving erase and vt distribution control. Moreover, close, assist fan & erase the twist to make a compact erase state The distribution can be beneficial to multiple 681939-27U3 30 1309875 quasi-applications (MLC). By using some designs as memory array structures, the effective channel length (Leff) can be expanded to reduce or eliminate short channel effects. These examples do not use a diffusion junction to avoid the challenge of providing shallow junctions or using pocket implants during memory cell processing. Figure 1 shows an example of a memory element with a SONONOS design. Examples of different layers of material and their thickness. In some examples, a P+ polysilicon gate can be used to provide a lower saturation reset/erase voltage Vt, which can be achieved by reducing gate implants. Figures 22a and 22b show a memory. An example of a volume array, such as having The S〇n〇n〇S-NAND array of memory cells according to the specific embodiment of Table 1 has a diffusion junction. In an example, the separated components can be isolated from each other by various isolation techniques, such as By isolation technique using shallow trench isolation (STI) or insulator on-board (SOI). Referring to Figure 22a, a memory array can include multiple bit lines (e.g., BL1 and BL2), and multiple word lines ( In addition, the array may include a source line transistor (or source line select transistor or SLT) and a bit line transistor (or bit line select transistor or BLT). For example, the memory cells in the array can be designed using SONONOS, and the SLT and BLT can include n-type MOSFETs (NMOSFET). Figure 22b shows an exemplary layout of a memory array such as a NAND array. Referring to Fig. 22b, the Lg is the channel length of the memory cell, and the Ls is the space between the separation lines of the memory element. In addition, the w is the channel of the memory cell, and the Ws is separated by the bit line or the source/no pole. The isolation area of the interval is 681939-27U3 31 1309875 degrees ' it is in one An example may be the STI width. Referring again to Figures 22a and 22b, the memory elements may be connected in series and form a NAND array. For example, a string of memory elements may include 16 or a magic memory element 'providing a number of strings of 16 or 32. BLT may be used And SLT as a selection transistor to control the corresponding SfAND string. In one example, the gate dielectric for BLT 'and SLT can be a hafnium oxide layer that does not include a tantalum nitride trapping layer. In some examples (although not necessarily required in all cases) φ may avoid possible vt shifts of BLT and SLT during memory array operation. Another option, BLT and SLT, can be used as a gate dielectric layer by combining a plurality of layers of ONONO layers. In some examples, the gate voltage applied to the BLT and SLT may be less than 10V, which may result in less gate interference. If the gates of BLT and SLT; the I electrical layer can be charged or trapped, an additional _Vg erase can be applied to the gate of the BLT or SLT to discharge its gate dielectric. Referring again to the figures, each BLT can be coupled to a bit line (BL). In a φ paradigm, BL can be a metal line having the same or approximately the same pitch as the STI. Similarly, each SLT is connected to a source line (SL). The source line is parallel to the WL and is connected to a sense amplifier for read sensing. The source line can be a metal (e.g., tungsten), or a polysilicon line, or a diffused N+ doped line.

• Figure 23a shows a cross-sectional view of an exemplary memory array (such as SONONOS-NAND - array of memory) along the length of the channel. In general, Lg & Ls is approximately equal to F, which generally represents the critical dimensions of a component (or node). The critical dimensions can vary with the technology used for manufacturing. For example, F = 5Q nm represents the use of a 50 nm node. Figure 23b shows a cross-sectional view of an exemplary memory array (e.g., 681939-27U3 32 1309875 S〇N〇N〇S_NAND memory array (1) along the channel width 0 direction. Referring to Figure 23b, the channel width direction spacing is approximately equal to or slightly larger than The spacing in the length direction of the channel. Therefore, the 4F2/cell of a memory unit. In the case of manufacturing a memory array (such as an array of images), the over-travel may be related to using only two main masks or lithography buttons. Process, one for polycrystalline stone (word line) and the other for STI (bit line). Conversely, the fabrication of 臓d-type galvanic gate components may require at least two polycrystalline processing And another polycrystalline stone processing. Therefore, the structure and process of the disclosed components can be simpler than the NAND type floating gate memory. Referring to Figure 23a, in an example, between the word lines (WL) The space (Ls) can be formed with a shallow junction (such as the shallow junction of the N+ doped region), which can serve as the source or drain region of the memory element. As shown in Figure 23a, the 彳 performs additional implantation and/or diffusion. Process (eg, beveled pocket implant) to provide proximity to one or more One or more "pocket" areas or pocket extensions of the junction of the junction areas. In some examples, this configuration provides better component characteristics. The sti is used to isolate the isolated memory elements. In the example, the ditch depth of the sti _ zone can be greater than the vacant width of the p well, especially when the junction bias used is raised higher. For example, the junction bias can be as high as 7V for stylized forbidden bits. Meta-line (bit line not selected during stylization). In an example, the depth of the STI region can be in the range of 200 to 400 nm. After the memory array is fabricated, other memory arrays can be used. The reset operation is performed before the operation to make the Vt distribution compact. Figure 24a shows an example of this operation. In an example, before other operations start, VG = about 681939-27U3 33 1309875 _7V and P well = +8V can be applied first. To reset the array (the voltage drop of the VG and P wells can be divided into the gate voltage into each of the WL and p wells). During RESET, bl can float, or rise to the same voltage as the p-well, as shown in Figure 24b. The reset operation provides excellent self-convergence properties. In one example, even— Begin charging the SONONOS components to various Vt's. This reset operation can make it "compact" to the reset/erase state. In one example, the reset time is about 1 millisecond. In this example, the memory array An η-channel SONONOS component with Å can be used with an N+ polysilicon gate of Lg/W=0.22/0.16 μm. 'Generally, conventional floating gate components are not available. Self-convergence erase. Conversely, SONONOS components can be operated with a convergence reset/erase method. In some cases, the Vt conversion is often due to mosquito process problems (such as process non-induced or plasma charging effects). This operation can become very important in a fairly wide range. An exemplary self-convergence "reset" can help to make the initial Vt distribution of the memory element compact or narrow.

In the example of stylized operation, the WL of the selected device can be applied with a high voltage (for example, a voltage of about +16V to +20V), and injected into the channel side. Other PASS Gates (Other Unselected WLs) 2 Insects G7 J Plus is turned on to induce an inversion layer in a NAND string. Stylized in law. In the example, the parallel stylized method of 'T is a low-powered sheep, and the other is 4, and the fourth is like a 4Κ byte unit, which can be programmed to make the program The current consumption can be controlled within the lmA ^ to more than the brain version C, in the other muscle towel material interference, - higher fan, in order to avoid application to other BL, so that the inversion layer potential ^ 4 (such as about 7V voltage) It can be higher to suppress the voltage drop in the unselected 681939-27U3 1309875 BL (eg, cell B in Figure 25). In the example of a read operation, the selected WL can be boosted to a voltage between an erased state level (EV) and a stylized state level (PV). The other WL can be used as a "PASS gate" so that its gate voltage can be raised to a voltage higher than pv. In some examples, the erase operation can be similar to the reset operation described above, which can allow self-convergence to the same or similar reset Vt. Figure 25 shows an example of operating an array of memory. Stylization can include channel +FN electron injection into the SON〇N〇S nitride trapping layer. Some examples may include applying Vg = about +18V to selected WLN-1, and applying vg = about +10V to other WLs and BLT〇SLT can be turned off to avoid channel hot electron injection in cell B. In this example, because all of the transistors in the NAND string are turned on, the inverted layer passes through the strings. Further, since the inverted layer in the Bl 1 grounding 'BL1 has a zero potential. On the other hand, the other bl is raised to a high potential (e.g., a voltage of about +7 V) so that the potential of the inversion layer of the other BL is higher. In particular, for cell A, which is a selected stylized cell, the voltage drop is about +18V, resulting in a +FN implant. And Vt can be promoted to pv. As for cell B, the voltage drop is +11V, resulting in much less +FN implant because the fn implant is sensitive to Vg. As for cell C, only +10V is applied, resulting in no or negligible +FN injection. In some examples, the stylization operation is not limited to the techniques described. In other words, other suitable stylization suppression techniques can be applied. Figures 24a, 26 and 27 further show some examples of array operation and show some examples of durability and retention properties. As an example, component degradation after some cycles of 681939-27U3 35 1309875 can be kept to a minimum. Figure 24a shows an exemplary erase operation that can be similar to the reset operation. In one example, the erase is performed by a sector or block. As noted above, the memory elements can have good self-convergent erase properties. In some examples, erasing saturation Vt may depend on Vg. For example, a higher Vg can result in a higher saturation Vt. As shown in Fig. 26, the convergence time can be about 10 to 100 milliseconds. Figure 27 shows an example of a read operation. In one example, the reading can be performed by applying a gate voltage between a erased state Vt (EV) and a stylized state Vt (PV). For example, the gate voltage can be about 5V. On the other hand, other WL and BLT and SLT systems are applied with a higher gate voltage (e.g., about +9V) to turn on all other memory cells. In an example, if the Vt of cell A is higher than 5V, the read current may be extremely small (<0.1uA). If the Vt of cell A is lower than 5V, the read current may be higher (>0.1uA). As a result, the state of the memory (i.e., the stored information) can be identified. In some examples, the pass gate voltage for other WLs should be higher than the high Vt state or the stylized state Vt, but not too high to trigger gate interference. In one example, the PASS voltage is in the range of about 7 to 10V. The applied voltage at BL can be about IV. Although larger read voltages can induce more current, read disturb may become more apparent in some examples. In some examples, the sense amplifier can be placed on the source line (source sense) or on a bit line (drain sense). Some examples of NAND strings can have 8, 16, or 32 memory elements per string. A larger NAND string saves additional overhead and increases array efficiency. However, in some examples, the read current may be small and the interference may become more noticeable 681939-27U3 36 1309875. Therefore, the appropriate number of NAND strings should be selected based on various design, fabrication, and operational factors. Figure 28 shows the cycle durability of certain exemplary components. Referring to the figure, a p/E cycle with +FN stylization and -FN erasing can be performed and the results show good endurance characteristics. In this example, the erase condition is Vg = about _16v for milliseconds. In some examples, only a single erase is required and verification of the state is not necessary. The memory Vt window is good without degradation. Figures 29a and 29b show IV features of exemplary memory elements using different scales. In particular, the small wobble degradation of the display elements in Figure 29a, and Figure 29b shows the small transconductance degradation of the elements. Figure 3A shows the retention characteristics of an exemplary s〇n〇n〇s element. Referring to Figure 30, good retention is provided by having a charge loss of less than 1 〇〇mV for the component after the ιοκ cycle and after 200 hours of leaving. Figure 30 also shows the acceptable charge loss at high temperatures. In some examples, a 'split gate design (e.g., a split gate SONONOS-NAND design) can be used to achieve a further step-by-step scaling of the memory array. Figure 31 shows an example of using this design. Referring to Fig. 31, the space (Ls) between two adjacent memory elements between the word lines or sharing the same bit line can be reduced. In one example, Ls can be reduced to about 3 nanometers or less. As in the example, a memory element using a split gate design may only have a source region or a drain region along the same bit line. In other words, for some memory parts, the split gate SONONOS-NAND array can be used without the diffusion region or the ❹ (❹ doped region). In the example, the design also reduces or eliminates the need for shallow joints and adjacent "pockets", which in some examples may involve more complex processes. In addition, in some sample cases, the design is less 681939-27U3 37 1309875 due to the short channel effect because the channel length has been increased, such as increasing to Lg = 2F-Ls in an example. Figure 32 shows an exemplary process for a memory array using a split gate design. This schematic is merely an exemplary example, and the memory array can be designed and fabricated in a variety of different ways. Referring to Fig. 32, after forming a multilayer material for providing a memory element, the layers may be patterned using a niobium oxide structure as a hard mask formed on the layers. For example, the yttrium oxide regions can be defined by lithography and etching processes. In one example, the pattern used to define the initial yttrium oxide region may have a width of about F and a space of about F of the yttrium oxide region, resulting in a distance of about 2F. After patterning the initial yttrium oxide region, a hafnium oxide spacer can then be formed to expand the respective hafnium oxide regions around the patterned regions and narrow the spacing thereof. Referring again to Figure 32, after forming the hafnium oxide region, it is used as a hard mask to define or pattern its underlying layer to provide one or more memory elements, such as a plurality of NAND strings. In addition, an insulating material such as hafnium oxide can be used to fill the space between adjacent memory elements, such as the space Ls shown in FIG. In one example, the space Ls between adjacent memory elements along the same bit line can range from about 15 nanometers to about 30 nanometers. As described above, in this example, the effective channel length can be expanded to 2F-LS. In one example, if F is about 30 nm and Ls is about 15 nm, then Leff is about 45 nm. For the operation of these exemplary memory elements, the gate voltage can be reduced to less than 15V. In addition, the polysilicon voltage drop between the word lines can be designed to be no greater than 7V to avoid spacer collapse in the Ls space. In an example, this can be achieved by having an electric field of less than 5 MV/cm between adjacent word lines. 681939-27U3 38 1309875 Leff for the diffusion junction of a conventional NAND floating gate element is about half of its gate length. Conversely, in one example, if F is about 5 nanometers and Leff is about 3 nanometers, Leff is the recommended design (split gate NAND) of about 80 nanometers. Longer Leffs provide better component characteristics by reducing or eliminating the effects of short channel effects. The NAND design of the split gate as described above can further reduce the space (Ls) between adjacent memory cells of the same bit line. Conversely, the traditional nand type = the gate, the components may not provide a small pitch, because the floating gates are lightly combined = the cannon loses the memory window. When the coupling capacitance between adjacent floating gates is ', the e-gate _ is the interference between adjacent memory cells (the work of floating closed-pole 2, 'so that the coupling capacitance between adjacent floating gates is extremely high So that the shell ^ interferes with A). As noted above, the design eliminates the need for manufacturing - some of the diffusion junctions and can be directly connected if all of the word lines are turned on. Therefore, this design simplifies the process of memory components. The description includes structured design, array design and memory components, which can provide an array size that meets the requirements, and is excellent and reliable in any combination of scales. The above-mentioned examples can also be applied to the size of the flash-small (four)^small non-volatile (four) memory, such as flash memory that is faster than the data application. Some examples provide sc)nqnqs components that are t1 money 2^ hole tunneling erased. A second case can also provide a memory element to over-improve (4) _~ and reduce the difficulty of erasing or showing the question "° the same place" can provide good

Small degradation after the cycle; 3僖*卞 proud of components such as in P/E—not II. Array of own /, with no bits or units of 疋. Furthermore, 681939-27U3 1309875

Some examples can be based on the split gate NAN feature, which can be used to name a good short channel component, and provide a better margin for the preferred body of the present invention during operation of the TCfeTC device. And the purpose of the description. It is not intended to reveal the precise form. :SSt: omission or desire to limit the invention to the disclosed embodiment. The person should be able to understand the specifics of the above (4) money in the wide-ranging concept. Therefore, the cover belongs to the embodiment of the request, and is embossed. 7 疋 之 本 本 本 本 本 本 本 本 本 本 本 本 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前 前For the purpose of the disclosure, each embodiment is not limited to the specific embodiment. However, it should be understood that the present invention resides in various drawings: * means and apparatus. The memory ^ ^ and ^ are respectively according to an embodiment of the present invention, the N-channel is broken and the P-channel memory unit according to the present invention - the specific embodiment is not intended; A schematic diagram of the threshold voltage (charge trapping capacity) of the associated dielectric structure of the embodiment under the method of the present invention; the SONONOS memory limit voltage of the embodiment according to the present invention is during the erasing period Illustrated with time; 〇 Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 An energy band diagram of a germanium tunnel dielectric structure in accordance with various embodiments of the present invention; FIG. 6 is a graphical representation of hole tunneling current versus electric field strength for three different tunnel dielectric structures; FIG. 7a is a diagram in accordance with the present invention A graphical representation of the threshold voltage of a memory cell of a particular embodiment over time during the erasing of various types of stylization; φ Figure 7b is a memory cell having a platinum gate in accordance with an embodiment of the present invention. In addition to changing over time Figure 7c and 7d are diagrams showing the capacitance versus voltage of the memory cell of Figure 7b; Figure 8 is a diagram of a plurality of stylized memory cells in various operating conditions in accordance with an embodiment of the present invention. FIG. 9 is a diagram showing a current-voltage (iv) relationship of a memory cell after a cycle of φ and ίο3 according to an embodiment of the present invention; FIG. 10 is based on the present invention. A diagram of a threshold voltage of a memory unit in a set of stylization and erasing conditions during a number of stylization/erasing cycles; and FIG. 11 is a memory unit in accordance with an embodiment of the present invention. FIG. 12a and 12b are respectively an equivalent circuit diagram and a layout diagram of a virtual ground array of a memory unit according to an embodiment of the present invention; FIG. 13 is a diagram showing a change of a threshold voltage with time under a VG plus-speed hold test; FIG. 12b is a cross-sectional view of the virtual ground array of the memory 681939-27U3 41 1309875 unit taken along line 12B-12B in accordance with an embodiment of the present invention; FIGS. Ma and Mb are included in accordance with the present invention - An equivalent circuit diagram of a memory array of memory cells of the embodiment, and describing suitable reset/erase voltages for two embodiments in accordance with the operation of the present invention; Figures 15a and 15b are included in accordance with an embodiment of the present invention. An equivalent circuit diagram of a memory array of memory early, which describes one of the methods according to the present invention; „ a diagram (10) and 16b includes an equivalent circuit diagram of an early memory memory array according to the present invention. The description is based on the method of the bit; the method of the present invention is based on the threshold voltage of the memory unit according to the present invention in the various spears of the present invention; the program I / this ^ - specific The icon of the new example is shown in a number of threshold voltages in the process of Figure 19a = %; in various m 1%, according to a memory of a specific embodiment of the present invention, the voltage of the lower extremity 1 stream county logarithmic scale and array Ξ, etc. including a memory unit according to an embodiment of the present invention. A road diagram describing a fabric Z 21b of a square array of one-dimensional elements according to the present invention is in accordance with the present invention. - specific implementation Virtual ground, local map and equivalent circuit diagram; set I ΝΛ = 22b are respectively memory W AND_ material efficiency and layout according to an embodiment of the present invention; 681939-27U3 42 1309875 single - Figure 23a and 23b A cross-sectional view taken along lines 22A_22A and 22B_22b shown in FIG. 22b, respectively, according to an embodiment of the present invention; 24a is a ρ-effect thunder-fixation diagram according to a preferred embodiment of the present invention. It describes a method of operation in accordance with the present invention; a pair of NAND arrays of a particular embodiment is shown in Figure 24b during a reset operation in accordance with an embodiment of the present invention.

FIG. 25 is a circuit diagram of an operational method in accordance with an embodiment of the present invention; FIG. 26 is a memory diagram in accordance with an embodiment of the present invention; FIG. 26 is a circuit diagram of a method for operating a memory unit having different initial threshold voltages; FIG. 27 is an equivalent circuit diagram depicting an operation method in accordance with an embodiment of the present invention; FIG. 28 is a memory unit in accordance with an embodiment of the present invention; FIG. Illustration of threshold voltages during a number of stylization and erasing cycles in a set of stylization and erasing cycles; Figures 29a and 29b are memory cells in accordance with the present invention - in various gates The current at the voltage at the drain is at a number of three different cycles - in accordance with the logarithmic scale and the linear scale, respectively; the threshold voltage of the memory cell according to an embodiment of the invention is at three different temperatures and cycles Figure 31 is a cross-sectional view of a NAND array character 681939-27U3 43 1309875 line in accordance with an embodiment of the present invention; 32 a schematic sectional view of line art NAND array of word lines is formed based on a specific embodiment of the present invention. [Main component symbol description] 100 η channel memory unit 101 Ρ type substrate 102 Ν type doped region 104 η type doped region 106 channel region 120 tunnel dielectric structure 122 underlying thin oxide layer 124 small hole tunneling barrier height nitridation Thin oxide layer 130 above layer 126 charge trapping/charge storage layer 140 insulating layer 150 gate 200 ρ channel memory unit 201 n-type substrate 202 Ρ-type doping region 204 换-type replacement region 206 channel region 220 channel dielectric structure 222 Lower thin oxide layer 224 Small hole tunneling barrier High nitride layer 681939-27U3 44 1309875

226 Upper thin oxide layer 230 Charge trapping/charge storage layer 240 Insulation layer 250 Gate 681939-27U3 45

Claims (1)

鬌lJ〇987s7 'Application for patent garden: ., a memory unit, which comprises: - a semiconductor substrate, its ~ 汲桎 region, · a source region separated by a channel region - tunnel dielectric structure, hair / electricity The structure includes a plurality of layers disposed on the channel region, the tunnel hole passing through the barrier height, and the dielectric structure comprises a storage layer having a -7 load, which is: an insulating layer, The ruin is placed on the dielectric structure of the tunnel; - the gate electrode is held on (1) the charge storage layer; and the electrode contains a placed on the insulating bank j., = - the work function value is greater than the Ν + ^ layer Where 'the gate is ... wherein the material with a plurality of reeds, bismuth = 7 storage structure, = = structure: the charge passes through the intervening dielectric structure of the structural layer and traps the second electricity;:: as requested The item is as requested: Second, its "closed electrode contains the name. The second dielectric layer dielectric structure Mi is as thick as the thickness of the request. Brother-虱化矽层,一在嗲,"Electrical structure consists of a layer, and the first stone layer on the IP layer, the first-&虱 矽==1 Memory unit, i should be: layer. The chaotic master, the eight shouts, and the Hf〇2, the composition of the family chose the storage layer to include at least the read element from the request item i, the "insulation layer p ' ' ' II - I l_ I _ _ ~ ip year / / month phase repair (more) is replacing Mj ^ - one 2. 4. 5. 681939-27U3 46 *1309875 8. For example. The memory unit of the month 1 is the negligible trapping rate. A battery 5 array of memories, comprising a plurality of such as request elements. ' Structure has a memory list of 1. 9. 10. 12. 12. 13, = memory of request 8 _, the number of its jobs is at least two memory cells are separated by at least one of the shallow ditch Weiss _ and - the insulator is cut as in the memory array of claim 8 wherein the memory array comprises at least: a word line, at least two bit lines, and at least _ source lines. For example, the memory array of item 10, wherein the memory array includes at least a 选择 line selection transistor ' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The memory array of claim 10, wherein the memory array comprises a source-selective transistor that is coupled to the corresponding source line. The memory array of claim 10, wherein the substrate comprises at least one pair of shallow junctions for the memory element. 681939-27U3 47