TWI307965B - Multi-level non-volatile memory and manufacturing method thereof - Google Patents

Description

I3079^〇2 19830twf.doc/e IX. Description of the Invention: [Technical Field of the Invention] A semiconductor element, and particularly relates to "and its manufacturing method and operation method. The present invention relates to a multi-level non-volatile memory. [Prior Art] The non-volatile recording (four) component has the advantages of being in, reading, and technically reducing the loss of the 仃人仃仃贝#, so it has become a = The data of the person will not disappear after the power is turned off - the memory component. 1 Typical non-volatile memory components widely used in brain and electronic equipment are push gates (F1〇ating Gate) and control clamps = poles are directly set on the _, 浮 ) = = = = = = The layers are separated, and the floating _ is separated from the substrate by 0xlde. That is to say, the so-called stacked gate flash memory ^ fe 体 body in the wipe _ ' _ degree 镰 silk is too serious, resulting in the problem of ==. Therefore, the gate gate and the floating gate sidewall are controlled, and the s(select gate) is selected to form a split gate structure. Generally, σ 'sees the non-volatile which is commonly used in the industry. The memory is, for example, an inverse or gate (Ν〇·_ structure. In the inverse or gate of the known (in the ν-type array, every two memory cells share - a bit_connect_) and share a source line. Therefore, Each memory cell occupies half the width of the contact ^ and half of the source line. Since each memory cell is directly connected by a bit line, in the inverse or gate (N〇R) type array, the memory cell Any I30796$7〇2 19830twf.d〇c/e can be taken and written, and since the resistance of the series is small, it is recorded during the operation. The flow is large, the reading speed is faster / the heart level ± NC) R _ the memory in the volatile memory as the multi-distribution range 2 is used to determine the starting voltage of each data state. The calendar type non-volatile memory recognition step ^ requires a multi-filing step and stylization to ensure that the 'money stylized memory is freshly in the set starting voltage distribution range, which will take a long time. [Summary of the Invention] In view of the above, the object of the present invention is to provide a memory and a method for manufacturing the same, and to improve the device. A further object of the present invention is to provide a multi-stage non-volatile memory and method. And the operation method, the process is simple, and the process margin can be increased. Another object of the present invention is to provide a multi-stage non-volatile memory and, manufacturing method and operation method, which can shorten the stylized time of the memory cell and speed up The invention provides a fresh forward memory, comprising a first memory cell disposed on the substrate. The first memory cell includes a control gate, a charge storage layer, a doped region, a select gate and a gate is provided on the substrate, and a charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate on the first side of the control gate. The selection gate is disposed on the control gate The first side _ wall 'and the base between the control gate and the doping is 1307965702 19830twf.doc / e =. Auxiliary miscellaneous _ 帛 帛 帛 触 触 施加 施加 ' ' ' 辅助 辅助 辅助 辅助 辅助Preferably, the bottom layer is disposed between the charge storage layer and the substrate. Ϊ - "Electrical layer is disposed in the charge storage layer, and the first layer is placed on the auxiliary gate and the control gate; The dielectric layer is disposed between the pole and the substrate. The fourth layer (10) is between the 3/ and the auxiliary gate charge storage layer, and the upper gate is: the control gate, the body two, and the second two: the multi-order non-description Volatile memory spacers. Between the electrical layer and the control gate, the charge storage layer is formed with a _ wall formed between the multi-level non-volatile 逑t逑 fourth dielectric layer and the control gate according to the preferred embodiment of the present invention. ... body, the implementation of the description of the _ volatile memory side of the "electric layer material includes yttrium oxide. The material according to the touch implementation of the present invention = the material of the second dielectric layer comprises oxidized oxide/nitriding: dihex. The second order of the hidden body =, the k-good embodiment of the seventh embodiment is the second; the tantalum layer and the fourth dielectric layer are high temperature thermal oxide layers. The thickness of the multi-stage non-swollen memory Sr丨 electric layer and the fourth dielectric layer described in the preferred embodiment of the present invention are between the purchase and the hometown according to the present invention. Stepped facial memory 7 1307965 702 19830twf.doc / e body, including the second memory cell. The second memory cell has the same structure as the first memory cell, and the second memory cell is disposed adjacent to the first memory cell in a mirror symmetrical square. And in combination with the multi-level non-volatile memory according to the preferred embodiment of the present invention, the second memory cell is disposed on the first side of the first memory cell, and the first memory cell shares the doped region. According to a multi-stage non-volatile grammar of the preferred embodiment of the present invention, the second memory cell is disposed on a second side of the first memory cell, and the first memory cell shares an auxiliary electrode. /, a multi-order non-volatile record according to a preferred embodiment of the invention, further comprising a cap layer. This cap layer is placed on the control gate. μ In accordance with a multi-stage non-volatile record according to a preferred embodiment of the present invention, the charge storage layer portion protrudes horizontally from the control electrode, and the position adjacent to the selection gate has a rotation angle. The present invention provides a multi-level non-volatile memory including a plurality of bit lines, a plurality of control gate lines, a plurality of strips, and a plurality of f-crystals. Most of the memories are two: The upper 5 is again placed in a row/column array. Each memory cell includes a control gate, an electric ‘its:: a smart area, a selection gate, and an auxiliary gate. The control gate is placed between the % load reservoir & placed between the control side and the substrate. Doped in the substrate on the first side of the interpole. The selected interpole is disposed on the side wall of: :: on the side of the side, and is located between the control idler and the doped region, I = two, the gate is disposed on the sidewall of the second side of the control gate, wherein the gate is The read cells are contiguously arranged in a mirror symmetrical manner. Most of the strips 8 Ό 2 19830twf.doc/e are lined up in parallel in the row direction, connecting the swap cells of the same row of memory cells. A plurality of control gate lines are arranged in parallel in the column direction to connect the control gates of the memory cells of the same two columns. A plurality of strip select gate lines are arranged in parallel in the column direction to connect the select gates of the memory cells of the same column. Most of the auxiliary closed = lines are parallel in the column direction, connecting the auxiliary poles of the same-like memory cells. The transistor is divided into a sub-base under the auxiliary gate line. According to the invention, the first dielectric layer, the second dielectric layer and the third dielectric layer are electrically layered. The first dielectric layer is disposed between the charge storage layer and the substrate. The first: " electrical layer is set between the charge storage layer and the control side pole two =:: rrr, charge fine; = electricity price: ί Γ layer is set between the selection of the interpole and the control between the pole, the electrical storage layer, and Between the surface _ and the substrate. Recall the gap wall. The body I, the control electrode, and the electrical storage layer are formed with a body 'two: four: memory honey, wherein the third dielectric layer and:: '02 19830twf.doc / e in accordance with a preferred embodiment of the present invention In the multi-level non-volatile memory, the charge storage layer portion protrudes horizontally from the control horn, and the position adjacent to the selection gate has a rotation angle. The multi-level non-volatile memory according to the preferred embodiment of the present invention' The multi-level non-volatile memory according to the preferred embodiment of the present invention, the adjacent two memory cells mirror-symmetrical to each other share an auxiliary gate. In the multi-level non-volatile memory of the present invention, adjacent two memory cells are arranged, for example, in a mirror symmetrical manner, that is, adjacent two memory cells share an auxiliary gate or doped region. Therefore, the multi-stage non-volatile memory of the present invention can not only simplify the manufacturing process, reduce the manufacturing cost, but also improve the integration of components. Further, when a voltage is applied to the auxiliary gate to open the channel under the auxiliary gate and an inversion layer is formed, a voltage is applied to the inversion layer so that the inversion layer under the auxiliary gate can be in a precharged state. In the non-volatile memory of the present invention, by means of self-accelerating charge injection (ch^nei ^lfboosting), the use of the source side injection effect to perform memory cells can increase the programming speed. Moreover, when the non-volatile body is used as a multi-order memory cell, the starting voltage of the memory cell can be accurately controlled during the stylization operation within the set range. The present invention provides a method of manufacturing a multi-stage non-volatile memory, 勹 step. First, a time-penetrating layer is formed on the substrate, and the storage layer is formed, and at least two stacked layers are formed on the charge storage layer. The stacked layers sequentially include a dielectric layer, a control layer, and a layer. Next, 130796^702 19830twf.doc/e 130796^702 19830twf.doc/e ft (4) the charge storage layer of the stacked layer to form the first groove. The side wall of the π-stack® layer is the first and the third, and the tears are made. The charge storage layer on the outside of the second ceremony. Jude, you and * L... into a dielectric layer. In the second stacking of the bank gate;; the second two sides, the sidewalls on the outer side of the base are formed separately ~ ~ lamination stack and doping::;: do not form a miscellaneous area, and select the gate system of the second wide In a preferred embodiment of the invention, the age-old electrical material desuperheating wave is made up of a thickness of between 100 angstroms and fine angstroms. Method of Making Non-volatile memory according to the embodiment, the outer side wall is divided into the following greens. First, the conductor layer is formed in the > layer. The conductor material layer fills the first trench, the soil-return, and is made. : removing part of the conductor material layer until the top cover layer is exposed; a stack of auxiliary gates is formed between the stacks of layers, and the second stacking channel is then 'into the stack', then the multi-level non-volatile memory曰体^方法' The material of the above-mentioned dielectric layer includes oxidized stone. The method of forming the fused dielectric layer on the multi-stage non-volatile memory core method described in the embodiment includes a thermal oxidation method. The invention relates to a multi-stage non-volatile memory according to a preferred embodiment of the present invention: a multi-stage non-volatile memory according to a preferred embodiment of the invention, a method for preparing the same, and the above-mentioned The material of the layer includes oxygen cut/nitridite eve/memory 11 130796^702 19830 twf.doc/e in the present invention is not a wave: Shi Xi. And the cost of the day, increase the process margin. Since the formed charge storage layer has a corner at the corner, the electric field is concentrated by selecting the angle between the poles of the pair f to increase the electron::out: the speed of the erase operation of the second electrode. The $仃 storage layer is pulled out to the selection gate; the method for operating a multi-level non-volatile memory is suitable for the gate-side substrate of the gate. The selection gate is disposed on the sidewall of the control gate 1 and is located on the substrate between the control impurity and the doping region, and the pole is disposed on the sidewall of the second side of the control gate, and the method includes performing the patterning In operation, a first voltage is applied to the auxiliary gate in advance to form an inversion layer in the substrate under the auxiliary gate, and a second electrification is applied to the inversion layer. Applying a third voltage to the control side, applying a fourth voltage to the select gate, and applying a fifth voltage to the drain region, wherein the first voltage is greater than the start voltage of the auxiliary gate, and the third voltage is greater than the first voltage The fourth voltage is greater than or equal to the starting voltage of the selected gate, and the third voltage is greater than the fifth voltage to program the memory cell with the source side injection effect. According to a preferred embodiment of the preferred embodiment of the present invention, the first voltage is about 8 volts; the second voltage is 5 volts 12 13079657 02 19830 twf.doc/e ΐΐ volts or so as voltage It is about volts; the voltage of the fifth is about 0 volts. Operation, = good __ multi-level non-volatile memory, second power plant: for the purpose of the 仃 erase operation

It is pulled out and removed, and the first thunder pressure plate is mounted on the left side by the selection gate. In the eighth, the voltage difference between the voltage and the substrate causes the FN to be the second-order non-volatile memory of the preferred embodiment, and the sixth voltage is about u to 15 volts. The multi-stage non-volatile memory according to the preferred embodiment of the present invention is intended to apply a nine-threshold voltage to the auxiliary gate during the advance % pick operation, and apply the first voltage to the gate. The tenth voltage is applied to the embossed area to read the memory cell, and the ninth power 1 is greater than the starting voltage of the selected gate. The eighth voltage of the non-volatile memory of the non-volatile memory described in the preferred embodiment of the invention is about 4 volts, and the ninth electric dust is Vcc (power supply voltage), The ten dragon is i 5 volts right 0 The present invention provides a method for operating multi-level non-volatile memory, which is suitable for most memory memory cell arrays. Each memory cell includes a '1 pole, a charge storage layer, a doped region, a selective pole, and an auxiliary pole. The control electrode is placed on the substrate. The charge storage layer is disposed on the control gate and the substrate. The doped region is disposed in the substrate on the first side of the control interpole. The sigh is placed on the side wall of the first side of the control gate and is located on the substrate between the control opening and the doped 13 '702 19830 twf.doc/e. The auxiliary pole is disposed on the side wall of the second side of the control paste, and the memory cells of the towel on the same line are adjacently arranged in a mirror-to-turn manner. Most of the bit lines are arranged in parallel in the row direction, connecting the cells of the same row (4). Most age paste lines are arranged in parallel in the fiscal direction. The control gates connected to the memory cells of i are arranged in parallel in the column direction, and the selection gates of the memory cells of the same column are connected. Most of the auxiliary brewing lines are arranged in parallel in the financial direction, connecting the auxiliary gates of the same-like memory cells; 13⁄4. The drain of the transistor is connected to the substrate under the auxiliary (5) gate line. The t method includes, when performing a stylization operation, applying a second voltage to the source of the transistor in advance to the voltage of the idle electrode of the transistor, and applying a second voltage to the auxiliary gate of the gate to the lower side of the auxiliary idle line. The base towel forms an inversion 曰' such that the inversion layer is turned on by a second voltage, and then the gates of the transistors are changed to be volts to close the channels of the transistors, so that the inversion layer is in a precharge State, then pull the auxiliary gate voltage to s volts left 'to coupling the voltage of the inversion layer to about 5 volts. Applying a fourth voltage to the selected inter-electrode line, applying a voltage to the selected gate line, applying a sixth voltage to the selected bit line, wherein the third voltage is a starting voltage of the auxiliary gate of the reed, The fourth voltage is greater than the third voltage, the fifth voltage is greater than or equal to the starting voltage of the selected gate, and the second voltage is greater than the sixth voltage to program the selected memory cell using the source side injection effect. According to a multi-stage non-volatile memory processing method according to a preferred embodiment of the present invention, the first voltage is Vcc (supply voltage); the second voltage is ^cc (supply voltage)-Vth (from the crystal) The starting voltage); the third voltage is (supply voltage), the fourth voltage is about 10 volts; the fifth voltage is 14 1307 〇 2 19830 twf.doc / e volts; the sixth voltage is about 0 volts. The multi-stage non-volatile memory of the preferred embodiment of the invention is included in the selection gate application = pull-out and removal, wherein the voltage tunneling effect of W and the substrate. The method of the multi-stage non-volatile memory described in the preferred embodiment of the invention is the left voltage of about 11 to 15 volts. The multi-stage non-volatile memory electrode i described in the preferred embodiment includes 'applying a voltage to the selected auxiliary gate line when performing a read operation, and applying a ninth voltage to the selected control side line, 33? Applying a tenth voltage to the _ line, applying a starting voltage to the selected bit line to renew the memory cell, the tenth voltage is greater than the selection of the gate, and the fourth embodiment of the preferred embodiment of the non-volatile memory operation In the 乍 method, the first person voltage is Vee (supply voltage), the ninth voltage is about t 4 , the tenth voltage is Vee (power supply voltage), and the tenth voltage is about 15. The multi-level non-volatile memory that can be used in the present invention The method of self-acceleration charge injection (self-bcK) Sting) uses the source-side injection effect to perform the weaving, and the auxiliary open-circuit channel is charged to the set voltage. Fast stylized memory cells. Moreover, using the selection gate to erase the memory cells, so that the electrons are removed by erasing the gates, can reduce the number of electrons crossing the phone, and improve the components 15 13079 02 1983 twf .doc/e reliability. In addition, charge storage Adjacent to the selection of the gate, the time is taken to "concentrate the electric field by the corners, and the speed of the erase operation of the electrons from the storage layer to the selection gate can be increased. To achieve the above and other objects, features and features of the present invention. The advantages can be more obvious and easy to use 'the following specific embodiment' and with the formula, the detailed description is as follows 0 [Embodiment]

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the structure of a non-volatile memory in accordance with an embodiment of the present invention. x to β Please refer to the multi-dimensional non-volatile memory proposed by the present invention, for example, by a plurality of memory cells Q2 and Q3 provided on the substrate 100. Each of the memory cells Qb, Q3, Q4 includes a tunneling dielectric layer 1, 2, a charge storage layer 104, a gate dielectric layer 1〇6, a control gate 1〇8, a cap layer Π0, a spacer 112a, 112b, doped region 114, select gate 116, auxiliary gate 118, and dielectric layers 120, 122. The inter-gate dielectric layer 〇6, the control gate 108, and the cap layer 11 〇 form a stacked layer 1U.

The control gate 108 is, for example, disposed on the substrate 1A. The material of the control gate 〇8 is, for example, a doped polycrystalline stone. The charge storage layer 104 is disposed, for example, between the control gate 1A8 and the substrate 100. The material of the charge storage layer 104 is, for example, a conductor material (e.g., a doped polysilicon) or a material capable of trapping charges therein, such as tantalum nitride, I oxidized cerium oxide, cerium oxide, titanate or oxidized. The inter-gate dielectric layer 106 is disposed, for example, between the control gate 108 and the charge storage layer 104. The material of the inter-gate dielectric layer 106 is, for example, hafnium oxide/nitride 16 19830 twf.doc/e 矽/yttria. The pass-through dielectric layer 102 is, for example, disposed on the substrate 100 just below the charge storage layer, and the material of the tunnel dielectric layer 102 is, for example, oxidized oxide. The doping region U4 is disposed in the substrate 1〇〇 on one side of the control gate 1〇8. The doping region 114 is, for example, a drain region. The selection gate 116 is disposed, for example, on a side wall of the control room 1 side, and is located on the substrate (10) between the control electrode and the doping region 114. The material of the gate 116 is selected, for example, a doped poly-two layer 12 〇, for example, disposed between the selection _116 and the control inter-electrode, the storage layer, and the material of the gate 116 and the underlying layer 12G. The thickness of the fU 1 electrical layer 120 formed by the high temperature thermal oxidation method is between 120 angstroms and 130 angstroms. The partial polysilicon underneath the auxiliary gate 118 forms an inversion layer 124 when a portion of the dielectric layer between the selective and substrate contacts is selected as the voltage. The material of the auxiliary gate 118 is, for example, 掺8, and the electricity is not placed between the auxiliary chamber 118 and the control electrode. Dielectric / / 22 7 ' and auxiliary idle 118 and substrate 100 fossil layer. In addition, for example, oxygen formed by high-temperature thermal oxidation is used as an auxiliary gate between the dielectric layer and the dielectric layer 120 between 130 angstroms. Electrical layer. " Electrical layer 122 thickness between 120 angstroms to 130796^702 19830 twf.doc / e in the auxiliary gate m and control gate l 〇 8, the charge storage layer (7). The material for selecting the gate 116 and the control gate is, for example, a nitrogen shirt, (10) because the portion of the storage layer 1 〇 4 is horizontally two thick, 108 and is located below the spacer 112a, so that the charge == two, the gate 116 The part has a corner (9), which is caused by the corner 126 when the read and the cell are erased.

=: = the child is pulled from the charge storage layer 104 to the selected interpole 丨; Further, the doped region 114 is electrically connected to the bit line 128, for example, by the plug 130. The plug 13G and the bit line 128 are read, for example, of a conductor material.

In the non-volatile memory of the eclipse of the month, the two memory cells of the _ _ are configured in a mirror-symmetrical manner, that is, the adjacent two memory cells share the auxiliary gate or doped region. For example, the memory cell Q1 shares the auxiliary gate with the memory cell Q2; the memory cell Q2 and the memory cell Q3 co-transform region; the memory cell Q3 shares the auxiliary gate with the memory cell Q4. Therefore, the structure of the multi-stage non-volatile memory of the present invention can simplify the manufacturing process, reduce the manufacturing cost, and improve the integration of components. Moreover, when a voltage is applied to the auxiliary gate 118 to open the channel under the auxiliary gate 118 and the inversion layer 124 is formed, a voltage is applied to the inversion layer 1% so that the inversion layer 124 under the auxiliary gate 118 can In pre-charged state. In the stylization of the non-volatile memory of the present invention, the memory cell can be programmed by the source side injection effect by means of channel self_b〇osting, which can improve the programming speed. And 18 13 07% & 19830twf.doc/e and 'when this non-volatile memory is used as a multi-level memory cell, the programmed voltage can be accurately controlled during the stylization operation. The starting voltage is programmed. In the range. For example, the multi-level memory cell is read by the reference voltage Vrefl,

VreG, Vref3 ' to discriminate four different threshold voltages (Threshold Voltage) Vthl, Vth2, Vth3, Vth4,

Vthl < Vrefl < Vth2 < Vref2 < Vth3 < Vref3 < Vth4. Vthl is, for example, less than 〇 volts, denoted as "〇〇" state; Vref1 is, for example, 〇 volts; _ Vth2 is, for example, 0.2 to 2 volts, expressed as "〇1" state; Vref2 is, for example, 2.2 volts; Vth3 is, for example, 2· 4 to 4.2 volts, expressed as "1 〇" state; Vref3 is, for example, 4.4 volts; Vth4 is, for example, greater than 44 volts, and the table is not "11" state. When stylizing, in order to make the memory cell in the "〇1" or "10" state, it is necessary to make the starting voltage of the memory cell accurately fall within the range of ο.?~2 volt or 2.4~4.2 volt. Since the memory cell is in the range of the starting voltage in the "〇1" or "10" state, it is necessary to perform multiple stylization steps and stylization confirmation steps so that the stylized memory cell is accurately at the set starting voltage. This will take a long time. However, if self-accelerated charge injection (channel self_b〇〇sting) is used, the source side injection effect is used to program the memory cell, and the auxiliary inter-electrode channel is charged to the set voltage in advance, and the program can be quickly executed. The memory cell is in the state of "or "1". As for the "η" state, you can use the self-accelerating method or the self-accelerating charge (ehannd self_bGGSting) κ to perform the stylization, 0 19 1307% & 02 19830twf. Doc/e

It is depicted as a programmatic operation of the memory cell. Figure 2A is a diagram showing the example of the memory cell being erased by 2C. Referring to Figure 2, the money is stroked. AG applies voltage Vag to assist pre-assisted closure

^ L L The starting voltage of the gate AG, the voltage 2a is, for example, VI is 5 volts. g is, for example, about 8 bats. The voltage is then 'in the control gate (^ applied voltage Vpi: at == voltage = ^_ voltage, voltage ¥ is greater than or equal to the selected gate ': two: mate ^;, Vp2 is greater than special; voltage V1 (four) is for example L5 volt M Vi is greater than New VP3 'Voltage Vp3 is for example 〇 volt right' to program the memory cell using the source side injection effect. Adding Ray 2B, when performing the erase operation, the selection of the gate is made to apply the sleeve and set the base material 'The money in the charge storage layer', '! k select the open pole SG is pulled out and removed, where the voltage Vel = differential pressure will bow the mFN wear effect. The dragon Vel is, for example, ^ to 15 volts or so. 2C', when performing a read operation, applying a voltage Vr2 to the control gate CG at the auxiliary gate 〇 = = voltage Vrl ', applying a voltage Vr2 to the gate, and applying a voltage to the secret region D to read 20 130796§〇2 19830twf.doc/e where the voltage Vrl is determined, for example, by the resistance of the substrate under the auxiliary gate, and the voltage Vrl is, for example, Vcc (supply voltage). The voltage Vr2 is, for example, about 14 volts. The voltage Vr3 It is greater than the starting voltage of the selection gate, and the voltage Vr3 is, for example, Vcc (supply voltage). The voltage Vr4 is, for example, about 5 volts. In the case of the above bias voltage, the digital information stored in the memory cell can be judged by detecting the channel current of the memory cell. In the operation method of the present invention, The method of accelerating charge injection (channel self_b〇osting) uses the source side injection effect to program the memory of the memory, and the channel of the auxiliary gate is charged to the set voltage in advance, so that the memory cell can be quickly programmed. The selection of the gate to erase the memory cells, so that the electrons are removed through the selection gate, can reduce the number of electrons crossing the tunneling dielectric layer, * improve component reliability. In addition, the charge storage layer is adjacent to the gate Having (4). When erasing, the electric field is concentrated by the corner, and the erasing operation speed of electrons pulling out from the charge storage layer to the selection gate can be improved. FIG. 3 is a multi-stage non-volatile process of the present invention. A circuit diagram of an embodiment of a S memory cell composed of a memory cell. As shown in FIG. 3, the memory cell array is, for example, a memory cell QU~Q44, an auxiliary gate, and a line AL1. AL2, a plurality of bit lines BL1 to BL4, and control gate lines CL1 to CL4. The memory cells Qn to Q44 are shown in the above-mentioned Q1 to Q4 in Fig. 1. The memory cells Q11 to Q44 are arranged in a row/column array. In the X direction (bidirectional two-way) soil 'memory cells Q11~Q14 are, for example, mirrored. The two adjacent ''I Q11~Q14 will share an auxiliary gate or immersion area. For example, 21 Ό 2 19830twf .doc/e says that memory cells Qll and Q12 share the auxiliary gate; memory cells Q12 and q13 share the drain region; memory cells Q13 and Q14 share the auxiliary gate. The plurality of auxiliary gate lines AL1 to AL2 are arranged in parallel in the Y direction (column direction) and are connected to the auxiliary gates of the memory cells of the same column. For example, the auxiliary gate line AL1 is connected to the auxiliary gate of the memory cell Q11~memory cell Q41 and the memory cell Q12~memory cell Q42; the auxiliary gate line AL2 is connected to the memory cell Q13~memory cell Q43 and the memory cell Q14~memory cell The auxiliary gate of Q44. The plurality of bit lines BL1 to BL4 are arranged in parallel in the X direction (row direction) to connect the drain regions of the memory cells of the same row. For example, the bit line Bu is connected to the drain region of the memory cell Q11 to the memory cell Q14; the bit line BL2 is connected to the drain region of the memory cell Q21 to the memory cell Q24; and so on, the bit line BL4 Connect the bungee region of memory cell q41 ~ memory cell q44. A plurality of control gate lines CL1 to CL6 are arranged in parallel in the column direction, and are connected to the control electrode of the same-shaped memory cell. For example, the control idle line CL1 is connected to the control cell of the memory cell Q11~memory cell Q41; the control inter-pole line CL2 is connected to the control gate of the memory cell φ2~memory cell Q42; ...and thus, the gate line is controlled CL4 is connected to the control gate of memory cell Q14~memory cell 44. The plurality of selection gate lines SL1 to SL4 are arranged in parallel in the column direction, and are connected to the selection of the same-shaped memory cell. For example, the selection of the interpolar line SL1 is connected to the selective closed pole of the memory cell Q11 to the memory cell Q41; the selection of the interpolar line SL2 is connected to the selected gate of the memory cell Q12 to the memory cell Q42; Line SL4 is connected to the memory cell Q14~memory cell_^22 13079<^t)2 19830twf.doc/e Select the gate. The transistor ΤΙ, the drains D1 and D2 of T2 are connected to the substrate under the auxiliary gate lines AL1 to AL2. When a voltage is applied to the auxiliary gate lines AL1 and AL2 to open a channel under the auxiliary gate lines AL1 and AL2, and an inversion layer is formed, and the gates G1 and G2 of the transistors ΤΙ and T2 are applied with a voltage to turn on the transistor. In the case of the channel of T2 and T2, the currents applied to the source electrodes S1 and S2 of the transistor ή and T2 flow through the drain electrodes D1 and D2 to the inversion layer below the auxiliary gate lines AU and AL2. Then, the channel of the transistor τB2 is turned off and the voltages of the auxiliary gate lines AL1 and AL2 are pulled, so that the inversion layer under the auxiliary gate lines AL1 and AL2 can be in a precharge state, that is, the voltage of the inversion layer is greater than The source voltages of SI and S2 are reduced by the initial voltages of the transistors Ή and Τ2. In the case of the non-volatile memory of the present invention, by self-adding, the charge injection (ehaimel self_b(K)Sting) can be simplified. Moreover, when this non-volatile memory is used as a multi-level memory, the starting voltage after stylization is within the set range. Next, the non-volatile memory of the present invention will be described as including the operation (4) mode of the non-volatile memory of the invention, which is programmed, erased, and erased. The preferred embodiment is described as an example. However, the present invention is not limited to the following, and is not limited to the method. = The operation of the memory is interrupted. The memory array is arbitrarily operated. 4a is shown as the opposite of the memory operation. 4B is a schematic diagram showing a consistent example of a memory array. Figure 23 is an example of an example 23 (2 19830 twf.doc/e diagram. Moreover, in the following description, the memory unit Q13 shown in Fig. 3 is taken as an example. Please refer to Fig. 3 and Fig. 4A' When the memory cell Q13 is programmed, 'the voltage vtg is applied to the gate of the transistor ΤΙ, T2 in advance; the voltage vts is applied to the sources SI and S2 of the transistor τι, T2; and the voltage Val is applied to the auxiliary gate line AL2 to An inversion layer L2 is formed in the substrate under the auxiliary gate line AL2, and the inversion layer L2 is turned on by a voltage Vts_Vth, where vth is the initial voltage of the transistor Tb and T2, and the voltage of the auxiliary gate line AL1 is Maintain 0 volts, so no inversion layer is formed in the underlying substrate. Then 'turn off the transistor ΤΙ, T2 channel' and pull the voltage of the auxiliary gate line AL2 up to about 8 volts to couple the inversion layer L2 The voltage is about 5 volts, so that the inversion layer L2 can be in a precharge state, wherein the 'voltage vtg is, for example, greater than or equal to the start_voltage Vth of the transistors T1, T2 to open the channel of the transistor Ding Ding 2 The voltage Vtg is, for example,

Vcc (supply voltage). The voltage Vts is, for example, Vcc (the power supply voltage W is, for example, greater than or equal to the starting voltage of the auxiliary gate, for example, starting with the reference Vcc (supply voltage)') until the transistors, T2_, and then pulling up by about volts. After ^^, a voltage vpl is applied to the selected control gate line CL3, a voltage Vp2 is applied to the selected closed line SL3, and a voltage Vp3 is applied to the selected bit line Bu1. The electric dust Vpl is, for example, about w volts; Electric dust ^You ί or equal to the starting power of the gate SG, the voltage Vp2 is for example 1.5 sex Ϊ right 'electricity VtS is greater than the electric wish Vp3 'electrical repeated Vp3 for example 0 volt temple right to use the source side The injection effect is programmed to select the memory cell. 24 1307%^〇2 19830twf.doc/e In the above stylized operation, the control gate line CL3, the selection gate line SL3 and the auxiliary gate are shared with the selected memory cell QU. For other unselected memory cells Q23, Q33, and Q43 of line AL2, voltages may be applied to the unselected positioning element lines BL2, BL3, and BL4 to which the unselected memory cells Q23, Q33, and Q43 are coupled to suppress non-selection. Memory cells Q23, Q33 and Q43 are stylized. Also 'because they are not selected The control gate lines cli, CL2, and CL4 are not applied with voltage, so other unselected memory cells qU to Q41, Q12 to Q42, and Q14 to Q44 are not programmed. § Scratchly with reference to FIG. 3 and FIG. 4B, the erase operation is performed. When a voltage Vel is applied to the selection gate lines SL1 to SL4, the substrate is floated so that electrons stored in the charge storage layers of all the memory cells Q11 to Q41, Q12 to Q42, Q13 to Q43, and Q14 to Q44 are selected. The gate is pulled out and removed, wherein the voltage difference between the voltage Vel and the substrate causes an FN tunneling effect. The voltage Vel is, for example, about 11 to 15 volts. Referring to FIG. 3 and FIG. 4C, when performing a read operation, The selected auxiliary gate line AL2 applies a voltage Vd' to apply a voltage Vr2 to the selected control gate line CL3, applies a voltage Vr3 to the selected gate line SL3, and applies a voltage Vr4 to the selected bit line BL1 to read the memory. The voltage Vrl is determined, for example, by the resistance of the substrate under the auxiliary gate line, and the voltage Vrl is, for example, Vcc (supply voltage). The voltage Vr2 is, for example, about L4 volts. The voltage Vr3 is greater than the starting voltage of the selected gate. For example, Vcc (supply voltage). The voltage Vr4 is, for example, about 1.5 volts. As for the unselected auxiliary gate line AL1, the unselected control gate lines CLI1, CL2, CL4, the unselected selection gate lines SL1, SL2, SL4, the unselected bits 25 Ό 2 19830tw£doc/c Ό2 19830tw£doc/c

« The main lines BL2, BL3, BL4 are not applied with voltage or floating. In the above bias condition, the digital information stored in the memory cell can be determined by detecting the channel size of the memory cell q13. In the operation method of the present invention, since the source-side injection effect is used, the source side injection effect is used, and the channel of the auxiliary gate is charged in advance to the channel of the auxiliary gate. Set the battery [can quickly program the memory cell. Moreover, by using the selection gate to erase the memory cell, the electrons are removed via the selection gate, which can reduce the number of times of crossing the tunneling dielectric layer and improve component reliability. In addition, there is (4) where the gate is selected by the drain layer. When the erasing is performed, the electric field is spread by the electric field, and the erasing operation speed of the electrons from the charge dislocation layer to the selection gate can be increased. Next, a method of producing the non-volatile memory of the present invention will be described. FIG. 5G is a flow cross-sectional view showing a method of manufacturing a memory in accordance with an embodiment of the present invention. Hui Fa ° a First, please refer to FIG. 5A, a substrate 200 is provided. This base of 200 cases of female 疋石夕 base. A dielectric layer 2〇2 is formed on the substrate 200. The material of the dielectric sound is, for example, oxygen cutting, and the method of forming the dielectric layer is, for example, a (four) method. Then, a layer of charge storage layer is formed on the dielectric | 2〇2. = The material of the storage layer 204 is, for example, a conductor material (such as a polycrystalline spine). It is sufficient to cause the charge to be trapped in the material of the towel, such as smear, nitrous oxide, titanate or yttrium oxide. The material of the charge storage layer is determined by the method of chemical vapor deposition, for example, after forming an undoped polycrystal (IV) by chemical vapor deposition, and then performing the ion implantation step (10), ^ 26 1307 19830 twf.doc /e can also be formed by chemical vapor deposition by means of on-site implant doping. Moreover, when the charge storage layer 204 is a conductor material, the charge storage layer 204 is, for example, strip-shaped (not shown). An inter-gate dielectric layer 206 is then formed on the substrate 200. The material of the inter-gate dielectric layer 206 is, for example, yttrium oxide/yttria/yttria, which is formed by, for example, forming a layer of ruthenium oxide by thermal oxidation, and then sequentially forming a layer of nitridation by chemical vapor deposition. The tantalum layer and another layer of tantalum oxide. Of course, the material of the inter-gate dielectric layer 206 may also be tantalum oxide, tantalum nitride, tantalum oxide or the like. Next, referring to FIG. 5B, a conductor layer (not shown) and a top cap layer (not shown) are formed on the inter-gate dielectric layer 206. Then, the cap layer, the conductor layer and the inter-gate dielectric layer 206 are patterned to form a plurality of stacked layers 212 composed of the inter-gate dielectric layer 2, such as the conductor layer 208 and the cap layer 210. The material of the conductor layer 208 is, for example, a doped polysilicon, which is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, performing an ion implantation step, or forming a dopant by field implantation. The method is formed by chemical vapor deposition. The conductor layer 2〇8 is used, for example, as a control gate. The material of the cap layer 210 is, for example, tantalum nitride or hafnium oxide, and its formation method is, for example, chemical vapor deposition. Next, referring to FIG. 5C, a patterned mask layer 214 is formed on the substrate 200. The patterned mask layer 214 has an opening 216 that exposes at least the conductor layer 204 between each two stacked layers 212. The patterned mask layer 214 is then a mask that removes the conductor layer 204' between each two stacked layers 212 to form a trench 218. The method for forming the trench 218 is, for example, ^ 27 13079 02 1983 twf.d 〇 c / e to expose the dielectric stack 212 - the conductor layer is the photoresist surface. The material of the patterned mask layer 214 is, for example, a process. The method of forming the mask layer 214 (four) is, for example, lithography; as shown in Fig. 5D, the patterned mask layer 214 is removed. After removing the mask A of the figure, after removing the sidewalls of the large sidewalls and the trenches, the spacers 220 are formed on the stacked layers 212. The spacer 220 is made of a material such as a dielectric material or other dielectric material. Example of forming a spacer top 2 〇Γ. ^ Phase gap wall (four) layer 'four shape' (four) live the entire base layer, to form a non-isotropic silver engraving, remove part of the spacer material and then, referring to Figure 5, with spacers 22, stacked layers = The exposed conductor layer is removed so that each of the stacked layers is ^= into the storage layer 2〇4a. The dielectric layer 2 〇 2 between the charge storage layer 鸠 and the second technique G 0 is, for example, a tunneling dielectric layer. A conformal dielectric layer 222 is then formed thereon. The material of the dielectric layer 222 is, for example, a hot-oxidized layer. The method of forming the dielectric layer 222 is, for example, a high-temperature thermal oxidation method. Subsequently, referring to FIG. 5F, a conductive layer 22 is formed between the two stacked layers 212 and formed on the sidewalls outside the two stacked layers 212; The layer 224 fills the trench 218. The conductor layer 224 and the material of the conductor layer 226, for example, ytterbium doped (tetra) crystal 7, are formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, performing an ion implantation step to form, or may be employed. The method of implanting the dopant in the field is chemical vapor deposition 28 1307鄕2 19830twf.doc/e ft ΐ. Forming layer doping prior to substrate 2GG using the above method

Divided: Heterolithic; ΐ亍 etchback process (non-isotropic etching process) removal section The blade is doped to the top layer until the top 2iG = and the conductor layer 226 are exposed. The conductor layer 224 is, for example, an auxiliary closed =, a dielectric layer 222 between the layer 224 and the substrate 200, and a dielectric layer 2, for example, 疋 as an auxiliary gate dielectric layer. The conductor layer is 226 poles. The dielectric layer 202 between the conductor layer 226 and the substrate 200 is, for example, a selective gate dielectric layer. Dielectric layer and dielectric

The sum of the thicknesses of layer 202 is, for example, between 120 angstroms and 13 angstroms. Then, doped regions 228 are formed in the substrates 20A outside the two stacked layers 212, respectively. This doped region 228 is, for example, a drain region. Doped region 228

The formation method is, for example, an ion implantation process. The conductor layer 2 26 is formed, for example, on the substrate 200 between the doped region 228 and the conductor layer 208. Subsequently, referring to FIG. 5G, an interlayer insulating layer 230 is formed on the substrate 200. The material of the interlayer insulating layer 230 is, for example, cerium oxide, phosphoric glass, borophosphon glass or other suitable dielectric material, and is formed by a chemical oxygen phase deposition method, for example. Then, a plug 232 electrically connected to the doping region 228 is formed in the interlayer insulating layer 230. The plug 232 is formed by, for example, patterning the interlayer insulating layer 230 to form an opening exposing the doped region 228, and then filling the opening with a conductor material. Thereafter, a conductor layer 234 electrically connected to the plug 232 is formed on the interlayer insulating layer 230. The conductor layer 234 is, for example, a bit line. The subsequent process of completing the non-volatile memory is well known to those skilled in the art and will not be described here. 1307丨19830twf.doc/e—In the manufacturing method of the non-volatile memory of the present invention, the auxiliary gate (conductor layer 224) and the selective gate (conductor layer 226) are formed by self-alignment. No need to use the lithography process, so you can save on the cost and increase the process margin. Moreover, since the formed charge storage layer 204a has a corner at a portion close to the selection gate (the conductor layer 226), the electric field is concentrated by the corner of the memory cell, and the electrons can be increased from the charge storage θ 〇 The erase operation speed to the selected interpole (conductor layer 226). In the above-mentioned multi-stage non-volatile memory of the present invention, adjacent two are arranged, for example, in a mirror symmetrical manner, that is, adjacent memory cells share an auxiliary open or doped region, thereby improving component Accumulation? : and: When a voltage is applied to the auxiliary gate to open the auxiliary gate; when, and, and an inversion layer is formed, a voltage is applied to the inversion layer, and the counteraction can be in (4) the charged state. When stylizing the "volatile memory" of the present invention, by self-accelerating charge = _bQ〇sted_ehaFge injeetiGn), the _ source side note is used to program the memory cell, which can improve the stylization fantasity. When the memory is used as a multi-order memory cell, it is within the range of _ _ _ ^. The stalk is located in the yoke of the fork. In addition, since the formed charge storage layer has a corner in the ^, the memory cell is wiped. _, two, the corners make the electric field concentrated, and can increase the electrons from the charge storage: the speed of the erase operation of the pole. e杈 to select the gate 30 1307965) 2 19830twf.doc / e 1307965) 2 19830twf.doc / e

In addition, the multi-stage non-volatile memory of the present invention is simple in manufacturing method, can reduce manufacturing cost, and increase process margin. The present invention has been disclosed in the above embodiments, and it is not intended to limit the present invention. Any one skilled in the art can protect the present invention even if it can be made more difficult without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the structure of a non-volatile memory according to an embodiment of the present invention. X ° ~ Figure 2A is a schematic diagram of one of the stylized operations on the memory cell. FIG. 2B is a schematic diagram showing an example of erasing a memory cell. Fig. 2C is a diagram showing an example of a reading operation on a memory cell. And, ® 3 are circuit diagrams showing an embodiment of a memory cell array composed of the multi-stage non-volatile memory cells of the present invention. Figure 4A is a schematic diagram showing an example of a singulation operation of a memory array. Figure 4B is a schematic illustration of an example of an erase operation of a memory array. Figure 4C is a schematic diagram showing an example of a read operation on a memory array. 5A through 5G are schematic cross-sectional views showing a process of manufacturing a non-volatile memory according to an embodiment of the present invention.曰31 1307 9^0^02 19830twf.doc/e [Description of main component symbols] 100, 200: substrate 102: tunneling dielectric layers 104, 204, 204a: charge storage layers 106, 206, 206a: dielectric between gates Layer 108, CG: Control gate 110, 210: Top cover layer 111, 212: Stacked layer • 112a, 112b, 220: Clearance wall 114, 228: Doped region 116, SG: Select gate 118, AG: Auxiliary gate Pole 120, 122, 202, 222: dielectric layer. 124, L, LI, L2: inversion layer 126: corner 128, BL1~BL4: bit line repair 130, 232: plug - 208, 224, 226, 234: conductor layer 214: patterned mask layer 216: Opening 218: trench 222: dielectric layer 230: interlayer insulating layer AG: auxiliary gate 32 1307945) 2 19830twf.doc/e AL1 to AL2: auxiliary gate lines CL1 to CL4: control gate line. D. Wave zone Dl, D2: Bungee G1~G2: Gate 亟 Q1~Q4, Q11~Q44: Memory cell SI, S2: Source ΤΙ, T2: Transistor

33

Claims (1)

I307%5)2 19830twf.doc/e X. Patent application scope: 1. A multi-stage non-volatile memory comprising: a first memory cell disposed on a substrate; the first memory cell comprises: a control a gate is disposed on the substrate; a charge storage layer is disposed between the edge control gate and the substrate; and a replacement region is disposed in the bottom of the first side of the control gate; a selection gate disposed on the sidewall of the first side of the control gate and located on the substrate between the control gate and the doped region; and an auxiliary gate disposed at the control gate a side wall of the second side, and when a voltage is applied to the auxiliary (5) gate, an inversion layer is formed in the substrate under the auxiliary closed electrode. 2 The multi-stage non-volatile as described in claim 1 includes: an X-first dielectric layer disposed between the charge storage layer and the substrate; a second dielectric layer disposed on the The charge storage layer and the memory of the control electrode are a third dielectric layer, and are: a • between the auxiliary gate and the control gate, the current gate, the layer=between, and the auxiliary gate and the substrate Between the 丨 and / the charge gambling f, and the selection of the closed pole and the substrate = closed pole, the 3 = the scope of the second paragraph of the patent application form a gap. Between the storage layers, 34 13 079 knees 19830 twf.doc / e 4. The body described in claim 2, wherein the first electrical layer has no _ The multi-level non-volatile memory of claim 1, wherein the material of the first dielectric layer comprises yttrium oxide. 6_ The multi-stage non-volatile memory as described in claim 2, wherein the material of the second dielectric layer comprises oxidation; 7 'Multi-stage non-volatile memory as described in claim 2, wherein the third dielectric layer and the fourth dielectric layer are a high temperature thermal oxide layer. 8. The multi-stage non-volatile memory of claim 2, wherein the thickness of the third dielectric layer and the thickness of the fourth dielectric layer are between 100 angstroms and 200 angstroms. 9. The multi-stage non-volatile memory of claim 1, further comprising a first memory cell, the second memory cell having the same structure as the first memory cell, and the second The memory cells are disposed adjacent to the first memory cell in a mirror symmetrical manner. 10. The multi-stage non-volatile memory of claim 9, wherein the second memory cell is disposed on the first side of the first memory cell and shares the doping with the first memory cell. Area. 11. The multi-stage non-volatile memory of claim 9, wherein the second memory cell is disposed on the second side of the first memory cell, and the auxiliary electrode is shared with the first memory cell . 12. The multi-stage non-volatile memory as described in claim 1 further comprising a cap layer disposed on the control gate. 13. The multi-stage non-volatile memory 35 130791⁄2 2 19830 twf.doc/e body as described in claim 12, wherein the charge storage layer portion protrudes horizontally from the control closed electrode and adjacent to the selection gate The location has a corner. 14. A multi-stage non-volatile memory comprising: a plurality of memory cells disposed on a substrate as a row of memory cells comprising: J a control gate disposed on the substrate; a charge storage layer disposed on Between the control gate and the substrate; a doped region, the 曰 base set on one side of the control gate, a select gate disposed on the side of the first side of the control gate J 'and on the substrate between the (four) pole and the doped region; and an auxiliary closed pole, the memory cells disposed on the side of the second side of the control idler are mirrored Symmetrically adjacent, but the plurality of bit lines are arranged in parallel in the row direction, connecting the doped regions of the two 5 cells of the same row; ^ number of control gate lines arranged in parallel in the column direction The control gate of the same - 0 falling memory cell; ^ several selected gate lines, arranged in parallel in the column direction, connecting the selected gates of the memory cells of the same column; the column has a small auxiliary gate line, Arranged in parallel in the column direction, connecting the auxiliary gate of the same-Μ6 6 memory cell; And the gates of the transistors at the bottom of the gate are respectively connected to the auxiliary 36 I30796 & 19830twf.doc / e body, = object 14 item _ volatile memory - first dielectric layer, set _ charge layer _ a second dielectric layer 'disposed on the charge reservoir layer and the electrical layer' is disposed between the auxiliary closed electrode and the control open electrode, and between the auxiliary gate and the substrate, / between the charge storage layers, and the selection = the closed pole, the body, wherein the third dielectric layer 盥 non-volatile memory is formed with a spacer. The gate electrode, the charge storage layer body, the multi-stage non-volatile memory described in item 15 of the ι 17^ circumference has a spacer. The body 'where the first dielectric layer, 15 of the _ home _ volatile memory ^ such as the application run Wei cut / _. Body, wherein the (four) electric ^ ^ ^ ^ _ volatile memory, wherein the charge stores (four) volatile memory and adjacent to the selected idle pole two for the control of the idle pole, the body, the multi-step non-volatile The adjacent two memory cells of the memory are said to share the bungee region. 37 1307965 pt.ap702 19830twf.doc/e 23. The body described in claim 14 of the patent application, wherein the two memory cells are mirror-symmetrical to each other. The two memory cells share the same. 24. A method for manufacturing a multi-level non-volatile memory The method includes: sequentially forming a tunneling dielectric layer on a substrate, and forming at least two stacked layers on the charge storage layer, wherein each of the two stacked layers sequentially includes a gate dielectric layer, and a control gate The pole and the two top cover remove the charge storage layer trench between the two stacked layers; the money first forms a sidewall of the two stacked layer sidewalls and the first trench sidewall; the spacer layer serves as a mask Removing the electric current on the outer side of the two stacked layers to form a dielectric layer on the substrate; 々tw forming an auxiliary gate between the stacked layers and forming a selection on the sidewalls outside the two stacked banks a gate electrode; and θ respectively forming a doping region in the substrate outside the two stacked layers and the selection gate is located between the stacked layer and the doped region. 25. Please use the high-temperature thermal oxide layer. The dielectric layer consists of a high-temperature thermal oxide layer. ^ 26. The non-volatile manufacturing method as described in the scope of the patent application, wherein the thickness of the dielectric layer is in the range of the non-volatile memory of the 24th meal of the 2nd party, / Forming the auxiliary gate between the two stacked layers, and the method of apologizing (4) to the selected pole comprises: forming a layer of a conductor material on the substrate, the conductor material layer being filled The 38 丨 2 19830 twf.doc/e first ditch; and the dew:: engraving process 'removing part of the conductor material layer until the violent body's (four) idiopathic memory %, the material of the (four) dielectric layer in the gentry Including the oxidized stone eve. The manufacturing side of the body: the second two = the multi-level non-volatile memory method. The formation method of the Ul electrical layer includes the thermal oxidant's 24 items of _ _ 记忆 记忆 记忆 夕 Z Z Z The material of the electric layer includes the multi-step non-volatile memory method described in item 22 of the oxidized stone/nitride body, wherein the material of the charge storage layer includes the modified polycrystalline stone eve. _ volatile clock operation method, suitable for a memory cell including: - control gate, set Placed on the substrate; the storage layer is disposed between the control gate and the substrate; - the non-polar region, the ^1 is in the substrate on the first side of the idle pole; On the substrate; and an auxiliary == controlling the sidewall of the second side of one of the gates, the method comprising: applying a pre--the underside of the auxiliary idler to the gamma electrode during the feeding operation Forming an inversion layer in the substrate and applying a second voltage to the inversion layer; and applying a third voltage to the gate control gate, applying a 391307% & 19830twf.doc/e to the selection gate :: ^' is applied to the drain region - the fifth voltage, wherein the first voltage is the starting voltage of the closed pole, the third voltage is greater than the first; the fourth voltage is greater than or equal to the starting voltage of the selected value, The fourth voltage of the fourth voltage is used to program the reading body of the source side by using the source side effect. The multi-level non-volatile recording described in item 32==' wherein the first voltage is about 8 volts; 4 &.5 volts;; == volts; the fourth electric wish stone, the fifth voltage is about 0 volts. The electrical power between the 32-pin (four)-order scaly memory of the body, wherein the electrical potential difference between the sixth voltage and the substrate causes an FN tunneling effect. The multi-level non-volatile memory described in item 34 of the body wherein the sixth voltage is about 11 to 15 volts. The multi-stage non-volatile memory application described in Item 32 of the operation of the body is further included in the read operation, and an eighth power is applied to the auxiliary gate Reading the record begins with the application of the tenth area - the tenth health, to 37. If the ^ special ° " nine test in the starting voltage of the selected gate. Operation method 2 The non-volatile memory described in item 31 of the first factory is w volt left (the power supply is ten, the eighth electric large is about, the ninth is Vcc (the power supply is repeated), the tenth 1307965) 2 19830twf.doc/e The voltage is around 1.5 volts. 38. A method for operating a multi-stage non-volatile memory, which is applicable to a memory cell array composed of a plurality of memory cells, each of the memory cells comprising: a gate electrode disposed on the wire; a charge storage layer, set Between the gate and the substrate; a secret region disposed in the substrate on one side of the control gate; - a selection _, a sidewall disposed on the first side of the control gate And located on the substrate between the control gate and the doped region; and an auxiliary gate disposed on the second side of the control gate, wherein the memory cells are on the same row The mirror symmetrical manner is adjacently arranged; a plurality of strip lines are arranged in parallel in the row direction to connect the drain regions of the memory cells of the same row; and a plurality of control gate lines are arranged in parallel in the column direction to be connected with the same - The control poles of the memory cells; the plurality of strips select gate lines arranged in parallel in the column direction to connect the selected gates of the memory cells of the same column; the plurality of auxiliary gate lines are in the column direction Parallelly arranging the lion gates that connect the same-like memory cells; And a plurality of transistors, wherein the drains of the transistors are connected to the substrate under the auxiliary gate lines, the method comprising: applying a first voltage to the gates of the transistors in advance during the stylizing operation, Applying a second voltage to the sources of the transistors, and applying a third voltage to the auxiliary gate lines to form an inversion layer in the substrate under the auxiliary gate lines, and The inversion layer is turned on by the second voltage, and then the channels of the transistors are turned off, so that the inversion layer is in a precharge state; and the fourth voltage is applied to the selected control gate line. 41 1307娜'2 19830iwf.doc/e pole line application - fifth electric M, applying a third in the bit line of the slave, the third _ is greater than the starting voltage of the auxiliary closed poles, the fourth electric The starting voltage of the first:= is greater than the third voltage, and the second voltage is greater than the sixth source source side staging effect-selected memory cell. The multi-level non-volatile memory described in Item 38 of the body = Fang Shen ΓΓ: electric = - (power supply voltage, some electric crystals) power supply voltage; the first, about ig volts; two, about 5 volts; The sixth voltage is about Q volts. After the body's fall (4) non-volatile memory ::: high =::== after the channel, the auxiliary gate is about 5 volts. , ^ coupling the voltage of the inversion layer to the body 38 picking (four) the clearing memory memory application - the seventh voltage is divided by the operation of the selection gate, the selection gate line is pulled out and removed, wherein The voltage difference between the bottoms will trigger the FN (four) effect. The electric non-volatile memory of the matrix is 43. As the patent application range flute u s main gang. The operation method of the body further includes applying a H voltage to the advanced non-volatile memory-assisted gate line. When reading, the selected gate line is applied to the control gate line to apply a 42 I307%>52 19830twf.doc /e nine voltages, applying a tenth voltage to the selected gate line, applying an eleventh power to the selected bit line to read the memory cell, the tenth voltage being greater than the selected gate The starting voltage. 44. The method of operating a non-volatile memory according to claim 43, wherein the eighth voltage is Vcc (power supply voltage), the ninth voltage is about 1.4 volts, and the tenth voltage is Vcc (power supply) Voltage), the eleventh voltage is about 1.5 volts. 43