TWI304275B - Gallium nitride-based compound semiconductor multilayer structure and production method thereof - Google Patents
Gallium nitride-based compound semiconductor multilayer structure and production method thereof Download PDFInfo
- Publication number
- TWI304275B TWI304275B TW95110847A TW95110847A TWI304275B TW I304275 B TWI304275 B TW I304275B TW 95110847 A TW95110847 A TW 95110847A TW 95110847 A TW95110847 A TW 95110847A TW I304275 B TWI304275 B TW I304275B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- gallium nitride
- based compound
- compound semiconductor
- semiconductor laminate
- Prior art date
Links
Landscapes
- Led Devices (AREA)
- Semiconductor Lasers (AREA)
Description
1304275 九、發明說明: , 【發明所屬之技術領域】 . 本發明係關於一種對發出高輸出之藍、綠色或紫外領域 之光線的發光元件之製造有用的氮化鎵系化合物半導體積 層物及其製法。 【先前技術】 近年來,作爲發出短波長之光的發光元件用的半導體材 料,氮化物半導體材料受到了囑目。一般,氮化物半導體 B 係將以藍寶石單結晶爲首之種種氧化物結晶、碳化矽單結 晶及III-V族化合物半導體單結晶等作爲基板,並於其上藉 由有機金屬汽相化學反應法(MOCVD法)、分子線磊晶生長 法(ΜBE法)或氫化物汽相磊晶生長法(HVPE法)等來加以積 層。 現在,工業等級上最爲廣泛採用之結晶生長方法,係使 用藍寶石、SiC、GaN、A1N等作爲基板,並利用於其上使 用有機金屬汽相化學反應法(MOCVD法)進行製作的方法, B 在已設置上述基板之反應管內使用III族有機金屬化合物 及V族原料氣體,在溫度700°C〜1 200°C之區域,以使n 型層、發光層及Ρ型層生長。 在各半導體層之生長後,藉由於基板或η型層形成負 極,於Ρ型層形成正極,可獲得發光元件。 習知之發光層,爲了調整發光波長,使用已調整組成之1304275 IX. Description of the Invention: [Technical Field] The present invention relates to a gallium nitride-based compound semiconductor laminate useful for the production of a light-emitting element that emits light in a blue, green or ultraviolet region with high output and System of law. [Prior Art] In recent years, a nitride semiconductor material has been attracting attention as a semiconductor material for a light-emitting element that emits light of a short wavelength. In general, a nitride semiconductor B system uses a variety of oxide crystals, single crystals of tantalum carbide, and single crystals of a III-V compound semiconductor, including sapphire single crystals, as a substrate, and an organic metal vapor phase chemical reaction method thereon. (MOCVD method), molecular line epitaxial growth method (ΜBE method) or hydride vapor phase epitaxial growth method (HVPE method) or the like is laminated. At present, the most widely used crystal growth method in the industrial grade is a method in which sapphire, SiC, GaN, A1N, or the like is used as a substrate, and a method in which an organometallic vapor phase chemical reaction method (MOCVD method) is used, B The group III organometallic compound and the group V source gas are used in the reaction tube in which the substrate is provided, and the n-type layer, the light-emitting layer, and the ruthenium-type layer are grown in a region of a temperature of 700 ° C to 1 200 ° C. After the growth of each semiconductor layer, a positive electrode is formed on the ruthenium-type layer by forming a negative electrode due to the substrate or the n-type layer, and a light-emitting element can be obtained. Conventional light-emitting layer, in order to adjust the wavelength of light, use the adjusted composition
In GaN,並使用藉由InGaN而由高帶隙之層來合夾此之雙重 異質構造、使用量子井效果的多重量子井構造。 1304275 在具有多重量子井構造之發光層的氮化鎵系化合物半導 ’ 體發光元件中’當令井戶層之膜厚爲2〜3nm時,可獲得良 . 好之輸出。但有驅動電壓高之問題。相反,當令井戶層之 膜厚爲2nm以下等時,雖然驅動電壓下降,但無法獲得良 好之輸出。 另外’爲了提高發光輸出,提出一種如下之將發光層形 成爲點狀的量子點構造的方案。 例如’於日本特開平1〇-795〇1號公報及特開平1卜3 5 4 8 3 9 B 號公報等’揭示有包含量子點構造之發光層的發光元件, 量子點構造係藉由抗表面活性效果所形成。根據日本特開 平1 1 -3 548 3 9號公報,各發光體之尺寸,係以〇.5nm$高度 S50nm、0.5nmg 寬度 S200nm、106$ 密度 Sl〇13cm·2 爲較 佳’實施例中,係由高度6nmx寬度40nm所製作。 但是’由量子點所覆被之部分以外,與點區域比較,成 爲極端低之低電阻區域,而優先使得電流流動,另外,非 點部分對發光並無貢獻。藉此,在此處所提案之量子點構 B 造中,即便可提高一個個之發光體的發光效率,但整體上 仍有對流動之電流的發光輸出下降的問題。 另外,日本特開200卜687 3 3號公報,揭示含In之量子箱 構造。根據該公報,藉由在氫氣中對暫時形成之量子井_ 造進行退火處理,以引起井戶層之昇華,而作成一量子箱 構造。實施例中,量子箱具有200埃以下之尺寸,例如, 令其具有20埃x20埃x20埃之尺寸。發光體之密度雖未規 定,但根據所揭示之圖面,由發光體所覆被之面積係與間 1304275 隙之面積相同或間隙方較大。 、 簡言之’在該些技術中,在未形成有量子點或量子箱之 • 區域中’作成完全未形成點或箱之構造,所以,與形成有 量子點或量子箱之區域比較,成爲極端低之低電阻區域, 而於該部分優先流動電流。 在此種點或箱之未覆被的區域上未形成有發光體的構造 中,雖可見到驅動電壓下降的效果,但同時具有招致發光 輸出降低的問題’,而無法勝任實際的使用。 t 又,在日本特開200 1 -687 3 3號公報中,在形成通常之量 子井構造後’在氫氣中進行退火以使貫穿轉位上之InGaN 結晶分解,形成量子箱構造。但是,在氫氣中對量子井構 造進行退火,即使在殘留而應形成量子箱構造之部分,仍 誘發In之脫離,而產生使發光波長被短波長化的不利狀況。 另外,在美國專利申請公開US2003/0 1 60229A1號說明書 中,爲了獲得高效率之發光,提出一種在井戶層具有膜厚 之偏差的多重量子井構造的發光層。在該說明書中,在附 I 帶圖面所見的範圍,於全井戶層設置膜厚之偏差。 【發明內容】 本發明之目的在於,提供一種對可降低驅動電壓,且具 有良好發光輸出之氮化鎵系化合物半導體發光元件之製造 有用之氮化鎵系化合物半導體積層物。 本發明提供以下之發明。 (1) 一種氮化鎵系化合物半導體積層物,係在基板上具有 η型層、發光層及P型層’該發光層係交錯由井戶層及障 1304275 ' 壁層所積層之多重量子構造,且該發光層係配置爲由η型 - 層及Ρ型層所挾持,其特徵爲:構成該多重量子構造之井 % 戶層,係由厚度不勻之井戶層及厚度均勻之井戶層所構成。 (2) 如上述第1項之氮化鎵系化合物半導體積層物,其中 最接近Ρ型層之井戶層厚度均勻。 (3) 如上述第1或2項之氮化鎵系化合物半導體積層物, 其中最接近η型層之井戶層厚度均勻。 (4) 如上述第1至3項中任一項之氮化鎵系化合物半導體 ® 積層物,其中厚度均勻之井戶層的膜厚爲1.8〜5nm。 (5) 如上述第1至4項中任一項之氮化鎵系化合物半導體 積層物,其中厚度不勻之井戶層之薄膜部的膜厚爲2.7 nm 以下。 (6) 如上述第1至5項中任一項之氮化鎵系化合物半導體 積層物,其中多重量子井構造係將井戶層及障壁層作3至 10次積層之構造。 (7) 如上述第1至6項中任一項之氮化鎵系化合物半導體 ^ 積層物,其中障壁層係從In比率比形成GaN、AlGaN及井 戶層之InGaN小的InGaN構成之群中選出之氮化鎵系化合 物半導體。 (8) 如上述第7項之氮化鎵系化合物半導體積層物,其中 障壁層係GaN。 (9) 如上述第1至8項中任一項之氮化鎵系化合物半導體 積層物,其中障壁層係摻雜物。 (10)如上述第9項之氮化鎵系化合物半導體積層物,其 1304275 中摻雜物係從 C 、 Si 、 Ge 、 Sn ' Pb 、〇、S 、 Se 、 Te 、 Po 、 Be、Mg、Ca、Sr、Ba、Ra之群中選出之至少一種類。 (1 1)如上述第9或1 0項之氮化鎵系化合物半導體積層 物,其中摻雜物之濃度係1 X 1 〇 17 c πΓ 3至1 X 1 〇 18 c ηΓ3。 (1 2)如上述第1至1 1項中任一項之氮化鎵系化合物半 導體積層物,其中障壁層之膜厚爲7〜50nm。 (1 3 )如上述第1 2項之氮化鎵系化合物半導體積層物, 其中障壁層之膜厚爲14nm以上。 (1 4)如上述第1至1 3項中任一項之氮化鎵系化合物半 導體積層物,其中井戶層含有In。 (1 5 )如上述第1 4項之氮化鎵系化合物半導體積層物, 其中在障壁層之至少基板側表面存在有未含有In的薄層。 (16) —種忍化嫁系化合物半導體發光兀件,其特徵爲: 於上述第1至1 5項中任一項之氮化鎵系化合物半導體積層 物之η型層設置負極,於p型層設置正極。 (1 7) —種燈’其使用上述第1 6項之氮化鎵系化合物半 導體發光元件。 (18) —種上述第丨至15項中任一項之氮化鎵系化合物 丰導體積層物之製造方法’其特徵爲··在形成井戶層後, 藉由使該一部分之井戶層分解或昇華,以形成厚度不勻之 井戶層。 (19) 如上述第18項之氮化鎵系化合物半導體積層物之 製造方法,其中形成井戶層時之基板溫度Τ 1及使該一部分 之井戶層分解或昇華時之基板溫度Τ2,爲τΐ$Τ2。 -9- 1304275 (20)如上述第18或19項之氮化鎵系化合物半導體槙層 - 物之製造方法,其中該一部分之井戶層之分解或昇華,係 ^ 在含有氮源且未含有III族金屬源之氣體環境下進行。 (2 1)如上述第1 8至20項中任一項之氮化鎵系化合物半 導體積層物之製造方法,其中該一部分之井戶層之分解或 昇華’係在障壁層之形成步驟所進行。 本發明之主架構,係在形成發光層之多層量子構造的井 戶層’將厚度不勻之井戶層及厚度均勻之井戶層混合,根 B 據本發明’可獲得良好之發光輸出,且可降低驅動電壓之 氮化鎵系化合物半導體發光元件。 另外,根據本發明所獲得之氮化鎵系化合物半導體發光 元件,其逆方向耐壓特性之劣化少。 另外,藉由在氮源之存在下形成厚度不勻之井戶層,可 防止從井戶層產生之光的短波長化。 【實施方式】 周知,構成氮化鎵系化合物半導體發光元件之η型層、 ® 發光層及Ρ型層之氮化鎵系化合物半導體,係由一般式 AlxInyGai-x.yN(0Sx< 1、〇$y< 1、〇Sx + y< 1)所表示之各 種組成的半導體,而作爲本發明之構成η型層、發光層及 Ρ型層之氮化鎵系化合物半導體’可無任何限制地使用由 一般式 AlxInyGai-x-yN(0S x< 1、〇$ y< 1、OS x + y< 1)所表 示之各種組成的半導體。 至於基板,除可使用藍寶石、SiC外’可無任何限制地使 用GaP、GaAs、Si、Zn〇、GaN等以往公知之基板。 -10- 1304275 除GaN基板外,原理上爲了在與氮化鎵系化合物未作晶 格整合之該些基板上’使氮化鎵系化合物半導體積層,可 使用日本專利第3026087號公報、特開平4-297023號公報 所揭示之低溫緩衝法、特開2003 -243 302號公報等所揭示之 被稱爲SP(Seeding Process)法的晶格不整合結晶磊晶生長 技術。尤其是以可製作GaN系結晶之程度的高溫來製作A1N 結晶膜的S P法,係在提高生產性等之觀點上優良的晶格不 整合結晶磊晶生長技術。 在使用低溫緩衝法或S P法等之晶格不整合結晶磊晶生 長技術的情況,積層於其上面作爲襯底之氮化鎵系化合物 半導體,係以無摻雜或5x1 017cm·3程度之低摻雜的GaN爲 較佳。襯底層之膜厚,以1〜20 // m爲較佳,更以5〜1 5 // m 爲較佳。在其上依序積層有η型層、發光層及p型層。 本發明中,形成發光層之多層量子構造的井戶層,係必 定將厚度均勻之井戶層及厚度不勻之井戶層混合。本發明 中,「厚度均勻」係指膜厚在任一處均落在平均膜厚之±10% 以內。其中以落在±7 %以內爲較佳。「厚度不勻」係指具有 膜厚未落在平均膜厚之±10%以內的部分。「平均膜厚」係 指將該膜之最大膜厚與最小膜厚平均計算的膜厚。在厚度 不勻之井戶層中,稱比平均膜厚更厚之部分爲「厚膜部」, 而稱薄的部分爲「薄膜部」。 各井戶層之厚度是否均勻或不勻,可藉由氮化鎵系化合 物半導體的剖面ΤΕΜ照片來作判定及測定。例如,當由 200,000倍至2,000,000倍的ΤΕΜ照片來觀察剖面時,可測 -11- 1304275 ' 定各井戶層之膜厚變化。第3至第10圖爲藉由第 • 所製作之晶片的倍率1,000,000倍的剖面TEM照 、 慮倍率來計算出該膜厚。在各圖之邊上所附表內 各井戶層之在該圖中的最大膜厚及最小膜厚。從 8個圖所求得之各井戶層之最大膜厚及最小膜厚 各井戶層是厚度均勻之井戶層還是厚度不勻之井 平均計算最大膜厚與最小膜厚所求得之平均膜厚 分爲厚膜部,而更薄的部分爲薄膜部。圖中,A爲 ® B爲薄膜部。各井戶層之最大膜厚及最小膜厚, 察剖面TEM照面之複數處、例如、觀察距相鄰處隔 之間隔的至少8處所求得。 在形成發光層之多重量子井構造中的所有井戶 度不勻的情況,與在所有井戶層爲厚度均勻的情 雖然驅動電壓下降,但發光輸出亦下降或相同。 在未將所有井戶層之厚度作成不勻,而將井戶層 作成均勻厚度時,雖然未能充分地瞭解其理由, 動電壓下降,且發光輸出增大。尤其是,在最爲 層或η型層之井戶層厚度爲均勻的情況,其發光 大效果很大。在最爲接近ρ型層之井戶層及最爲 層之井戶層兩者之厚度爲均勻的情況,其發光輸 效果成爲最大,但驅動電壓之降低效果亦減少。 度均勻之井戶層’雖可包括最爲接近ρ型層之井 爲接近η型層之井戶層兩者,但以包括其中一方 厚度均勻之井戶層’尤其以包括最爲接近ρ型層 1實施例 片。可考 ,記載有 綜合該些 ,可判定 戶層。比 更厚之部 薄膜部, 可利用觀 開 2 0 ju m 層,爲厚 況比較, 但是,當 之一部分 但有使驅 接近P型 輸出之增 接近η型 出之增大 因此,厚 戶層及最 爲較佳。 之井戶層 1304275 '者爲較佳。 - 當厚度均勻之井戶層數增大時,驅動電壓之降低效果將 > 減少。因此,以厚度均勻之井戶層數爲1以上且爲井戶層 整體之數量的60 %以下爲較佳。尤以井戶層整體之數量的 4 0 %以下爲較佳。 以厚度均勻之井戶層厚度爲1.8〜5nm爲較佳。當爲該範 圍以外之厚度時,將招致發光輸出的降低。更以2.0〜3.5nm 的範圍爲較佳。 > 以厚度不勻之井戶層的厚膜部的厚度爲1.8〜5nm爲較 佳。當厚膜部爲該範圍以外之厚度時,將招致發光輸出的 降低。更以2.3〜3.5 nm的範圍爲較佳。另外,以厚膜部之 寬度爲10〜5000nm爲較佳。更以20〜lOOOnm爲較佳。 以厚膜部之比率相對井戶層整體爲30〜90%爲較佳,其 可實現驅動電壓之降低及輸出增大的雙方。更以60〜90% 爲較佳。該厚膜部及薄膜部之比率,亦可根據從剖面TEM 照片所求得之寬度的測定値來算出。 以薄0吴部之寬度爲1〜200nm爲較佳。更以5〜150nm爲 較佳。 以該厚膜部之最大膜厚及薄膜部之最小膜厚的差爲1〜 3nm程度爲較佳。以薄膜部之膜厚爲i.o〜27nm爲較佳。 薄膜部雖可包括膜厚爲零的範圍、即完全無井戶層之範 圍’但因其會成爲發光輸出降低的原因,所以,以其範圍 爲小範圍者較佳。以相對井戶層整體爲30%以下爲較佳, 更以20%以下爲較佳,而以1〇 %以下爲特佳。該比率可根 -13- 1304275 據剖面TEM照片之寬度的測定値來算出。 井戶層係以含In之氮化鎵系化合物半導體爲較佳。含In 之氮化鎵系化合物半導體,係容易成爲具有厚膜部及薄膜 部之構造的結晶系,另外,可以強發光強度進行藍光之波 長區域的發光。 障壁層除GaN、AlGaN外,亦可由In比率比構成井戶層 之InGaN更小的InGaN來形成。其中,以GaN較爲適合。 障壁層亦可爲積層多層之構造。在井戶層爲含In之氮化 鎵系化合物半導體的情況,以在障壁層之至少與基板側之 井戶層相接的表面設置未含In的薄層爲較佳。以藉由設置 該薄層來抑制井戶層中的In的分解昇華,使得發光波長之 穩定控制成爲可能爲較佳。該薄層係以與井戶層之生長溫 度相同程度的基板溫度所設爲較佳。 當於障壁層摻雜一摻雜物時,將使其驅動電壓降低而較 佳。作爲該摻雜物元素,可舉出C、Si、Ge、Sn、Pb、〇、 S、Se、Te、Po、Be、Mg、Ca、Sr、Ba、Ra 等。其中以 Si、 Ge爲較佳,更以Si爲特佳。 摻雜物之濃度,以5xl016cm_3〜lxl018cm·3爲較佳。若未 滿5x10 16cnT3,則將使得驅動電壓之降低效果減少。若超過 lxl018cirT3時,則有逆方向電壓特性變差的傾向。更以 lxl017cm_3 〜5xl〇17cm_3 爲較佳。 障壁層之膜厚,係以7 n m以上爲較佳,更以1 4 n m以上 爲較佳。當障壁層之膜厚薄時,則無法完全塡滿井戶層之 厚膜部及薄膜部的厚度差,阻礙了井戶層之厚膜部及薄膜 -14 - 8' 1304275 部的形成,從而引起發光效率的降低及老化特性的降低。 • 另外,當障壁層之膜厚過厚時,則引起驅動電壓的上昇及 . 發光輸出的降低。因此,障壁層之膜厚,係以50nm以下爲 較佳。 多重兩子井構造之積層次數,以3至10次爲較佳,更以 3至6次的程度爲較佳。在各井戶層及障壁層中,亦可使 組成及構造變化。 η型層通常爲1〜10//m、較佳爲2〜5//m的厚度,且由 ® 形成負極用之η接觸層及帶隙比發光層更大且相接於發光 層的η覆被層所構成。η接觸層及η覆被層亦可兼用。η接 觸層係以高濃度來摻雜Si或Ge爲較佳。摻雜該些摻雜物 所形成之 η型層,以將載子濃度調整爲5xlOI8cm·3〜 2xl019cnT3的程度爲較佳。 η覆被層雖可由AlGaN、GaN、InGaN等來形成,但在爲 InGaN的情況,當然以作成比發光層之InGaN的帶隙更大 的組成爲較佳。η覆被層之載子濃度,可與n接觸層相同, ® 亦可比其大或比其小。爲了使形成於其上之發光層的結晶 性更爲良好,以適宜調節生長速度、生長溫度、生長壓力、 摻雜量等的生長條件,而作成平坦性高的表面爲較佳。 另外,η覆被層亦可利用交錯多次地積層組成及晶格常 數不同之層來形成。此時,除藉由積層之層來改變組成外, 亦可使摻雜物之量、膜厚等變化。 Ρ型層通常爲0.01〜l//m的厚度,且由相接於發光層的 P覆被層及形成正極用之P接觸層所構成。p覆被層及p接 1304275 觸層亦可兼用。P覆被層係使用GaN、AlGaN等所形成,並 '摻雜Mg作爲p摻雜物。爲了防止電子之過多流動,以具有 ,比發光層之材料更大的帶隙的材料來形成爲較佳。另外, 以可有效地將載子注入發光層的方式,形成高載子濃度的 層爲較佳。 有關P覆被層,亦可利用交錯多次地積層組成及晶格常 數不同之層來形成。此時,除藉由積層之層來改變組成外, 亦可使摻雜物之量、膜厚等變化。 t P接觸層可使用GaN、AlGaN、In GaN等所形成,並摻雜In GaN, and a multi-quantum well structure in which a double-heterostructure with a high band gap is sandwiched by InGaN and a quantum well effect is used. 1304275 In a gallium nitride-based compound semiconductor light-emitting device having a light-emitting layer of a multiple quantum well structure, when the film thickness of the well layer is 2 to 3 nm, a good output can be obtained. However, there is a problem of high driving voltage. On the other hand, when the film thickness of the well layer is 2 nm or less, although the driving voltage is lowered, a good output cannot be obtained. Further, in order to increase the light-emitting output, a quantum dot structure in which the light-emitting layer is formed into a dot shape is proposed as follows. For example, a light-emitting element having a light-emitting layer including a quantum dot structure is disclosed in Japanese Unexamined Patent Publication No. Hei No. Hei. No. Hei. No. Hei. The surface active effect is formed. According to Japanese Laid-Open Patent Publication No. Hei No. Hei 1 1 - 3 548 399, the size of each illuminant is preferably 〇5 nm$ height S50 nm, 0.5 nm width S200 nm, 106$ density S1 〇 13 cm·2, in the embodiment, It is made of a height of 6 nm x a width of 40 nm. However, in addition to the portion covered by the quantum dots, it is an extremely low-low resistance region as compared with the dot region, and the current is preferentially flowed, and the non-dot portion does not contribute to the light emission. As a result, in the quantum dot structure B proposed herein, even if the luminous efficiency of each of the luminous bodies can be improved, there is a problem that the luminous output of the flowing current is lowered as a whole. Further, Japanese Patent Publication No. 200 687 333 discloses a quantum box structure including In. According to this publication, a quantum box structure is formed by annealing a temporarily formed quantum well in hydrogen gas to cause sublimation of the well layer. In an embodiment, the quantum box has a size of 200 angstroms or less, for example, having a size of 20 angstroms x 20 angstroms x 20 angstroms. Although the density of the illuminant is not specified, according to the disclosed surface, the area covered by the illuminant is the same as the area of the gap of 1304275 or the gap is large. In short, in these technologies, in a region where quantum dots or quantum boxes are not formed, a structure in which dots or boxes are not formed at all is formed, and therefore, compared with a region in which quantum dots or quantum boxes are formed, Extremely low and low resistance area, and current flows preferentially in this part. In the structure in which the illuminant is not formed in the uncovered region of such a dot or box, the effect of lowering the driving voltage can be seen, but at the same time, there is a problem that the illuminating output is lowered, and it is not suitable for practical use. Further, in Japanese Laid-Open Patent Publication No. 2001-68733, after forming a normal quantum well structure, annealing is performed in hydrogen gas to decompose the InGaN crystals in the transposition to form a quantum box structure. However, the quantum well structure is annealed in hydrogen gas, and even if a part of the quantum box structure is formed to remain, the detachment of In is induced, and an unfavorable situation is caused in which the emission wavelength is shortened. In order to obtain high-efficiency luminescence, a luminescent layer of a multiple quantum well structure having a variation in film thickness in a well layer is proposed in the specification of U.S. Patent Application Publication No. 2003/0 1 60229 A1. In this specification, the deviation of the film thickness is set in the whole well layer in the range seen in the attached panel. SUMMARY OF THE INVENTION An object of the present invention is to provide a gallium nitride-based compound semiconductor laminate which is useful for the production of a gallium nitride-based compound semiconductor light-emitting device which can reduce a driving voltage and has a good light-emitting output. The present invention provides the following invention. (1) A gallium nitride-based compound semiconductor laminate having an n-type layer, a light-emitting layer, and a p-type layer on a substrate; the light-emitting layer is interlaced with a multiple quantum structure in which a layer of a well layer and a barrier layer 1304275' are stacked, And the light-emitting layer is configured to be held by the n-type layer and the Ρ-type layer, and is characterized in that: the well layer constituting the multiple quantum structure is a well layer with uneven thickness and a well layer with uniform thickness Composition. (2) The gallium nitride-based compound semiconductor laminate according to the above item 1, wherein the well layer closest to the ruthenium layer has a uniform thickness. (3) The gallium nitride-based compound semiconductor laminate according to the above item 1, wherein the well layer closest to the n-type layer has a uniform thickness. (4) The gallium nitride-based compound semiconductor ® laminate according to any one of items 1 to 3 above, wherein the thickness of the well layer having a uniform thickness is 1.8 to 5 nm. (5) The gallium nitride-based compound semiconductor laminate according to any one of the items 1 to 4, wherein the film thickness of the thin film portion of the well layer having a thickness unevenness is 2.7 nm or less. (6) The gallium nitride-based compound semiconductor laminate according to any one of items 1 to 5 above, wherein the multiple quantum well structure has a structure in which the well layer and the barrier layer are formed by 3 to 10 times. (7) The gallium nitride-based compound semiconductor laminate according to any one of items 1 to 6, wherein the barrier layer is formed from a group of InGaN having a ratio of In which is smaller than InGaN forming GaN, AlGaN, and a well layer. A gallium nitride-based compound semiconductor is selected. (8) The gallium nitride-based compound semiconductor laminate of the above item 7, wherein the barrier layer is GaN. (9) The gallium nitride-based compound semiconductor laminate according to any one of the items 1 to 8, wherein the barrier layer is a dopant. (10) The gallium nitride-based compound semiconductor laminate according to the above item 9, wherein the dopant in 1304275 is from C, Si, Ge, Sn 'Pb, 〇, S, Se, Te, Po, Be, Mg, At least one selected from the group consisting of Ca, Sr, Ba, and Ra. (1) A gallium nitride-based compound semiconductor laminate according to the above item 9 or 10, wherein the concentration of the dopant is 1 X 1 〇 17 c π Γ 3 to 1 X 1 〇 18 c η Γ 3. The gallium nitride-based compound semiconductive volume layer according to any one of the above items 1 to 11, wherein the barrier layer has a film thickness of 7 to 50 nm. (1) The gallium nitride-based compound semiconductor laminate of the above item 1, wherein the barrier layer has a film thickness of 14 nm or more. (1) The gallium nitride-based compound semi-volume layer of any one of the above items 1 to 3, wherein the well layer contains In. (1) The gallium nitride-based compound semiconductor laminate according to the above item 14, wherein a thin layer not containing In is present on at least the substrate side surface of the barrier layer. (16) A forbearing grafting compound semiconductor light-emitting device, characterized in that: the n-type layer of the gallium nitride-based compound semiconductor laminate according to any one of the above items 1 to 5 is provided with a negative electrode, and is p-type The layer is set to the positive pole. (17) A lamp used in which the gallium nitride-based compound semiconductor light-emitting device of the above-mentioned item 16. (18) A method for producing a gallium nitride-based compound rich volume layer according to any one of the above items (15), characterized in that, after forming a well layer, by making the part of the well layer Decompose or sublimate to form a well layer with uneven thickness. (19) The method for producing a gallium nitride-based compound semiconductor laminate according to the above item 18, wherein a substrate temperature Τ 1 when the well layer is formed and a substrate temperature Τ 2 when the portion of the well layer is decomposed or sublimated are Ϊ́ΐ$Τ2. The method for producing a gallium nitride-based compound semiconductor layer according to the above item 18 or 19, wherein the decomposition or sublimation of the portion of the well layer is contained in a nitrogen source and is not contained The Group III metal source is operated under a gaseous environment. (2) The method for producing a gallium nitride-based compound semiconductor laminate according to any one of the above-mentioned items 18 to 20, wherein the decomposition or sublimation of the portion of the well layer is performed in the step of forming the barrier layer . The main structure of the present invention is to mix a well layer having a non-uniform thickness and a well layer having a uniform thickness in a well-layered layer of a multi-layer quantum structure forming a light-emitting layer, and the root B can obtain a good light-emitting output according to the present invention. Further, the gallium nitride-based compound semiconductor light-emitting device can reduce the driving voltage. Further, the gallium nitride-based compound semiconductor light-emitting device obtained according to the present invention has less deterioration in the reverse direction withstand voltage characteristics. Further, by forming a well layer having a thickness unevenness in the presence of a nitrogen source, it is possible to prevent the short-wavelength of light generated from the well layer. [Embodiment] It is known that a gallium nitride-based compound semiconductor constituting an n-type layer, a luminescent layer, and a bismuth layer of a gallium nitride-based compound semiconductor light-emitting device is of the general formula AlxInyGai-x.yN (0Sx<1, 〇 $y<1, 〇Sx + y<1) A semiconductor of various compositions represented by the present invention, and the gallium nitride-based compound semiconductor constituting the n-type layer, the light-emitting layer, and the bismuth layer of the present invention can be used without any limitation A semiconductor of various compositions represented by the general formula AlxInyGai-x-yN (0S x < 1, 〇$ y < 1, OS x + y < 1). As the substrate, a conventionally known substrate such as GaP, GaAs, Si, Zn or GaN can be used without any limitation except for using sapphire or SiC. -10- 1304275 In addition to the GaN substrate, in principle, in order to laminate a gallium nitride-based compound semiconductor on the substrates which are not lattice-integrated with the gallium nitride-based compound, Japanese Patent No. 3026087, A lattice unconformed crystal epitaxial growth technique called SP (Seeding Process), which is disclosed in Japanese Laid-Open Patent Publication No. H03-243302, and the like. In particular, the S P method for producing an A1N crystal film at a high temperature to the extent that GaN-based crystals can be produced is a lattice inhomogeneous crystal epitaxial growth technique which is excellent in terms of productivity and the like. In the case of using a lattice unconformed crystal epitaxial growth technique such as a low-temperature buffer method or an SP method, a gallium nitride-based compound semiconductor laminated thereon as a substrate is undoped or low in the range of 5×1 017 cm·3. Doped GaN is preferred. The film thickness of the substrate layer is preferably from 1 to 20 // m, more preferably from 5 to 15 // m. An n-type layer, a light-emitting layer, and a p-type layer are sequentially laminated thereon. In the present invention, the well layer of the multilayer quantum structure forming the light-emitting layer is required to mix the well layer having a uniform thickness and the well layer having a small thickness. In the present invention, "even thickness" means that the film thickness falls within ±10% of the average film thickness at any point. Among them, it is preferable to fall within ±7 %. "Uneven thickness" means a portion having a film thickness that does not fall within ±10% of the average film thickness. The "average film thickness" means the film thickness calculated by averaging the maximum film thickness and the minimum film thickness of the film. In the well layer having uneven thickness, a portion thicker than the average film thickness is referred to as a "thick film portion", and a portion called a thin portion is a "thin film portion". Whether the thickness of each of the well layers is uniform or uneven can be determined and measured by a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semiconductor. For example, when the cross-section is observed from 200,000 to 2,000,000 times of ΤΕΜ photos, the film thickness of each well layer can be measured -11 - 1304275 '. The third to tenth figures show the film thickness by the cross-sectional TEM photograph of the magnification of 1,000,000 times the wafer produced by the first method, and the magnification. The maximum film thickness and minimum film thickness of each well layer in the table attached to the side of each figure are attached. The maximum film thickness and the minimum film thickness of each well layer obtained from the eight figures are the well-thickness of the well layer or the uneven thickness of the well calculated by the average calculation of the maximum film thickness and the minimum film thickness. The average film thickness is divided into a thick film portion, and the thinner portion is a thin film portion. In the figure, A is ® B for the film portion. The maximum film thickness and the minimum film thickness of each well layer are obtained by observing at least 8 locations of the TEM facets, for example, at least 8 intervals from the adjacent spaces. In the case of unevenness in all wells in the multiple quantum well structure in which the light-emitting layer is formed, and in the case where the thickness is uniform in all the well layers, although the driving voltage is lowered, the light-emitting output is also decreased or the same. When the thickness of all the well layers is not made uneven, and the well layer is made uniform, although the reason is not sufficiently understood, the dynamic voltage is lowered and the luminous output is increased. In particular, in the case where the thickness of the well layer of the outermost layer or the η-type layer is uniform, the light-emitting effect is large. In the case where the thickness of both the well layer closest to the p-type layer and the most well-layered well layer is uniform, the luminous output effect is maximized, but the driving voltage reduction effect is also reduced. A well-balanced well layer' may include both wells closest to the p-type layer being close to the n-type layer of the well layer, but including one of the well layers having a uniform thickness, especially including the closest p-type Layer 1 embodiment piece. Can test, record the combination of these, can determine the household level. Compared with the thicker part of the film, it is possible to use the 20 μm layer to compare the thickness. However, when one part has the increase of the near-P-type output, the increase is close to the η-type. Therefore, the thick layer And most preferred. It is better to use the well floor 1304275. - When the number of wells with a uniform thickness increases, the effect of reducing the drive voltage will be reduced by >. Therefore, it is preferable that the number of well layers having a uniform thickness is 1 or more and 60% or less of the total number of the well layers. In particular, less than 40% of the total number of wells is preferred. It is preferred that the thickness of the well layer having a uniform thickness is 1.8 to 5 nm. When it is outside the range, it will cause a decrease in the light output. More preferably, it is in the range of 2.0 to 3.5 nm. > It is preferable that the thickness of the thick film portion of the well layer having a small thickness is 1.8 to 5 nm. When the thick film portion is outside the range, the light output is lowered. More preferably in the range of 2.3 to 3.5 nm. Further, it is preferable that the thickness of the thick film portion is 10 to 5000 nm. More preferably 20~lOOOnm. It is preferable that the ratio of the thick film portion is 30 to 90% with respect to the entire well layer, which can achieve both a reduction in driving voltage and an increase in output. More preferably 60 to 90%. The ratio of the thick film portion to the thin film portion can also be calculated from the measurement 値 of the width obtained from the cross-sectional TEM photograph. It is preferable that the width of the thin 0 portion is 1 to 200 nm. More preferably, it is 5 to 150 nm. It is preferable that the difference between the maximum film thickness of the thick film portion and the minimum film thickness of the thin film portion is about 1 to 3 nm. The film thickness of the film portion is preferably i.o to 27 nm. The thin film portion may include a range in which the film thickness is zero, that is, a range in which the well-free layer is completely omitted. However, since the light output is lowered, it is preferable that the film portion has a small range. The overall well layer is preferably 30% or less, more preferably 20% or less, and more preferably 1% or less. This ratio can be calculated from the measurement of the width of the cross-sectional TEM photograph -13 - 1304275. The well layer is preferably a gallium nitride-based compound semiconductor containing In. The gallium nitride-based compound semiconductor containing In is likely to be a crystal system having a structure of a thick film portion and a thin film portion, and can emit light in a wavelength region of blue light with strong luminescence intensity. In addition to GaN or AlGaN, the barrier layer may be formed of InGaN having a smaller In ratio than the InGaN constituting the well layer. Among them, GaN is more suitable. The barrier layer may also be a multi-layered construction. In the case where the well layer is a gallium nitride-based compound semiconductor containing In, it is preferable to provide a thin layer not containing In on the surface of the barrier layer which is at least in contact with the well layer on the substrate side. It is preferable to suppress the decomposition and sublimation of In in the well layer by providing the thin layer, so that stable control of the emission wavelength is possible. The thin layer is preferably set to a substrate temperature which is the same as the growth temperature of the well layer. When a dopant is doped into the barrier layer, the driving voltage is lowered to be preferable. Examples of the dopant element include C, Si, Ge, Sn, Pb, yttrium, S, Se, Te, Po, Be, Mg, Ca, Sr, Ba, Ra, and the like. Among them, Si and Ge are preferred, and Si is particularly preferred. The concentration of the dopant is preferably 5xl016cm_3~lxl018cm.3. If it is less than 5x10 16cnT3, the effect of reducing the driving voltage will be reduced. When it exceeds lxl018cirT3, the reverse voltage characteristic tends to be deteriorated. More preferably lxl017cm_3 ~ 5xl 〇 17cm_3. The film thickness of the barrier layer is preferably 7 n m or more, and more preferably 1 4 n m or more. When the film thickness of the barrier layer is thin, the thickness difference between the thick film portion and the film portion of the well layer cannot be completely filled, which hinders the formation of the thick film portion of the well layer and the film-14-8' 1304275 portion, thereby causing A decrease in luminous efficiency and a decrease in aging characteristics. • In addition, when the film thickness of the barrier layer is too thick, the driving voltage is increased and the light output is lowered. Therefore, the film thickness of the barrier layer is preferably 50 nm or less. The number of layers of the multiple two-well structure is preferably 3 to 10 times, more preferably 3 to 6 times. In each of the well layers and the barrier layer, the composition and structure can also be changed. The n-type layer is usually 1 to 10 / / m, preferably 2 to 5 / / m, and the n-contact layer for forming a negative electrode and the band gap are larger than the light-emitting layer and are in contact with the light-emitting layer. The cover layer is composed of. The η contact layer and the η coating layer may also be used in combination. It is preferred that the η contact layer is doped with Si or Ge at a high concentration. It is preferable to dope the n-type layer formed by the dopants so as to adjust the carrier concentration to 5x1OI8cm·3 to 2xl019cnT3. The η coating layer may be formed of AlGaN, GaN, InGaN or the like. However, in the case of InGaN, it is preferable to form a composition having a larger band gap than InGaN of the light-emitting layer. The carrier concentration of the η coating layer can be the same as that of the n contact layer, and ® can be larger or smaller than it. In order to further improve the crystallinity of the light-emitting layer formed thereon, it is preferred to form a surface having a high flatness by appropriately adjusting growth conditions such as growth rate, growth temperature, growth pressure, and doping amount. Further, the η coating layer may be formed by a layer having a laminated composition and a lattice constant differently. At this time, in addition to changing the composition by the layer of the layer, the amount of the dopant, the film thickness, and the like can be changed. The ruthenium layer is usually a thickness of 0.01 to 1/m, and is composed of a P-coat layer which is in contact with the light-emitting layer and a P-contact layer which forms a positive electrode. The p-coat layer and the p-contact 1304275 touch layer can also be used. The P-cladding layer is formed using GaN, AlGaN, or the like, and 'doped Mg' as a p-dopant. In order to prevent excessive flow of electrons, it is preferable to form a material having a band gap larger than that of the material of the light-emitting layer. Further, it is preferable to form a layer having a high carrier concentration in such a manner that the carrier can be efficiently injected into the light-emitting layer. The P-cladding layer can also be formed by using a layer having a plurality of layers and a different lattice constant. At this time, in addition to changing the composition by the layer of the layer, the amount of the dopant, the film thickness, and the like can be changed. The t P contact layer can be formed using GaN, AlGaN, In GaN, or the like, and doped
Mg作爲雜質。摻雜有Mg之氮化鎵系化合物半導體,通常 在從反應爐取出的原狀態下爲高電阻,但利用施以退火處 理、電子線照射處理、微波照射處理等活性化處理,而顯 示P傳導性。 另外’亦可使用摻雜有P型雜質之磷化硼來作爲P接觸 層。摻雜有P型雜質之磷化硼,即使完全不進行如上述之 P型化用的處理,仍顯示P導電性。 構成該些η型層、發光層及p型層之氮化鎵系化合物半 導體的生長方法,並無特別的限定,可以周知條件來使用 ΜΒΕ、MOCVD、HVPE等的周知方法。其中以MOCVD法爲 較佳。 可於原料中使用氨、聯氨、疊氮化物等。另外,可使用 三甲鉀(TMGa)、三乙鉀(TEGa)、三甲銦(TMIn)、三甲鋁 (ΤΜΑ1)等作爲III族有機金屬。另外,可使用矽烷、乙矽烷、 鍺院、有機鍺原料、雙環戊二烯鎂(Cp2Mg)、其他有機金屬 -16- •1304275 類、氫化物等作爲摻雜源。可將氮氣及氫氣用於運載氣體。 厚度不勻之井戶層,係以在使井戶層生長至指定厚度 後,藉由使其一部分分解或昇華所形成爲較佳。含In之氮 化鎵系化合物半導體,容易分解或昇華,故而較佳。 含In之井戶層的生長,係以在將基板溫度爲650〜900°C 之範圍進行爲較佳。在其以下之溫度下,無法獲得結晶性 良好之井戶層,在其以上之溫度下,取入井戶層之In量減 少,而有無法製作使意圖的波長發光之元件的情況。 在一面供給含In之III族金屬源及氮源,一面將由含In 之氮化鎵系化合物半導體所構成的井戶層生長爲指定厚度 後,在停止III族金屬源之供給的狀態下,藉由使基板溫度 維持原有溫度或昇溫,可使其一部分分解或昇華。運載氣 體係以氮氣爲較佳。分解或昇華係以將基板溫度從上述生 長溫度昇溫至700〜1 000°C之範圍或一面昇溫一面進行爲 較佳。 障壁層之生長係以比井戶層的生長更高之基板溫度來進 行爲較佳。該溫度區域適宜爲700〜1 000 °C,且當設使井戶 層生長之溫度爲T1、使障壁層生長之溫度爲T2時,則 T1 S T2。在井戶層之生長後,從T1至T2的昇溫過程,利 用包含一面繼續含氮之運載氣體及氮源的供給,一面停止 III族原料之供給的步驟,可於井戶層有效地形成厚膜部及 薄膜部,而可作成厚度不勻之井戶層。此時,無需改變運 載氣體等。將運載氣體切換爲氫氧,可使發光波長成爲短 波長化。波長之變化程度較難控制,所以使得製品之生產 1304275 ~ 性降低。 ‘ 從T1至T2的昇溫速度,以1〜200°c /分爲較佳。更以5 . 〜15(TC /分爲較佳。另外,從T1至T2的昇溫所需時間, 以30秒至10分鐘爲較佳。更以1分種至5分鐘爲較佳。 障壁層之生長,可在生長溫度不同之複數個步驟來構 成。即,在井戶層上以T2之溫度且將障壁層積層爲指定膜 厚後,亦可將生長溫度作爲T3進一步來積層障壁層。當 T3爲比T2更低之溫度時,可提供抑制老化特性的劣化等 ® 的效果,而更佳。T3亦可爲與T1相同之溫度。 另外,如上述,在含In之井戶層的情況,雖以在障壁層 之基板側表面設置未含In的薄層爲較佳,但該情況下,在 以溫度T 1使含In之氮化鎵系化合物半導體所構成的井戶 層生長後,亦可以相同之基板溫度僅停止In源的供給,並 以溫度T1首先使由氮化鎵系化合物半導體所構成的障壁 層生長。 有關負極,周知有各種組成及構造的負極,可無任何限 ^ 制地使用該些周知的負極。與η接觸層相接之負極用的接 觸材料,除Al、Ti、Ni、Au等外,可使用Cr、W、V等。 當然亦可將負極整體作爲多層構造並賦予搭接性等。 有關正極,周知有各種組成及構造的正極,可無任何限 制地使用該些周知的正極。 透光性的正極材料,可包含p t、p d、A u、C r、N i、C u、 C 〇等。另外,已知利用作成使其一部分氧化的構造,可提 高透光性。反射型之正極材料,除上述材料外,可使用Rh、 -18- .1304275Mg acts as an impurity. The gallium nitride-based compound semiconductor doped with Mg is usually high-resistance in the original state taken out from the reaction furnace, but is subjected to an activation treatment such as annealing treatment, electron beam irradiation treatment, or microwave irradiation treatment to display P conduction. Sex. Alternatively, boron phosphide doped with a P-type impurity may be used as the P-contact layer. Phosphorus phosphide doped with a P-type impurity exhibits P conductivity even if the treatment for P-type as described above is not performed at all. The method for growing the gallium nitride-based compound semiconductor constituting the n-type layer, the light-emitting layer, and the p-type layer is not particularly limited, and known methods such as ruthenium, MOCVD, and HVPE can be used under known conditions. Among them, the MOCVD method is preferred. Ammonia, hydrazine, azide, or the like can be used as the raw material. Further, potassium trichloride (TMGa), triethylpotassium (TEGa), trimethylindium (TMIn), trimethylaluminum (ΤΜΑ1) or the like can be used as the group III organic metal. Further, as a doping source, decane, acetane, brothel, organic ruthenium raw material, dicyclopentadienyl magnesium (Cp2Mg), other organometallic-16- • 1304275 type, hydride or the like can be used. Nitrogen and hydrogen can be used to carry the gas. The well layer having a non-uniform thickness is preferably formed by causing a portion of the well layer to be decomposed or sublimated after it has been grown to a specified thickness. The gallium nitride-based compound semiconductor containing In is preferred because it is easily decomposed or sublimated. The growth of the well layer containing In is preferably carried out at a substrate temperature of 650 to 900 °C. At the temperature below, the well layer having good crystallinity cannot be obtained, and at the temperature above, the amount of In taken into the well layer is reduced, and there is a case where it is impossible to produce an element that emits light at an intended wavelength. After supplying a group of metal containing a source of In and a source of nitrogen to one side, a well layer composed of a gallium nitride-based compound semiconductor containing In is grown to a predetermined thickness, and then the supply of the group III metal source is stopped. A part of the substrate can be decomposed or sublimated by maintaining the substrate temperature at the original temperature or increasing the temperature. The carrier gas system is preferably nitrogen. Decomposition or sublimation is preferably carried out by raising the temperature of the substrate from the growth temperature to a range of 700 to 1 000 °C or while raising the temperature. The growth of the barrier layer is preferably performed at a higher substrate temperature than the growth of the well layer. The temperature region is suitably 700 to 1 000 °C, and when the temperature at which the well layer is grown is T1 and the temperature at which the barrier layer is grown is T2, then T1 S T2. After the growth of the well layer, the step of stopping the supply of the group III raw material by the supply of the carrier gas and the nitrogen source containing the nitrogen gas from the temperature rising process of T1 to T2 can effectively form the thick layer in the well layer. The film portion and the film portion can be formed into a well layer having a non-uniform thickness. At this time, it is not necessary to change the carrier gas or the like. By switching the carrier gas to hydrogen and oxygen, the emission wavelength can be shortened. The degree of change in wavelength is difficult to control, so the production of the product is reduced to 1304275. ‘ The temperature increase rate from T1 to T2 is preferably 1 to 200 ° C /. Further, it is preferably 5. 5 / TC (TC / is divided. Further, the time required for the temperature rise from T1 to T2 is preferably 30 seconds to 10 minutes, more preferably 1 minute to 5 minutes. The growth can be carried out in a plurality of steps having different growth temperatures. That is, after the barrier layer is formed to a predetermined thickness on the well layer at a temperature of T2, the growth temperature can be further increased as a T3 layer. When T3 is a temperature lower than T2, it is preferable to provide an effect of suppressing degradation of aging characteristics, etc., and T3 may be the same temperature as T1. Further, as described above, in the well layer containing In In the case where a thin layer containing no In is provided on the substrate side surface of the barrier layer, in this case, after the well layer composed of the gallium nitride-based compound semiconductor containing In is grown at the temperature T 1 , In addition, the supply of the In source may be stopped at the same substrate temperature, and the barrier layer made of the gallium nitride-based compound semiconductor may be first grown at the temperature T1. The negative electrode is known to have various compositions and structures. ^ These well-known negative electrodes are used in the system. Contact layer with η In addition to Al, Ti, Ni, Au, etc., Cr, W, V, etc. may be used as the contact material for the negative electrode. The entire negative electrode may have a multilayer structure and may be provided with a lap bond property or the like. The positive electrode of various compositions and structures can be used without any limitation. The light-transmitting positive electrode material may include pt, pd, A u, C r, N i, C u, C 〇, etc. It is known that a structure which is partially oxidized can be used to improve light transmittance. A reflective type positive electrode material can be used in addition to the above materials, Rh, -18-.1304275
Ag 、 A1 等。 • 該些正極可由濺鍍、真空蒸鍍等的方法所形成。尤其是 、 當使用濺鍍法時,利用適宜控制濺鍍的條件,在形成電極 膜後,即使不施以退火處理仍可獲得歐姆接觸,故而較佳。 發光元件之構造可爲具備反射型之正極的倒裝片型的元 件,亦可爲具備透光型之正極、晶格型、梳型之正極的面 朝上型的元件。 在具有厚膜部及薄膜部之厚度不勻的井戶層中,在從厚 B 膜部變爲薄膜部的境界區域,材料不同之井戶層及障壁層 的界面相對基板面形成傾斜,所以朝垂直於基板面之方向 的光的取出量增大,尤其是藉由作成具備反射電極之倒裝 片型的元件構造,可進一步增大發光強度。 藉由使用本發明之氮化鎵系化合物半導體積層物,可使 驅動電壓自由下降某一程度。但是,若電壓下降太多時, 隨之亦會看到發光輸出的降低。未引起發光輸出降低之驅 動電壓,係以在作成元件時流動20mA之電流時的電壓爲 B 2 · 5 V以上爲較佳、更以2 · 9 V以上爲較佳。但是,在組入裝 置時,電壓過高之情況將會造成不利,所以同時需要爲3 .5 V 以下。 使用本發明之氮化鎵系化合物半導體積層物的效果,在 屬二極體特性之一的電流及電壓的相關中,可舉出電流相 對電壓作急遽上昇的牽引電壓被降低的情況。但是,有關 牽引電壓亦是,若下降過多時,會看到發光輸出的降低。 未引起發光輸出降低之牽引電壓,以在作成元件時流動 S) -19- 1304275 2 0mA之電流時的電壓爲2.3V以上爲較佳、更以2.5V以上 爲較佳。但是,在組入裝置時,電壓過高之情況將會造成 不利,所以同時需要爲3.4V以下。 可將本發明之氮化鎵系化合物半導體積層物,用於發光 二極體、雷射二極體等之製作。 從本發明之氮化鎵系化合物半導體積層物來製作半導體 發光元件’例如,可藉由業界周知的手段設置透明罩來製 作燈。另外’使本發明之氮化鎵系化合物半導體發光元件 及具有螢光體之罩體組合,亦可製作白光的燈。 進而可獲得高發光強度之氮化鎵系化合物半導體發光元 件。根據該方法可製造高亮度之LED燈。更且,組入根據 該方法所製成之晶片之行動電話、顯示器、面板類等的電 子機器、組入該電子機器之汽車、電腦、遊戲機等之機械 裝置,可達成低電力的驅動、實現高的特性。尤其是,在 行動電話、遊戲機、汽車零件等之電池驅動的機器類中, 可發揮省電力之效果。 (實施例) 其次,根據實施例詳細說明本發明,但本發明並不受該 些實施例所限制。 (第1實施例) 第1圖爲由本實施例所製作之半導體元件用之氮化鎵系 化合物半導體積層物的模式圖(但是,省略發光層之井戶層 及障壁層)。如第1圖所示,在具有C面之藍寶石基板上, 藉由晶格不整合結晶之磊晶生長方法來積層由A1N構成的 -20- 1304275 ~ s P層,並於其上從基板側依序積層厚度爲8 // m的無摻雜 • GaN襯底層、具有約lxl019cnT3之電子濃度且厚度爲2/zm . 的高摻雜Ge的η型GaN接觸層、具有約ixi〇i8cm·3之電子 濃度且厚度爲20nm的摻雜Si的η型111。.〇2〇3。.98覆被層、 由6層之厚度爲15nm的3xl017cm·3之摻雜Si的GaN障壁 層及5層之厚度爲3nm的無摻雜的In 〇.〇 8Ga。.9 2N之薄層所構 成的井戶層所構成的多重量子井構造的發光層、厚度爲 16nm 之摻雑 Mg 的 ρ 型 Al0.05Ga0.95N 覆被層、具 8xl017cm·3 B 之電洞濃度的厚度爲0.2 // m的摻雜Mg的p型Al〇.〇2Ga〇.98N 接觸層的構造。 上述氮化鎵系化合物半導體積層物的製作,係使用 MOCVD法、並依以下的步驟所進行。 首先,將藍寶石基板導入可處理由感應加熱式加熱器來 加熱碳製承受器的形式之多片基板的不鏽鋼製反應爐中。 承受器係具有本身旋轉的機構、及使基板自轉的機構.。藍 寶石基板係在已經交換爲氮氣的球形盒中,載置於加熱用 1 的碳製承受器上。在導入試樣後,使氮氣流通而將反應爐 內純化。 在使氮氣流通而達8分鐘後,令感應加熱式加熱器作 動,並經過10分鐘而使基板溫度昇溫爲600 °C後,同時令 爐內之壓力成爲15kPa(150mbar)。在將基板溫度保持爲 6 00 °C的狀態下,一面使氫氣及氮氣流通,一面放置2分鐘’ 進行基板表面之加熱清潔。 在完成加熱清潔後,將氮氣之運載氣體的閥加以關閉’ -21 - 1304275 ' 僅對反應爐內供給氫氣。 • 在運載氣體之切換後,使基板之溫度昇溫爲1150 °C。在 • 確認溫度已穩定在1 150°C後,切換TMA1之配管的閥,將 含有TMA1之蒸氣的氣體供給反應爐內,使其與附著於反 應爐內壁之附著物的分解而產生之N原子反應,開始使A1N 附著於藍寶石基板上的處理。 在經過7分30秒的處理後,切換TMA1之配管的閥,停 止將含有TMA1之蒸氣的氣體供給反應爐內。在此狀態下 B 待機4分鐘,等待至殘留於爐內之TMA1蒸氣被完全排出。 接著,切換氨氣之配管的閥,開始對爐內供給氨氣。 經過4分鐘後,一面繼續氨氣之流通,一面使基板溫度 降溫至1 040°C,同時令爐內之壓力爲40kPa(400mbar)。在 基板溫度之降溫中,調節TMGa之配管的流量調整器的流 量。 在確認到基板溫度成爲1040 °c後,等待溫度之穩定,隨 後切換TMGa之閥,開始將TMGa供給爐內,開始無摻雜 B GaN的生長,約花費4小時進行上述GaN層的生長。 如此般,形成具有約8 // m之膜厚的無摻雜GaN襯底層。 更且,在該無摻雜GaN襯底層上’使高摻雜Ge之η型 GaN接觸層生長。在無摻雜GaN襯底層之生長後,停止將 TMGa供給爐內,其後以一分鐘使基板溫度昇溫爲1 0 80°C, 並保持3分鐘以使溫度穩定。在該期間調節TMGe之流通 量。而所流通之量係經事先檢討’而調整成爲摻雜Ge之 GaN接觸層的電子濃度約爲2x1 (T9cirT3。氨氣係以其原來的Ag, A1, etc. • These positive electrodes can be formed by methods such as sputtering, vacuum evaporation, and the like. In particular, when the sputtering method is used, it is preferable to obtain an ohmic contact after forming the electrode film without performing annealing treatment by appropriately controlling the conditions of the sputtering. The structure of the light-emitting element may be a flip-chip type element having a reflective positive electrode, or may be a face-up type element having a light-transmitting positive electrode, a lattice type, and a comb-type positive electrode. In the well layer having the thick film portion and the thickness of the thin film portion, the interface between the well layer and the barrier layer having different materials is inclined with respect to the substrate surface in the boundary region from the thick B film portion to the thin film portion, so The amount of light taken out in the direction perpendicular to the substrate surface is increased, and in particular, by forming a flip-chip type element structure including the reflective electrode, the light emission intensity can be further increased. By using the gallium nitride-based compound semiconductor laminate of the present invention, the driving voltage can be freely lowered to some extent. However, if the voltage drops too much, you will see a decrease in the luminous output. The driving voltage at which the light output is not lowered is preferably a voltage of B 2 · 5 V or more, more preferably 2 · 9 V or more, when a current of 20 mA flows when the element is formed. However, when the device is incorporated, the voltage is too high, which is disadvantageous, so it needs to be less than 3.5 V. The effect of using the gallium nitride-based compound semiconductor laminate of the present invention is a case where the current and the voltage which are one of the characteristics of the diode are related to each other, and the traction voltage in which the current is relatively increased with respect to the voltage is lowered. However, the relevant traction voltage is also such that if the drop is too much, the luminous output is reduced. The traction voltage which does not cause a decrease in the light-emitting output is preferably a voltage of 2.3 V or more when flowing a current of S) -19 - 1304275 2 0 mA when the component is formed, and more preferably 2.5 V or more. However, when the device is incorporated, the voltage is too high, which is disadvantageous, so it needs to be 3.4V or less at the same time. The gallium nitride-based compound semiconductor laminate of the present invention can be used for production of a light-emitting diode, a laser diode, or the like. A semiconductor light-emitting device is produced from the gallium nitride-based compound semiconductor laminate of the present invention. For example, a transparent cover can be provided by a means known in the art to produce a lamp. Further, a combination of the gallium nitride-based compound semiconductor light-emitting device of the present invention and a cover having a phosphor can also produce a white light lamp. Further, a gallium nitride-based compound semiconductor light-emitting device having high luminous intensity can be obtained. According to this method, a high-intensity LED lamp can be manufactured. Furthermore, an electronic device such as a mobile phone, a display, a panel, or the like incorporated in a wafer produced by the method, a mechanical device such as a car, a computer, or a game machine incorporated in the electronic device can be incorporated, and low-power driving can be achieved. Achieve high features. In particular, in battery-operated devices such as mobile phones, game consoles, and automobile parts, power saving effects can be achieved. (Embodiment) Next, the present invention will be described in detail based on examples, but the present invention is not limited by the examples. (First Embodiment) Fig. 1 is a schematic view showing a gallium nitride-based compound semiconductor laminate for a semiconductor device produced in the present embodiment (however, the well layer and the barrier layer of the light-emitting layer are omitted). As shown in Fig. 1, on the sapphire substrate having a C-plane, a layer of -20-1304275 to s P composed of A1N is laminated by an epitaxial growth method of lattice unconformity crystallization, and on the substrate side from above An undoped GaN substrate layer having a thickness of 8 // m, a highly doped Ge-type n-type GaN contact layer having an electron concentration of about 1×10 019 T3 and a thickness of 2/zm, having an ixi〇i8 cm·3 layer The Si-doped n-type 111 having an electron concentration and a thickness of 20 nm. .〇2〇3. The .98 coating layer, a 6-layer layer of a 3xl017cm·3 doped Si GaN barrier layer having a thickness of 15 nm, and 5 layers of an undoped In 〇.〇 8Ga having a thickness of 3 nm. .9 A light-emitting layer of a multi-quantum well structure composed of a well layer composed of a thin layer of 2N, a p-doped Mg-type ρ-type Al0.05Ga0.95N coating layer having a thickness of 16 nm, and a hole having 8xl017cm·3 B The concentration of the 0.2 m thick doped Mg p-type Al〇.〇2Ga〇.98N contact layer structure. The gallium nitride-based compound semiconductor laminate was produced by the MOCVD method in the following procedure. First, a sapphire substrate is introduced into a stainless steel reactor which can process a plurality of substrates in the form of a carbon heater by an induction heating heater. The susceptor has a mechanism for rotating itself and a mechanism for rotating the substrate. The sapphire substrate is placed in a spherical box that has been exchanged for nitrogen and placed on a carbon susceptor for heating 1. After the sample was introduced, nitrogen gas was passed through to purify the inside of the reactor. After circulating nitrogen gas for 8 minutes, the induction heating heater was operated, and after the substrate temperature was raised to 600 °C over 10 minutes, the pressure in the furnace was 15 kPa (150 mbar). While the substrate temperature was maintained at 600 ° C, hydrogen gas and nitrogen gas were allowed to flow while being left for 2 minutes to heat and clean the surface of the substrate. After the heating and cleaning is completed, the valve of the carrier gas of nitrogen is turned off ' -21 - 1304275 ' Only hydrogen is supplied to the reactor. • After the carrier gas is switched, the temperature of the substrate is raised to 1150 °C. After confirming that the temperature has stabilized at 1 150 °C, switch the valve of the piping of TMA1, and supply the gas containing the vapor of TMA1 to the reactor to cause decomposition with the deposit attached to the inner wall of the reactor. The atomic reaction begins the process of attaching A1N to the sapphire substrate. After 7 minutes and 30 seconds of treatment, the valve of the piping of TMA1 was switched, and the gas containing the vapor of TMA1 was stopped from being supplied to the reaction furnace. In this state, B stands by for 4 minutes, and waits until the TMA1 vapor remaining in the furnace is completely discharged. Next, the valve of the piping of the ammonia gas is switched, and the supply of ammonia gas into the furnace is started. After 4 minutes, the flow of the ammonia gas was continued while the substrate temperature was lowered to 1,040 ° C while the pressure in the furnace was 40 kPa (400 mbar). The flow rate of the flow regulator of the TMGa piping is adjusted during the temperature drop of the substrate. After confirming that the substrate temperature became 1040 ° C, the temperature was stabilized, and then the TMGa valve was switched to start supplying TMGa into the furnace to start the growth of undoped B GaN, and it took about 4 hours to grow the GaN layer. In this manner, an undoped GaN substrate layer having a film thickness of about 8 // m is formed. Further, a highly doped Ge n-type GaN contact layer is grown on the undoped GaN substrate layer. After the growth of the undoped GaN substrate layer, the TMGa was stopped from being supplied into the furnace, and thereafter the substrate temperature was raised to 1,080 ° C in one minute, and held for 3 minutes to stabilize the temperature. The throughput of TMGe is adjusted during this period. The amount of electrons that are circulated is adjusted to become a Ge-doped GaN contact layer with an electron concentration of about 2x1 (T9cirT3. The ammonia system is based on its original
SJ -22- •1304275 ' 流量被繼續供給爐內。 • 在經3分鐘之溫度穩定後,依序交錯地使厚度爲1 〇nm之 * 摻Ge的η型GaN、及厚度爲i〇nm之無摻雜GaN的薄膜生 長100個周期,生長爲約2 /z m之η型GaN接觸層。摻Ge 的η型GaN層係利用將TMGa及三甲鍺(TMGe)供給爐內所 製作’而無摻雜GaN層係利用供給TMGa所製作而成。藉 此’形成平均載子濃度約爲1 X 1 〇 19 c ηΓ3的η型G a N接觸層。 在使最後之無摻雜GaN層生長後,切換TMGa的閥,停 B 止將TMGa供給爐內。氨氣係在原來狀態下一面流通,一 面切換閥而將運載氣體從氫氣切換爲氮氣。其後,將基板 溫度從1 080°C降溫至720。(:。 在等待爐內之溫度變更的期間,設定了 SiH4的供給量。 而所流通之量係經事先檢討,而調整成爲摻雜S i之η型 InGaN覆被層的電子濃度爲lxl〇18cnr3。氨氣係以其原來的 流量被繼續供給爐內。 其後,等待爐內之狀態成爲穩定,同時將TMIii、TEGa B 及SiH4之閥加以切換,開始將該些原料供給爐內。僅依指 定時間持續供給’形成具有20nm膜厚之摻雜si之 In〇.〇2Ga〇.98N覆被層。其後,將TMIn、TEGa及SiH4之閥加 以切換,以停止該些原料之供給。在停止原料之供給後, 改變S i Η 4之供給量的設定。而所流通之量係經事先檢討, 而調整成爲摻雜 Si之 GaN障壁層的電子濃度爲 3 X 1 0 M c ηΓ3。摻雜S i之G a N障壁層之形成係依如下來進行。 在基板溫度爲720°C的狀態下,開始將TEGa及SiHN供給 -23- 1304275 爐內,並依指定時間形成由摻雜S i之G a N所構成的薄層之 • 障壁層A,然後停止TEGa及SiH4之供給。其後,在中斷 .生長之狀態下將基板溫度昇溫爲920 °C。在溫度穩定後,爐 內之壓力、氨氣及運載氣體之流量、種類,係在該狀態下, 將TEGa及SiH4之閥加以切換,再度開始使TEGa及SiH4 對爐內之供給,並在該狀態下,在基板溫度920°C,進行規 定時間之障壁層 B的生長。接著,使基板溫度下降爲 720°C,並在該狀態下,繼續TEGa及SiH4之供給,在進行 > 障壁層C之生長後,再度將閥加以切換,使TEGa及SiH4 之供給停止,完成GaN障壁層的生長。藉此,在由A、B 及C構成之3層構造的障壁層形成總膜厚爲1 5 nm的摻雜 Si之GaN障壁層。 在GaN障壁層之生長完成後,經過30秒而停止TEGa及 SiH4之供給後,基板溫度、爐內之壓力、氨氣及運載氣體 之流量、種類,係在該狀態下,將TEGa及SiH4之閥加以 切換,將TEGa及SiHU供給爐內,以形成井戶層。在預先 B 決定之時間內進行TEGa及TMIn之供給後,再度將閥加以 切換,僅僅停止TMIn之供給,完成In〇.〇8Ga〇.92N井戶層的 生長。在該時點,形成成爲3nm之膜厚的In〇.〇8Ga〇.92N井戶 層。接著,再度開始SiH4之供給,進入第2層之障壁層的 形成。SJ -22- • 1304275 ' The flow is continued to be supplied to the furnace. • After stabilization for 3 minutes, a film of GaN-doped η-type GaN with a thickness of 1 〇 nm and undoped GaN with a thickness of i〇nm is grown in a staggered manner for 100 cycles. 2 / zm n-type GaN contact layer. The Ge-doped n-type GaN layer is produced by supplying TMGa and trimethylsulfonium (TMGe) into a furnace, and the undoped GaN layer is produced by supplying TMGa. By this, an n-type G a N contact layer having an average carrier concentration of about 1 X 1 〇 19 c η Γ 3 is formed. After the final undoped GaN layer is grown, the TMGa valve is switched and the TMGa is stopped to supply the TMGa to the furnace. The ammonia gas flows while flowing in the original state, and the valve is switched on one side to switch the carrier gas from hydrogen to nitrogen. Thereafter, the substrate temperature was lowered from 1,080 °C to 720. (: The amount of SiH4 supplied is set while waiting for the temperature change in the furnace. The amount of the flow is adjusted in advance, and the electron concentration of the n-type InGaN coating layer adjusted to be doped with S i is lxl〇 18cnr3. The ammonia gas is continuously supplied to the furnace at its original flow rate. Thereafter, the state in the furnace is stabilized, and the valves of TMIii, TEGa B and SiH4 are switched, and the raw materials are supplied to the furnace. The In〇.〇2Ga〇.98N coating layer having a doping of Si having a film thickness of 20 nm was continuously supplied for a predetermined period of time. Thereafter, the valves of TMIn, TEGa, and SiH4 were switched to stop the supply of the raw materials. After the supply of the raw material is stopped, the setting of the supply amount of S i Η 4 is changed. The amount of the flow is adjusted in advance, and the electron concentration of the GaN barrier layer doped with Si is adjusted to 3 × 10 M c η Γ 3 . The formation of the G a N barrier layer doped with S i is performed as follows: At a substrate temperature of 720 ° C, TEGa and SiHN are initially supplied into the -23 - 1304275 furnace, and doped by a specified time. a layer of S a G a N consisting of a barrier layer A, then The supply of TEGa and SiH4 is stopped. Thereafter, the substrate temperature is raised to 920 ° C in the state of interruption and growth. After the temperature is stabilized, the pressure in the furnace, the flow rate and type of the ammonia gas and the carrier gas are in this state. Next, the valves of TEGa and SiH4 are switched, and the supply of TEGa and SiH4 to the furnace is started again, and in this state, the growth of the barrier layer B is performed at a substrate temperature of 920 ° C for a predetermined period of time. The temperature is lowered to 720 ° C, and in this state, the supply of TEGa and SiH 4 is continued. After the growth of the barrier layer C is performed, the valve is again switched to stop the supply of TEGa and SiH 4 to complete the GaN barrier layer. Therefore, a Si-doped GaN barrier layer having a total film thickness of 15 nm is formed in a barrier layer of a three-layer structure composed of A, B, and C. After the growth of the GaN barrier layer is completed, 30 seconds elapses. After stopping the supply of TEGa and SiH4, the substrate temperature, the pressure in the furnace, the flow rate and type of the ammonia gas and the carrier gas are switched, and the TEGa and SiH4 valves are switched, and TEGa and SiHU are supplied to the furnace. Form a well floor. Determined in advance B After the supply of TEGa and TMIn is performed in between, the valve is switched again, and only the supply of TMIn is stopped, and the growth of the In〇.〇8Ga〇.92N well layer is completed. At this point, an In〇 which becomes a film thickness of 3 nm is formed. .〇8Ga〇.92N Wells layer. Then, the supply of SiH4 is started again, and the formation of the barrier layer of the second layer is entered.
反複進行此種步驟,形成5層之摻雜Si之GaN障壁層及 5層之In〇.〇8Ga〇.92N井戶層。在該些井戶層及障壁層之製作 步驟中,在720 °C形成障壁層A後,在爲了形成障壁層B -24 - 1304275 而昇溫爲9 2 0 °C之步驟中,藉由停止ΠI族原料的供給,將 半導體之生長加以中斷。 . 在形成第5層之In。·。8G a。· 92N井戶層後,接著,進入第6 層之障壁層的形成。在第6層之障壁層的形成中,再度開 始SiH4之供給,在形成由摻雜Si之GaN構成的薄辭之障 壁層A後,繼續對爐內供給TEGa及SiH4,使基板溫度昇 溫爲920°C,並在該狀態下,在基板溫度920°C,進行規定 時間之障壁層B的生長。接著,使基板溫度下降爲7 20。(:, > 並在該狀態下,繼續TEGa及SiH4之供給,在進行障壁層C 之生長後,再度將閥加以切換,使TEGa及SiH4之供給停 止,完成GaN障壁層的生長。藉此,在由A、B及C構成 之3層構造的障壁層形成總膜厚爲15nm的摻雜Si之GaN 障壁層。 藉由以上步驟,形成含有厚度不勻之井戶層(第1至4層) 及厚度均勻之井戶層(第5層)的多重量子井構造之發光層。 在完成該摻雜Si之GaN障壁層的發光層上,形成摻雜 _ Mg 之 p 型 Al〇.Q5Ga〇.95N 覆被層。 在使TEGa及SiH4之供給停止,而完成摻雜Si之GaN障 壁層的生長後,使基板溫度昇溫爲1 000 °C,將運載氣體之 種類切換爲氫氧,使爐內之壓力變更爲15kPa(150mba〇。 等待爐內之壓力穩定後,將TMGa、TMA1及CP2Mg之閥加 以切換,開始將該些原料供入爐內。其後,在經過約爲3 分鐘的生長後,使TEGa、TMA1及CP2Mg之供給停止,以 停止摻雜Mg之p型Al〇.〇5Ga〇.95N覆被層的生長。藉此,形 -25 - 1304275 成具有1 6nm之膜厚的摻雜Mg之p型Alo.^GamN覆被層。 •在該摻雜Mg之p型Ah.osGamN覆被層上’形成摻雜 • Mg 之 p 型 Al〇.〇2Ga〇.98N 接觸層。 在停止TMGa、TMA1及CPaMg之供給,而完成摻雜Mg 之Al〇.〇5Ga〇.95N覆被層的生長後,將爐內之壓力變更爲 20kPa(200mba〇。等待爐內之壓力穩定後,將TMGa、TMA1 及CP2Mg之閥加以切換,開始將該些原料供入爐內。而使 CP2Mg流通之量係經事先檢討,而調整成爲摻雜Mg之p型 t Al〇.〇2Ga〇.98N接觸層的電洞濃度爲8xl017cnT3。其後,在經 過約12分鐘的生長後,使TMGa、TMA1及CP2Mg之供給停 止,以停止摻雜Mg之p型Al〇.〇2Ga〇.98N接觸層的生長。藉 此,形成具有約0.2// m之膜厚的摻雜Mg之P型Al〇.〇2GaD.98N 接觸層。 在完成該摻雜Mg之p型Al〇.〇2Ga〇.98N接觸層之生長後, 停止對感應加熱式加熱器之通電,花費20分鐘將該基板溫 > 度降溫爲室溫。在該降溫中,僅由氮氣構成反應爐內之環 境氣體,其後,確認到基板溫度降溫至室溫後,將製作完 成之氮化鎵系化合物半導體積層物取出至大氣中。 藉由如上之步驟,製成半導體發光元件用之氮化鎵系化 合物半導體積層物。在此,摻雜Mg之p型Alo.wGaowN接 觸層,即使未進行使p型載子活性化用的退火處理仍顯示 爲P型。 其次,使用上述氮化鎵系化合物半導體積層物,來製成 屬半導體發光元件之一種的發光二極體。 -26- 1304275This step was repeated to form a 5-layer Si-doped GaN barrier layer and a 5-layer In〇.〇8Ga〇.92N well layer. In the manufacturing steps of the well layer and the barrier layer, after the barrier layer A is formed at 720 ° C, in the step of raising the temperature to 920 ° C for forming the barrier layer B -24 - 1304275, by stopping the ΠI The supply of the raw materials of the family interrupts the growth of the semiconductor. In the formation of the fifth layer of In. ·. 8G a. · After the 92N well layer, then proceed to the formation of the barrier layer of the sixth layer. In the formation of the barrier layer of the sixth layer, the supply of SiH4 is resumed, and after forming the barrier layer A composed of GaN doped with GaN, TEGa and SiH4 are continuously supplied to the furnace to raise the temperature of the substrate to 920. °C, and in this state, the growth of the barrier layer B is performed for a predetermined time at a substrate temperature of 920 °C. Next, the substrate temperature was lowered to 720. (:, > In this state, the supply of TEGa and SiH4 is continued, and after the growth of the barrier layer C is performed, the valve is again switched to stop the supply of TEGa and SiH4, thereby completing the growth of the GaN barrier layer. A Si-doped GaN barrier layer having a total film thickness of 15 nm is formed in a barrier layer of a three-layer structure composed of A, B, and C. By the above steps, a well layer having a thickness unevenness is formed (1st to 4th) a light-emitting layer of a multiple quantum well structure with a uniform thickness of the well layer (Layer 5). On the light-emitting layer of the Si-doped GaN barrier layer, a p-type Al〇.Q5Ga doped with Mg is formed. 〇.95N coating layer. After the supply of TEGa and SiH4 is stopped, and the growth of the Si-doped GaN barrier layer is completed, the substrate temperature is raised to 1 000 °C, and the type of carrier gas is switched to hydrogen and oxygen. The pressure in the furnace was changed to 15 kPa (150 mba.) After the pressure in the furnace was stabilized, the valves of TMGa, TMA1 and CP2Mg were switched, and the raw materials were started to be supplied into the furnace. Thereafter, after about 3 minutes passed, After growth, the supply of TEGa, TMA1 and CP2Mg is stopped to stop the doping of Mg-doped p-type Al 〇5Ga〇.95N coating growth. Thus, the shape -25304 is formed into a Mg-doped p-type Alo.^GamN coating layer having a film thickness of 16 nm. On the Ah.osGamN coating layer, a p-type Al〇.〇2Ga〇.98N contact layer is formed which is doped with Mg. The supply of TMGa, TMA1 and CPaMg is stopped, and Mg-doped Al〇.〇5Ga〇 is completed. After the growth of the .95N coating layer, the pressure in the furnace was changed to 20 kPa (200 mba.) After waiting for the pressure in the furnace to stabilize, the valves of TMGa, TMA1, and CP2Mg were switched, and the raw materials were started to be supplied into the furnace. The amount of CP2Mg circulating was previously reviewed, and the hole concentration of the p-type t Al〇.〇2Ga〇.98N contact layer doped with Mg was 8xl017cnT3. Thereafter, after about 12 minutes of growth, The supply of TMGa, TMA1, and CP2Mg is stopped to stop the growth of the Mg-doped p-type Al〇.〇2Ga〇.98N contact layer. Thereby, a Mg-doped P having a film thickness of about 0.2//m is formed. Type Al〇.〇2GaD.98N contact layer. After completing the growth of the Mg-doped p-type Al〇.〇2Ga〇.98N contact layer, the energization of the induction heating heater is stopped. The substrate temperature was lowered to room temperature for 20 minutes. In this cooling, only the ambient gas in the reaction furnace was made up of nitrogen gas, and then it was confirmed that the substrate temperature was lowered to room temperature, and the completed gallium nitride was formed. The compound semiconductor laminate is taken out to the atmosphere. By the above steps, a gallium nitride-based compound semiconductor laminate for a semiconductor light-emitting device is produced. Here, the p-type Alo.wGaowN contact layer doped with Mg exhibits a P-type even if an annealing treatment for activating the p-type carrier is not performed. Next, a gallium nitride-based compound semiconductor laminate is used to form a light-emitting diode which is one of semiconductor light-emitting elements. -26- 1304275
' 在所製成之氮化鎵系化合物半導體積層物的p型AlGaN * 接觸層之表面上,藉由業界周知之方法,製成具有從接觸 . 層側依序積層有Pt、Rh及Au的構造之反射性的正極。 其後,更於該氮化鎵系化合物半導體積層物上進行乾式 蝕刻,以使高摻雜Ge之η型GaN接觸層的負極形成部分 露出,於該露出部分從接觸層側依序積層Ti及A1而製成 負極。藉由該些作業,製成具有第2圖所示之形狀的電極。 有關如此般形成有正極及負極之氮化鎵系化合物半導體 > 積層物,將藍寶石基板之背面加以硏削、硏磨,而作成鏡 面狀的面。其後,將該氮化鎵系化合物半導體積層物,切 斷爲3 5 0 μ m角之正方形的各個晶片,並以電極向下的方式 配置於副固定板上。並將該副固定板載置於導線架上,以 金線連接於導線架而作成發光二極體。 當沿順方向使電流流動於如上述般製成之發光二極體的 正極及負極間時,電流爲20mA之順方向電壓(驅動電壓) 則爲3.2V。另外,發光波長爲460nm,發光輸出爲10.8mW。 I 此種發光二極體之特性,可針對從製成之氮化鎵系化合物 半導體積層物的大致全面所製成的發光二極體,無偏差地 獲得。 另外,在以電流30mA進行100小時之通電的前後,測定 電流爲100#Α之逆方向電壓,經比較後,該逆方向電壓之 變化率爲〇 %。 另外,第3至第1 0圖爲針對所獲得之晶片之一’以剖面 TEM且以1〇〇〇,〇〇〇倍所觀察之照片的一例。觀察係針對某 1304275 " 一剖面,且在以20 // m間隔所配置的8個部位來進行。井 • 戶層之號碼係從氮化物半導體積層構造之表面側(半導體 • 側)所數起爲1至5。亦即,井戶層1係位於p型層側,井 戶層5係位於η型層側。圖中,A爲厚膜部,B爲薄膜部。 另外,在第3至第10圖記載有其部位中之各井戶層的最大 膜厚及最小膜厚。 表1顯示將第3至第1 〇圖所示之8個部位加以綜合,以 求得各井戶層之最大膜厚、最小膜厚、平均膜厚、及最大 ® 膜厚與最小膜厚之與平均膜厚的差的比率之結果。 [表1] 井層 最大膜厚(nm) 最小膜厚(nm) 平均膜厚(nm) 差之比率 1 3.1 2.8 2.95 ±5.1% 2 3.2 1.8 2.50 ±28.0% 3 3.1 1.9 2.50 ±24.0% 4 3.1 1.6 2.35 ±31.9% 5 3.2 1.7 2.45 ±30.6% 從表1可知井戶層1之膜厚範圍爲平均膜厚±5.1%、且在 10 %以內,所以爲本發明之厚度均勻的井戶層。另外,井戶 φ 層2至5之膜厚範圍分別爲平均膜厚±28.0%、±24.0%、 ±31.9%及±30.6%、且全部超過1〇%,所以爲本發明之厚度 不勻的井戶層。在井戶層2至5中,比各自之平均膜厚更 厚之部分爲厚膜部,而薄膜部分爲薄膜部。 第3至第10圖中,障壁層約爲15nm之膜厚。障壁層完 全塡埋了井戶層之薄膜部及厚膜部的膜厚的差。 第11至第18圖爲將倍率變更爲200,000倍來觀察第3 至第1 0圖之部位附近的TEM照片。在所有圖中,可知井 戶層1係均勻的厚度。 -28- .1304275 在該些TEM照片中,測定井戶層2至5的厚膜部之寬度 • 及薄膜部的寬度,並評價其分布。又’各井戶層之厚膜部 • 及薄膜部的判定,係根據從第3至第1 〇圖所求得之上述各 井戶層的平均厚度來進行。表2顯示其結果。例如,在第 1 1圖之TEM照片的井戶層2中,從TEM照片之視野左側’ 厚膜部爲寬度250nm,接著薄膜部爲60nm的寬度範圍,接 著,厚膜部爲寬度1 0 5 n m,接著’薄膜部爲3 5 n m的範圍’ 厚膜部爲75nm,但是在表中記入厚膜部(250nm)-薄膜部 ® (60nm)-厚膜部(1 〇5nm)-薄膜部(35nm)-厚膜部(75nm)。On the surface of the p-type AlGaN* contact layer of the formed gallium nitride-based compound semiconductor laminate, Pt, Rh, and Au are sequentially formed by laminating from the side of the contact layer by a method known in the art. Construct a reflective positive electrode. Thereafter, dry etching is performed on the gallium nitride-based compound semiconductor laminate to expose a negative electrode forming portion of the highly doped Ge n-type GaN contact layer, and Ti is sequentially deposited from the contact layer side in the exposed portion. A1 was made into a negative electrode. By these operations, an electrode having the shape shown in Fig. 2 was produced. The gallium nitride-based compound semiconductor having a positive electrode and a negative electrode as described above is laminated, and the back surface of the sapphire substrate is honed and honed to form a mirror-like surface. Thereafter, the gallium nitride-based compound semiconductor laminate was cut into individual wafers having a square shape of 305 μm, and was placed on the sub-fixing plate with the electrodes facing downward. The sub-fixing plate is placed on the lead frame, and the gold wire is connected to the lead frame to form a light-emitting diode. When a current is caused to flow in the forward direction between the positive electrode and the negative electrode of the light-emitting diode fabricated as described above, the forward voltage (driving voltage) at a current of 20 mA is 3.2V. Further, the emission wavelength was 460 nm, and the light emission output was 10.8 mW. I. The characteristics of such a light-emitting diode can be obtained without any deviation from the light-emitting diode which is made substantially from the entire gallium nitride-based compound semiconductor laminate. Further, before and after energization for 100 hours at a current of 30 mA, the voltage in the reverse direction of the current of 100 #Α was measured, and after the comparison, the rate of change in the reverse direction voltage was 〇%. Further, the third to tenth graphs are examples of photographs observed by one of the obtained wafers in a cross-sectional TEM and at a magnification of 1 〇〇〇. The observations were made for a 1304275 " section and were performed at 8 locations at 20 // m intervals. Well • The number of the floor is 1 to 5 from the surface side (semiconductor side) of the nitride semiconductor laminate structure. That is, the well layer 1 is located on the p-type layer side, and the well layer 5 is located on the n-type layer side. In the figure, A is a thick film portion, and B is a thin film portion. Further, in Figs. 3 to 10, the maximum film thickness and the minimum film thickness of each of the well layers in the portion are described. Table 1 shows that the eight locations shown in Figures 3 to 1 are combined to determine the maximum film thickness, minimum film thickness, average film thickness, and maximum film thickness and minimum film thickness of each well layer. The result of the ratio of the difference to the average film thickness. [Table 1] Maximum film thickness (nm) of the well layer Minimum film thickness (nm) Average film thickness (nm) Ratio of difference 1 3.1 2.8 2.95 ±5.1% 2 3.2 1.8 2.50 ±28.0% 3 3.1 1.9 2.50 ±24.0% 4 3.1 1.6 2.35 ±31.9% 5 3.2 1.7 2.45 ±30.6% It can be seen from Table 1 that the film thickness of the well layer 1 is within the average film thickness of ±5.1% and within 10%, so it is a well-layered well layer of the present invention. In addition, the film thickness range of the well φ layer 2 to 5 is an average film thickness of ±28.0%, ±24.0%, ±31.9%, and ±30.6%, and all of them exceed 1%, so the thickness of the present invention is uneven. Well household level. In the well layers 2 to 5, a portion thicker than the average film thickness of each is a thick film portion, and a film portion is a film portion. In the third to tenth figures, the barrier layer has a film thickness of about 15 nm. The barrier layer completely buryes the difference in film thickness between the film portion and the thick film portion of the well layer. In the eleventh to eighteenth drawings, the TEM photographs in the vicinity of the portions of the third to tenth graphs were observed by changing the magnification to 200,000 times. In all the figures, it is known that the well layer 1 is uniform in thickness. -28-.1304275 In these TEM photographs, the width of the thick film portion of the well layers 2 to 5 and the width of the film portion were measured, and the distribution thereof was evaluated. Further, the determination of the thick film portion and the film portion of each of the well layers is performed based on the average thickness of each of the above-mentioned well layers obtained from the third to the first drawings. Table 2 shows the results. For example, in the well layer 2 of the TEM photograph of Fig. 1, the thick film portion on the left side of the TEM photograph has a width of 250 nm, and then the film portion has a width of 60 nm, and then the thick film portion has a width of 1 0 5 . Nm, then 'the film portion is in the range of 35 nm', and the thick film portion is 75 nm, but in the table, a thick film portion (250 nm) - a thin film portion (60 nm) - a thick film portion (1 〇 5 nm) - a thin film portion ( 35 nm) - thick film portion (75 nm).
-29 - 1304275-29 - 1304275
[表2] TEM照片 井層 厚膜部及薄膜部之分布 _ 誤差 薄膜部 厚膜部 2 厚膜部(250nm)-薄膜部(60nm)·厚膜部(105nm)-薄膜部(35nm)-厚膜部(75nm) 35nm 〜60nm 75nm 〜250nm 增1 1回 3 厚膜部(260nm)-薄膜部(45nm)_厚膜部(220nm) 45nm 220nm 〜260nm 弟11圖 4 厚膜部(160nm)-薄膜部(100nm)-厚膜部(220nm) 100nm 160nm 〜220nm 5 厚膜部(260nmV薄膜部(70nm)·厚膜部(12〇nm) 70nm 120nm 〜260nm 2 厚膜部(41〇nm)-薄膜部(35nm)-厚膜部(50nm)_薄膜部(3〇nm) 30nm 〜35nm 50nm〜410nm 第12圖 3 厚膜部(470nm)-薄膜部G〇nm) 30nm 470nm 4 學膜部(185nm)-薄膜部(4〇nm)-厚膜部(235nm)-薄膜部(80nm) 40nm 〜80nm 185nm 〜235nm 5 厚膜部(145nm)-薄膜部dm)-厚膜部(245nm)·薄膜部(40nm) 40nm 〜50nm 145nm 〜245nm 2 厚膜部(270nm)-薄膜部(65nm)-厚膜部(20nm)-薄膜部(55nm) 55nm 〜65nm 20nm 〜270nm ^φ:Λ ΟΓ^Ι 3 厚膜部(320nm)-薄膜部(8〇nm)-厚膜部(70nm)屬膜部(50nm) 50nm 〜80nm 70nm 〜320nm 弟13圖 4 厚膜部(270nm)-薄膜部(9〇nm>厚膜部(120nm>薄膜部(30nm) 30nm 〜90nm 120nm 〜270nm 5 厚膜部(310mn>薄膜部(4〇nm)-厚膜部(200nm) 40nm 200nm〜310nm 2 厚膜部(190nm>薄膜部(60nm)-厚膜部(120nm>薄膜部(60nm>厚膜部(75nm) 60nm 75nm 〜190nm αφ; 1 a rsi 3 厚膜部(320nm>薄膜部(40nm>厚膜部(60nm)-薄膜部(60nm) 40nm 〜60nm 60nm 〜320nm 弟14圖 4 薄膜部(60nm)-厚膜部(65nm)-薄膜部(90nm)-厚膜部(140nm)-薄膜部(55nm) 55nm 〜90nm 65nm 〜140nm 5 厚膜部(330nm>薄膜部(45nm)-厚膜部(65nm)-薄膜部(60nm) 45nm 〜60nm 65nm 〜300nm 2 厚膜部(450nm>薄膜部(50nm)-厚膜部(40nm)-薄膜部(35nm) 35nm 〜50nm 40nm 〜450nm 1 c|SI 3 厚膜部(580nm) - 580nm 弟1!)圖 4 厚膜部(520nm)-薄膜部(70nm) 70nm 520nm 5 厚膜部(540nm)-薄膜部(55nm) 55nm 540nm 2 薄膜部(40nm)-厚膜部(250nm>薄膜部(lOOnm)-厚膜部(130nm)-薄膜部(60nm) 40nm 〜lOOnm 130nm 〜250nm /φ: 1 固 3 厚膜部(500nm>薄膜部(75nm) 75nm 500nm 弟16圖 4 厚膜部(580nm) - 580nm 5 厚膜部(600nm) - 600nm 2 薄膜部(65nm)-厚膜部(45nm)-薄膜部(30mn)-厚膜部(320nm)-薄膜部(lOOnm) 30nm 〜l〇0nm 45nm 〜320nm 1 otsi 3 厚膜部(330nm)-薄膜部(50nm)-厚膜部(180nm) 50nm 180nm 〜330nm 苐17圖 4 厚膜部(60nm>薄膜部(100nm>厚膜部(300nm)-薄膜部(50nm) 50nm 〜lOOnm 60nm 〜300nm 5 薄膜部(40nm)-厚膜部(330nm)-薄膜部(60nm) 40nm 〜60nm 330nm 2 薄膜部(80nm)-厚膜部(95nm)-薄膜部(95nm)-厚膜部(140nm)-薄膜部(70nm) 70nm 〜95nm 95nm 〜140nm 3 厚膜部(130nm)·薄膜部(60nm)-厚膜部(250nm)-薄膜部(100nm) 60nm 〜lOOnm 130nm 〜250nm 第18圖 4 薄膜部(70nm)-厚膜部(275nm)-薄膜部(90nm)·厚膜部(100nm>薄膜部(40nm) 40nm 〜90nm lOOnm 〜275nm 5 薄膜部(100nm)-厚膜部(85nm)-薄膜部(35nm>厚膜部(105nm)-薄膜部(6〇nm) 35nm 〜lOOnm 85nm 〜105nm 從該表可知,當求取各井戶層之薄膜部及厚膜部的寬度的 分布狀態時,薄膜部爲井戶層2爲30〜l〇〇nm,井戶層3爲 30〜lOOnm,井戶層4爲30〜lOOnm,井戶層5爲35〜lOOnm。 另外,厚膜部爲井戶層2爲20〜450nm,井戶層3爲60〜 580n m,井戶層4爲60〜580nm,井戶層5爲65〜600nm。 -30- 1304275 (第1比較例) 本比較例中,除將所有井戶層作成厚度均勻的井戶層 外’其他與第1實施例相同製成氮化鎵系化合物半導體積 層物。即,除在第1至第5層之障壁層中,亦與第6層相 同’在形成障壁層A後,繼續將TEGa及SiH4供給爐內的 狀態,且將基板溫度昇溫爲9 2 0 °C外,其他與第1實施例相 同製成氮化鎵系化合物半導體積層物。 使用該氮化鎵系化合物半導體積層物,與第1實施例相 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲3.9V。另外,發光波長爲460nm,發光輸出顯 示 9 m W 〇 另外,經比較1 0 μ A之逆方向電壓的初期値及以電流 30mA進行100小時之通電後的10// A之逆方向電壓値,逆 方向電壓之變化率爲- 0.5 %。 (第2比較例) 本比較例中,除將所有井戶層作成厚度不均勻的井戶層 外,其他與第1實施例相同製成氮化鎵系化合物半導體積 層物。即,除在第6層之障壁層中,亦與第1至第5層相 同,在形成障壁層A後’停止將,TEGa及SiH4供給爐內, 且將基板溫度昇溫爲920°C外,其他與第1實施例相同製成 氮化鎵系化合物半導體積層物。 使用該氮化鎵系化合物半導體積層物’與第1實施例相 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲3.15V。另外,發光波長爲460nm ’發光輸出顯[Table 2] TEM photograph of the distribution of the thick film portion and the thin film portion of the well layer _ Error film portion thick film portion 2 Thick film portion (250 nm) - Thin film portion (60 nm) Thick film portion (105 nm) - Thin film portion (35 nm) - Thick film portion (75nm) 35nm ~ 60nm 75nm ~ 250nm Increase 1 1 back 3 Thick film portion (260nm) - Thin film portion (45nm) Thick film portion (220nm) 45nm 220nm ~ 260nm Young 11 Figure 4 Thick film portion (160nm) - Thin film portion (100 nm) - Thick film portion (220 nm) 100 nm 160 nm to 220 nm 5 Thick film portion (260 nm V thin film portion (70 nm) · Thick film portion (12 〇 nm) 70 nm 120 nm to 260 nm 2 Thick film portion (41 〇 nm) - Thin film portion (35 nm) - Thick film portion (50 nm) - Thin film portion (3 Å nm) 30 nm to 35 nm 50 nm to 410 nm Fig. 12 Fig. 3 Thick film portion (470 nm) - Thin film portion G 〇 nm) 30 nm 470 nm 4 Film portion (185 nm) - thin film portion (4 〇 nm) - thick film portion (235 nm) - thin film portion (80 nm) 40 nm to 80 nm 185 nm to 235 nm 5 thick film portion (145 nm) - thin film portion dm) - thick film portion (245 nm) Thin film portion (40 nm) 40 nm to 50 nm 145 nm to 245 nm 2 thick film portion (270 nm) - thin film portion (65 nm) - thick film portion (20 nm) - thin film portion (55 nm) 55 nm to 65 nm 20 nm to 270 nm ^ φ: Λ ΟΓ ^ Ι 3 Thick film portion (320 nm) - Thin film portion (8 〇 nm) - Thick film portion (70 nm) is a film portion (50 nm) 50 nm ~ 80 nm 70 nm 〜 32 0 nm 弟13Fig. 4 Thick film portion (270 nm) - Thin film portion (9 Å nm) Thick film portion (120 nm > Thin film portion (30 nm) 30 nm to 90 nm 120 nm to 270 nm 5 Thick film portion (310 mn > Thin film portion (4 〇 nm) - Thick film portion (200 nm) 40 nm 200 nm to 310 nm 2 Thick film portion (190 nm) Thin film portion (60 nm) - Thick film portion (120 nm) Thin film portion (60 nm > Thick film portion (75 nm) 60 nm 75 nm to 190 nm αφ; 1 a rsi 3 Thick film portion (320 nm) Thin film portion (40 nm > Thick film portion (60 nm) - Thin film portion (60 nm) 40 nm to 60 nm 60 nm to 320 nm Younger 14 Fig. 4 Thin film portion (60 nm) - Thick film portion (65 nm) - Thin film portion ( 90 nm) - thick film portion (140 nm) - thin film portion (55 nm) 55 nm to 90 nm 65 nm to 140 nm 5 thick film portion (330 nm) thin film portion (45 nm) - thick film portion (65 nm) - thin film portion (60 nm) 45 nm to 60 nm 65 nm ~300nm 2 Thick film portion (450nm> Thin film portion (50nm) - Thick film portion (40nm) - Thin film portion (35nm) 35nm ~ 50nm 40nm ~ 450nm 1 c|SI 3 Thick film portion (580nm) - 580nm Brother 1!) Fig. 4 Thick film portion (520 nm) - Thin film portion (70 nm) 70 nm 520 nm 5 Thick film portion (540 nm) - Thin film portion (55 nm) 55 nm 540 nm 2 Thin film portion (40 nm) - Thick film portion (250 nm > Thin film portion (100 nm) - Thick film portion (130 nm) - thin film portion (60 nm) 40 nm to 100 nm 130 nm to 250 nm / φ: 1 Solid 3 Thick film portion (500 nm) Thin film portion (75 nm) 75 nm 500 nm Younger 16 Fig. 4 Thick film portion (580 nm) - 580 nm 5 Thick film portion (600 nm) - 600 nm 2 Thin film portion (65 nm) - Thick film portion (45 nm) - Thin film portion (30mn) - Thick film portion (320 nm) - Thin film portion (100 nm) 30 nm to 10 Å 0 nm 45 nm to 320 nm 1 otsi 3 Thick film portion (330 nm) - Thin film portion (50 nm) - Thick film portion (180 nm) 50 nm 180 nm to 330 nm 苐17Fig. 4 Thick film portion (60 nm) Thin film portion (100 nm) Thick film portion (300 nm) - Thin film portion (50 nm) 50 nm to 100 nm 60 nm to 300 nm 5 Thin film portion (40 nm) - Thick film portion (330 nm) - Thin film portion (60 nm) 40 nm to 60 nm 330 nm 2 Thin film portion (80 nm) - Thick film portion (95 nm) - Thin film portion (95 nm) - Thick film portion (140 nm) - Thin film portion (70 nm) 70 nm to 95 nm 95 nm to 140 nm 3 Thick film (130 nm), thin film portion (60 nm) - thick film portion (250 nm) - thin film portion (100 nm) 60 nm to 100 nm 130 nm to 250 nm, Fig. 18 Fig. 4 Thin film portion (70 nm) - thick film portion (275 nm) - thin film portion (90 nm) Thick film portion (100 nm) thin film portion (40 nm) 40 nm to 90 nm lOOnm to 275 nm 5 thin film portion (100 nm) - thick film portion (85 nm) - thin film portion (35 nm > thick film portion (105 nm) - thin film portion (6 〇) Nm) 35nm ~ lOOnm 85nm ~ 105nm From this table, when looking for the thin layer of each well When the width of the film portion and the thick film portion is distributed, the film portion is 30 to 10 nm for the well layer 2, 30 to 100 nm for the well layer 3, and 30 to 100 nm for the well layer 4, and the well layer 5 It is 35~100 nm. Further, the thick film portion is 20 to 450 nm for the well layer 2, 60 to 580 nm for the well layer 3, 60 to 580 nm for the well layer 4, and 65 to 600 nm for the well layer 5. -30- 1304275 (First comparative example) In the present comparative example, a gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment except that all the well layers were formed into a well-thickness layer. That is, in the barrier layers of the first to fifth layers, the same as the sixth layer, 'after the formation of the barrier layer A, the TEGa and SiH4 are continuously supplied to the furnace, and the substrate temperature is raised to 9 2 0 °. Other than C, a gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment. Using this gallium nitride-based compound semiconductor laminate, a light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the forward voltage of the current of 20 mA was 3.9V. In addition, the emission wavelength is 460 nm, and the light-emitting output shows 9 m W. In addition, the initial voltage of the reverse voltage of 10 μA is compared with the reverse voltage of 10//A after the current of 30 mA for 30 hours. The rate of change in the reverse direction voltage is -0.5%. (Second Comparative Example) In the present comparative example, a gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment except that all the well layers were formed as a well layer having a non-uniform thickness. In other words, in the barrier layer of the sixth layer, similarly to the first to fifth layers, after the barrier layer A is formed, the TEGa and SiH4 are stopped and supplied to the furnace, and the substrate temperature is raised to 920 ° C. A gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment. Using this gallium nitride-based compound semiconductor laminate, the light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the forward voltage of the current of 20 mA was 3.15 V. In addition, the emission wavelength is 460nm ’
SJ -31 - 1304275 示 9mW 〇 另外,經比較1 〇 # A之逆方向電壓的初期値及以電流 30mA進行100小時之通電後的10//A之逆方向電壓値,逆 方向電壓之變化率爲-7 %。 (第2實施例)· 本實施例中,除僅將最靠近η型層之井戶層作成厚度均 勻的并戶層外,其他與第1實施例相同製成氮化鎵系化合 物半導體積層物。即,除在第2層之障壁層中,與第1實 施例之第6層相同,在形成障壁層Α後,繼續將TEGa及 SiH4供給爐內的狀態,且將基板溫度昇溫爲920 °C,及在第 6層之障壁層中,與第1實施例之第1至第5層相同,在形 成障壁層A後,停止將TEGa及SiH4供給爐內,且將基板 溫度昇溫爲920 °C外,其他與第1實施例相同製成氮化鎵系 化合物半導體積層物。 使用該氮化鎵系化合物半導體積層物,與第1實施例相 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲 3.3V,發光波長爲 460nm,發光輸出顯示 10.8mW。 (第3實施例) 本實施例中,除僅將從p型層數起爲第3層之井戶層作 成厚度均勻的井戶層外,其他與第1實施例相同製成氮化 鎵系化合物半導體積層物。即,除在第4層之障壁層中, 與第1實施例之第6層相同,在形成障壁層A後,繼續將 TEGa及SiH4供給爐內的狀態,且將基板溫度昇溫爲 8、 -32- 1304275 9 20 °C,及在第6層之障壁層中,與第1實施例之第1至第 5層相同,在形成障壁層A後,停止將TEGa及SiH4供給 爐內,且將基板溫度昇溫爲920°C外,其他與第1實施例相 同製成氮化鎵系化合物半導體積層物。 使用該氮化鎵系化合物半導體積層物,與第1實施例相 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲3.2V,發光波長爲46 Onm,發光輸出顯示9.7 mW。 (第4實施例) > 本實施例中,除僅將最靠近P型層之井戶層及最靠近η 型層之井戶層之雙方作成厚度均勻的井戶層外,其他與第 1實施例相同製成氮化鎵系化合物半導體積層物。即,’除 在第2層之障壁層中,亦與第6層相同,在形成障壁層A 後,繼續將TEGa及SiH4供給爐內的狀態,且將基板溫度 昇溫爲920°C外,其他與第1實施例相同製成氮化鎵系化合 物半導體積層物。 使用該氮化鎵系化合物半導體積層物,與第1實施例相 I 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲 3.45V,發光波長爲 460nm,發光輸出顯示 1 1.4mW。 (第5實施例) 本實施例中,除僅將從P型層數起爲第1及第2層之2 個井戶層作成厚度均勻的井戶層外,其他與第1實施例相 同製成氮化鎵系化合物半導體積層物。即,除在第5層之 障壁層中,亦與第6層相同,在形成障壁層A後,繼續將 -33 - 1304275 TEGa及SiH4供給爐內的狀態,且將基板溫度昇溫爲920t 外’其他與第丨實施例相同製成氮化鎵系化合物半導體積 層物。 使用該氮化鎵系化合物半導體積層物,與第1實施例相 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲 3.2V,發光波長爲 460nm,發光輸出顯示 10.2mW。 (第6實施例) 本實施例中,除僅將從p型層數起爲第1至第3層之3 個井戶層作成厚度均勻的井戶層外,其他與第1實施例相 同製成氮化鎵系化合物半導體積層物。即,除在第4及第 5層之障壁層中,亦與第6層相同,在形成障壁層A後, 繼續將TEGa及SiH4供給爐內的狀態,且將基板溫度昇溫 爲9 20 °C外,其他與第1實施例相同製成氮化鎵系化合物半 導體積層物。 使用該氮化鎵系化合物半導體積層物,與第1實施例相 同製成發光二極體並加以評價。其結果,電流20mA之順 方向電壓爲3.35V,發光波長爲460nm,發光輸出顯示 1 0 · 2m W。 (第7實施例) 本實施例中,雖在由第1實施例製成氮化鎵系化合物半 導體積層物上,與第1實施例相同地設置正極及負極,但 正極之構造係爲由p-AlGaN接觸層表面依序積層Au及Ni〇 之透明電極及於其上依序積層Ti、Au、Αι及Au的襯墊電 S) -34 - .1304275 極所構成的構造。 與第1實施例相同,經評價該發光二極體之性能的結 果,電流20mA之順方向電壓爲3.2V,發光波長爲460nm, 發光輸出顯示5.5mW。此種發光二極體之特性,針對從製 成之氮化鎵系化合物半導體積層物的大致全面所製成的發 光二極體,可無誤差的獲得。 (第3比較例) 本比較例中,使用由第1比較例所製成之氮化鎵系化合 物半導體積層物,與第7實施例相同製成具有電極構造的 發光二極體。 與第1實施例相同經評價其性能的結果,電流20mA之 順方向電壓爲3.9V,發光波長爲460nm,發光輸出顯示 5mW。 (第4比較例) 本比較例中,使用由第2比較例所製成之氮化鎵系化合 物半導體積層物,與第7實施例相同製成具有電極構造的 發光二極體。 與第1實施例相同經評價其性能的結果’電流20mA之 順方向電壓爲3.15V,發光波長爲460nm’發光輸出顯示 5mW。 (產業上之可利用性) 使用本發明之氮化鎵系化合物半導體積層物所獲得的發 光元件,具有低驅動電壓及高發光輸出’所以其產業上之 利用價値非常大。 -35- 1304275 【圖式簡單說明】 * 第1圖爲顯示由實施例及比較例所製作之氮化鎵系化合 . 物半導體積層物的剖面之模式圖。 第2圖爲顯示由實施例及比較例所製作之發光二極體的 電極構造之模式圖。 第3圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之一例。 第4圖顯示由第1實施例所製作之氮化鎵系化合物半導 ® 體積層物的剖面TEM照片之另一例。 第5圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之又一例。 第6圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之又一例。 第7圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之又一例。 第8圖顯示由第1實施例所製作之氮化鎵系化合物半導 I 體積層物的剖面TEM照片之又一例。 第9圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之又一例。 第1 0圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之又一例。 第1 1圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面TEM照片之又一例。 第1 2圖顯示由第1貧施例所製作之氮化鎵系化合物半導 -36 - 1304275 ~ 體積層物的剖面TEM照片之又一例。 • 第1 3圖顯示由第1實施例所製作之氮化鎵系化合物半導 • 體積層物的剖面ΤΕΜ照片之又一例。 第1 4圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面ΤΕΜ照片之又一例。 第1 5圖灝示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面ΤΕΜ照片之又一例。 第1 6圖顯示由第1實施例所製作之氮化鎵系化合物半導 t 體積層物的剖面ΤΕΜ照片之又一例。 第1 7圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面ΤΕΜ照片之又一例。 第1 8圖顯示由第1實施例所製作之氮化鎵系化合物半導 體積層物的剖面ΤΕΜ照片之又一例。SJ -31 - 1304275 shows 9mW 〇In addition, the initial 値 of the reverse direction voltage of 1 〇# A and the reverse direction voltage 10 of 10//A after 100 hours of current supply of 30 mA, the rate of change of the reverse direction voltage It is -7 %. (Second Embodiment) In the present embodiment, a gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment except that only the well layer closest to the n-type layer was formed into a uniform layer having a uniform thickness. . In other words, in the barrier layer of the second layer, in the same manner as the sixth layer of the first embodiment, after the barrier layer is formed, TEGa and SiH4 are continuously supplied to the furnace, and the substrate temperature is raised to 920 °C. And in the barrier layer of the sixth layer, in the same manner as the first to fifth layers of the first embodiment, after the barrier layer A is formed, the supply of TEGa and SiH4 to the furnace is stopped, and the temperature of the substrate is raised to 920 °C. A gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment. Using this gallium nitride-based compound semiconductor laminate, a light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the current of 20 mA in the forward direction was 3.3 V, the emission wavelength was 460 nm, and the light-emitting output showed 10.8 mW. (Third Embodiment) In the present embodiment, the gallium nitride system is formed in the same manner as in the first embodiment except that the well layer of the third layer is formed from the p-type layer as the well layer having the uniform thickness. Compound semiconductor laminate. In other words, in the barrier layer of the fourth layer, in the same manner as the sixth layer of the first embodiment, after the barrier layer A is formed, TEGa and SiH4 are continuously supplied into the furnace, and the substrate temperature is raised to 8, 32- 1304275 9 20 ° C, and in the barrier layer of the sixth layer, in the same manner as the first to fifth layers of the first embodiment, after forming the barrier layer A, the supply of TEGa and SiH4 to the furnace is stopped, and A gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment except that the substrate temperature was raised to 920 °C. Using this gallium nitride-based compound semiconductor laminate, a light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the current of 20 mA in the forward direction was 3.2 V, the emission wavelength was 46 Onm, and the luminous output showed 9.7 mW. (Fourth Embodiment) > In the present embodiment, except that only the well layer closest to the P-type layer and the well layer closest to the n-type layer are made into a well-layer having a uniform thickness, the other and the first In the same manner as in the examples, a gallium nitride-based compound semiconductor laminate was produced. In other words, in the barrier layer of the second layer, the same as the sixth layer, after the barrier layer A is formed, TEGa and SiH4 are continuously supplied to the furnace, and the substrate temperature is raised to 920 ° C. A gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment. Using this gallium nitride-based compound semiconductor laminate, a light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the current of 20 mA in the forward direction was 3.45 V, the emission wavelength was 460 nm, and the luminous output showed 1 1.4 mW. (Fifth Embodiment) In the present embodiment, the two well layers of the first and second layers are formed into a well-layer having a uniform thickness from the number of P-type layers, and the other embodiments are the same as in the first embodiment. A gallium nitride-based compound semiconductor laminate. That is, in the barrier layer of the fifth layer, as in the sixth layer, after the barrier layer A is formed, the state of -33 - 1304275 TEGa and SiH4 is continuously supplied to the furnace, and the substrate temperature is raised to 920 t. A gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment. Using this gallium nitride-based compound semiconductor laminate, a light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the forward voltage of the current of 20 mA was 3.2 V, the emission wavelength was 460 nm, and the light-emitting output showed 10.2 mW. (Sixth embodiment) In the present embodiment, the same applies to the first embodiment except that the three well layers of the first to third layers are formed from the p-type layer to form a well layer having a uniform thickness. A gallium nitride-based compound semiconductor laminate. That is, in the barrier layers of the fourth and fifth layers, as in the sixth layer, after the barrier layer A is formed, TEGa and SiH4 are continuously supplied to the furnace, and the substrate temperature is raised to 9 20 °C. A gallium nitride-based compound semiconductor laminate was produced in the same manner as in the first embodiment. Using this gallium nitride-based compound semiconductor laminate, a light-emitting diode was produced in the same manner as in the first example and evaluated. As a result, the forward voltage of the current of 20 mA was 3.35 V, the emission wavelength was 460 nm, and the light-emitting output showed 1 0 · 2 mW. (Seventh embodiment) In the present embodiment, the positive electrode and the negative electrode are provided in the gallium nitride-based compound semiconductor laminate according to the first embodiment, but the structure of the positive electrode is p. - The transparent electrode of Au and Ni 依 is sequentially laminated on the surface of the AlGaN contact layer, and the structure of the pad of the Ti, Au, Α, and Au is sequentially laminated thereon, and the structure of the S) -34 - .1304275 electrode is formed. As in the first embodiment, as a result of evaluating the performance of the light-emitting diode, the forward voltage of the current of 20 mA was 3.2 V, the emission wavelength was 460 nm, and the light-emitting output showed 5.5 mW. The characteristics of such a light-emitting diode can be obtained without error for the light-emitting diode which is formed substantially from the total thickness of the formed gallium nitride-based compound semiconductor laminate. (Third Comparative Example) In the comparative example, a gallium nitride-based compound semiconductor laminate produced by the first comparative example was used, and a light-emitting diode having an electrode structure was produced in the same manner as in the seventh embodiment. As a result of evaluating the performance as in the first embodiment, the forward voltage of the current of 20 mA was 3.9 V, the emission wavelength was 460 nm, and the light-emitting output showed 5 mW. (Fourth Comparative Example) In the comparative example, a gallium nitride-based compound semiconductor laminate produced by the second comparative example was used, and a light-emitting diode having an electrode structure was produced in the same manner as in the seventh embodiment. As a result of evaluating the performance as in the first embodiment, the forward voltage of the current of 20 mA was 3.15 V, and the emission wavelength was 460 nm. The luminous output showed 5 mW. (Industrial Applicability) The light-emitting element obtained by using the gallium nitride-based compound semiconductor laminate of the present invention has a low driving voltage and a high light-emitting output, so that the industrial use price is extremely large. -35- 1304275 [Brief Description of the Drawings] * Fig. 1 is a schematic view showing a cross section of a gallium nitride-based compound semiconductor laminate produced by the examples and the comparative examples. Fig. 2 is a schematic view showing the electrode structure of the light-emitting diodes produced in the examples and the comparative examples. Fig. 3 is a view showing an example of a cross-sectional TEM photograph of a gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 4 is a view showing another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive ® volume layer produced in the first embodiment. Fig. 5 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 6 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 7 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 8 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semi-conductive I volume layer produced in the first embodiment. Fig. 9 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 10 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 1 is a view showing still another example of a cross-sectional TEM photograph of the gallium nitride-based compound semiconductive volume layer produced in the first embodiment. Fig. 1 is a view showing still another example of a cross-sectional TEM photograph of a gallium nitride-based compound semiconductor-36 - 1304275 - volume layer produced by the first embodiment. • Fig. 1 is a view showing still another example of a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semi-conductive volume layer produced in the first embodiment. Fig. 14 is a view showing still another example of a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semi-conductive volume layer produced in the first embodiment. Fig. 15 is a view showing still another example of a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semi-conductive volume layer produced in the first embodiment. Fig. 16 is a view showing still another example of a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semi-conductive t-volume layer produced in the first embodiment. Fig. 17 is a view showing still another example of a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semi-conductive volume layer produced in the first embodiment. Fig. 18 is a view showing still another example of a cross-sectional ΤΕΜ photograph of the gallium nitride-based compound semi-conductive volume layer produced in the first embodiment.
-37 --37 -
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005104963 | 2005-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200717861A TW200717861A (en) | 2007-05-01 |
| TWI304275B true TWI304275B (en) | 2008-12-11 |
Family
ID=45070903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW95110847A TWI304275B (en) | 2005-03-31 | 2006-03-29 | Gallium nitride-based compound semiconductor multilayer structure and production method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI304275B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3998623B1 (en) | 2019-07-10 | 2025-07-02 | Hitachi High-Tech Corporation | Scintillator for charged particle beam device and charged particle beam device |
-
2006
- 2006-03-29 TW TW95110847A patent/TWI304275B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TW200717861A (en) | 2007-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI385822B (en) | Method for manufacturing group III nitride semiconductor layer, and group III nitride semiconductor light-emitting device, and lamp | |
| TW200908393A (en) | Nitride semiconductor light emitting element and method for manufacturing nitride semiconductor | |
| TWI270217B (en) | Gallium nitride-based compound semiconductor multilayer structure and production method thereof | |
| JP2001160627A (en) | Group III nitride compound semiconductor light emitting device | |
| CN101438429A (en) | III nitride compound semiconductor laminated structure | |
| JP2010267950A (en) | Nitride-based semiconductor device and manufacturing method thereof | |
| TW200807831A (en) | Nitride semiconductor | |
| TW200807762A (en) | Nitride semiconductor light emitting element | |
| JP5504618B2 (en) | Group III nitride semiconductor light-emitting device and method for manufacturing the same | |
| JP2009021638A (en) | Gallium nitride compound semiconductor light emitting device | |
| JP2009283620A (en) | Group iii nitride semiconductor light emitting element, method for manufacturing thereof, and lamp | |
| TWI252599B (en) | N-type group III nitride semiconductor layered structure | |
| US7727873B2 (en) | Production method of gallium nitride-based compound semiconductor multilayer structure | |
| JP4762023B2 (en) | Gallium nitride compound semiconductor laminate and method for producing the same | |
| TWI270220B (en) | Group III nitride semiconductor light emitting device | |
| JP4641812B2 (en) | Gallium nitride compound semiconductor laminate and method for producing the same | |
| JP5533093B2 (en) | Group III nitride semiconductor light emitting device manufacturing method | |
| JP2008034444A (en) | Group iii nitride semiconductor light emitting device, method of manufacturing same, and lamp | |
| JP5105738B2 (en) | Method for producing gallium nitride compound semiconductor laminate | |
| JP2007329312A (en) | Method of manufacturing laminated layer structure of group iii nitride semiconductor | |
| JP2010010444A (en) | Semiconductor light emitting element, lamp and method of manufacturing semiconductor light emitting element | |
| TWI304275B (en) | Gallium nitride-based compound semiconductor multilayer structure and production method thereof | |
| JP2015115343A (en) | Method of manufacturing nitride semiconductor device | |
| TWI360234B (en) | Production method of group iii nitride semiconduct | |
| JP2005277401A (en) | Gallium nitride-based compound semiconductor laminate and manufacturing method thereof |