1304263 九、發明說明： 省 【發明所屬之技術領域】 本發明係有關一種絕緣閘極型半導體裝置及其製造方 法’尤有關一種藉著分離背閘極（back gate)而能以單一晶 片進行雙向切換動作的絕緣閘極型半導體裝置及其製造方 法。 【先前技術】 _ 第16圖係顯示做為習知半導體裝置之一例的η通道型 金氧半導體場效電晶體（M0SFET)。第16圖（Α)為平面圖， 第16圖（Β)為第16圖（Α)之f-f線的斷面圖。此外，第16 圖（A)係省略層間絕緣膜並以虛線來表示源極電極。 如第16圖（A)，在基板表面，溝渠44係以條紋狀形成， 並以鄰接溝渠44之方式配置源極區域48以及主體區域 49。溝渠44、源極區域48、主體區域（body tegion)49係 向同一個方向延伸。 • 如第16圖（B)，n通道型M0SFET係在n+型的半導體基 板41上層積n-型的遙晶（印丨taxiai)層且設置汲極區域 DR ，並在其上設置P型通道層43。並且，設置從通道層 43延伸到達n—型磊晶層的溝渠44，並以閘極氧化膜45覆 盖溝渠44的内壁，且在溝渠44中埋設閘極電極46。 、在鄰接溝渠44的通道層43表面，形成n+型的源極區 域48，相鄰的兩個單元（cen)的源極區域48間的通道層 43表面，係形成P+型的主體區域49。溝渠44上係以層間 、巴緣膜5〇覆蓋，並設置接觸源極區域48以及主體區域49 318086 6 1304263 、源極電極5卜源極電極51係連續設置在源極區域48 ，主體區域49上。此外，在基板的内面設置有没極電極 52 ° 上述的M0SFET係例如於用以進行二次電池的充放電 之電池管理的保護電路裝置中所採用者。 第^圖係為顯示保護電路裝置之一例的電路圖。 一次電池LiB係串聯兩個M〇SFET Q1及Q2。m〇sfet卯 φ .及Q2係將汲極D共通連接，並於兩端配置各自之源極s， 個別的閘極G係連接到控制電路1C。控制電路1C -邊 檢知二次電池LiB的電壓，一邊進行兩㈣刪⑽及的 的導通/切斷⑽/0FF)控制’而保護二次電池ub免於有過 充電、過放電、負載短路之情形(請參照專利文獻D。 > 控制電路1(：係檢測電池電壓，當檢測出的電壓 兩於最局設定電壓時，即將_ΕΤ⑽切換成切斷（不導 ，），以阻止二次電池LiB之過充電。此外，當檢測出的電 籲璧低於最低設定電壓時，乃將M〇smQ1切換成切斷，以 阻止二次電池UB之過放電。 專利文獻1 :曰本國專利公開第2002_11825 【發明内容】 (發明欲解決的問題） 如第16圖所示，習知的咖τ，主體區域49與源極 4 48係共通地連接到源極電極5卜該等之電位是被固 定^在將卿_用為雙向切換4的情形 個舰聊串聯連接，切換各源極電極51，而形成雙向的 318086 7 1304263 電流路徑。 這是因為，如第17圖，M0SFET係内藏有寄生二極體 PD。也就是說，在主體區域49(亦即背閘極區域）與源極區 域48的電位被固定住的M〇sm中，切斷時寄生二極體卯 的順方向動作是無法避免的。 因此，M0SFET切斷時，必須控制成，不會由於寄生二 極體PD產生不欲形成的電流路徑。 σ 為此如第1 7圖，將兩個相同的單元數、相同的晶片 尺寸的MGSFET串聯連接，並藉著控制電路來控制μ〇謂 Q卜Q2以及各自的寄生二極體pD。藉此形成所需的電流路 徑。 然而，在M0SFET中為了減低導通電阻（〇n resistance)，必須要有某左右的單元數以及晶片尺寸。另 方面一-人電池做為攜帶終端裝置的電池而變得十分普 及’隨著攜帶終端裝置的小型化，其保護電路小型化的要 求也愈來愈高。但是，上述以兩個M〇SFET Q1、Q2串聯連 接的保護電路，因應此要求係有其界限。 (解決問題的手段） 本發明為有鑒於相關問題而研創者，其解決問題之第 一手段為具備··在一導電型半導體基板上層積一導電型半 導體層的汲極區域；在前述半導體層表面所設置的逆導電 型通道層；於前述半導體層表面往第丨方向延伸，並具有 貝牙通道層之深度的溝渠；在該溝渠的内壁所設置的閘極 絕緣膜；填入於前述溝渠内的閘極電極；設置於前述通道 318086 8 1304263 .層表面而與前述溝渠相鄰接一導電型源極區域；設置在前 述通道層表面而鄰接前述溝渠以及前述源極區域的逆導電 型之主體區域；設置在前述源極區域上，於前述半導體層 表面中往第2方向延伸的第工電極層；以及設置在前述二 體區域上，於前述半導體層表面中往第2方向延伸的第2 電極層。 本發明之用以解決問題的第二手段係具備：在一導電 型半導體基板層積-導電型半導體層，並在該半導體層表 ••面形成逆導電型通道層的步驟；形成於前述半導體層表面 中往第1方向延伸、且具有貫穿通道層之深度的溝渠的步 2;在該溝渠的内壁形成閘極絕緣膜的步驟；形成填入至 f述溝渠内之閘極電極的步驟；在前述通道層表面形成與 前述溝渠相鄰接之-導電型源極區域的步驟；在前述通道 層表面形成鄰接前述溝渠及前述源極領域之逆導電型之主 體區域的步驟；形成與前述源極區域接觸並於前述半導體 鲁層^中往第2方向延伸的第極層的步驟；以及形成 與前述主體區域接觸並於前述半導體層表面中往第2方向 延伸的弟2電極層的步驟。 (發明之效果） 依據本發明，第一，可將源極電極與汲極電極個別連 接在主體區域（背閘極區域藉此，可用—顆廳㈣來 切換源極區域與背_區歧路之㈣，及祕區域與背 閘極區域短路之狀態。 藉此，可遮斷當M0SFET切斷時由於寄生二極體所形成 31S0S6 9 1304263 •之不需要的電流路徑（相對於所希望的電流路徑是相反的 電流路徑）。 因此，可用一個M0SFET的晶片來切換雙向的電流路 徑’且能防止電流的逆流。 第二，藉著將層間絕緣膜填入溝渠内，可實現第】電 極層及第2電極層所接觸之基板表面的平坦化。亦即，由 層間絕緣膜造成之階梯覆蓋現象（step c〇verage)不會發 鲁生由於係以條紋狀形成第1電極層及第2電極層，故可 •與個別的源極區域以及主體區域充分地接觸，亦可以確保 高密著性。 ’' 第二，儘管於源極區域12、主體區域丨3、層間絕緣膜 的各個形成步驟中使用三片遮罩，對於遮罩對準偏移， 僅須考慮一片份即可。亦即，與以往考慮到以三步驟之三 片如的遮罩對準偏移相比較，可以貼近溝渠間的距離。因 此，動作面積的擴大係成為可能。藉此，只要是相同的晶 •片尺寸，即可降低導通電阻，只要是相同的單元數，即可 達成晶片尺寸的縮小化。 第四，可用一個M0SFET的晶片來實現可進行雙向切換 =作的元件，例如採用於二次電池的保護電路等時，可以 實現零件數目的減少及裝置小型化。 【實施方式】 、芩照第1圖至第15圖，以η通道型溝渠構造的m〇sfet 為例來說明本發明的實施型態。 首先，參照第1圖至第U圖說明第丨的實施型態。第 318086 10 1304263 - 圖係為顯示M0SFET的斜視圖。第1圖（A)係為配置第i 及第2電極層之圖式、第1圖（B)係以虛線表示配置有第1 及第2電極層的區域之圖式。另外，第2圖係為斷面圖、 第2圖（A)係為第1圖（a)之a_a剖線之斷面圖、第2圖（B) 係為第1圖（A)之b-b剖線之斷面圖。 MOSFET20係由半導體基板i、半導體層2、通道層3、 .冓、5閘極、纟e緣膜6、閘極電極7、源極區域12、主體區 _ _域13、層間絕緣膜1〇、第工電極層14、第2電極層15、 及汲極電極16所構成。 曰基板100係在n+型的矽半導體基板i上層積n_型的磊 晶層2等且設置汲極區域DR者。在汲極區域⑽表面設置 其為P型雜質區域之通道層3。 ^溝渠5係以貫穿通道層3且達至汲極區域2之深度而 設置。此外，於η-型磊晶層2(通道層3)表面之圖案，係 以條紋狀向第1方向延伸而形成。（參照第工圖（Β))。 ·#照第2圖’溝渠5内壁係覆蓋著對應驅動電壓之膜 厚的閘極絕緣膜6。閘極電極7係為將導入雜質而謀求低 電阻化之多晶矽予以埋設在溝渠5内者。閘極電極7其上 部係設置成比溝渠5開口部（亦即通道層3表面）低數U 左右的下方。 型 圍 溝 源極區域12係以鄰接溝渠5之方式擴散高濃度的η 雜質而設置者。源極區域12係設置在溝渠5開口部之周 的通道層3表面，且其-部份設置成沿著溝渠$侧壁往 渠5深度方向延伸而到達閘極電極7之深度。於第2圖 318086 11 1304263 .(A)所示之斷面，在相鄰的溝渠5之間僅配置源極區域12。 此外〜著溝^ 5的延伸方向第一方向相鄰之源極區域丄2 係以預定間距分離配置，且該等源極區域之間配置有主體 區域13。也就是說，一個源極區域12係鄰接沿溝渠5的 相同侧壁配置之二個主體區域13(請參照第丨圖〇))。 主體區域13係以鄰接溝渠5之方式擴散高濃度的p 型雜質而設置者。主體區域13係設置在溝渠5開口部之周 圍的通道層3表面。於第2圖。）所示之斷面，在相鄰的溝 渠5之間僅配置主體區域丨3。此外，沿著溝渠5的延伸方 向第1方向相鄰之主體區域丨3係以預定間距分離配置，且 該等主體區域之間配置有源極區域12。也就是說，一個主 體區域13係4接石溝渠5的相同侧壁配置之兩個源極區域 12(清麥照第1圖（b))。亦即，在第i圖雖然僅配置兩個源 極區域12及一個主體區域，但源極區域12與主體區域丄3 是複數地交互配置。 • 層間絕緣膜1 〇係全體填入溝渠5内。閘極電極7上端 (表面）係位於從通道層3表面往下方數千人左右，而層間 絕緣膜10係完全埋設於由該閘極電極7之上端到通道層3 表面的溝渠5内，沒有突出基板表面的部分（參照第2圖）。 第1層電極層14係於閘極電極7及層間絕緣膜1〇上， 設置成幾乎平坦者且與源極區域12接觸。由於層間絕緣膜 1〇填入溝渠5内，故源極電極14係設置成在層間絕緣膜 10上沒有什麼斷差而幾乎呈平坦狀。第1電極層14係於 設置在源極區域12上之n—型磊晶層2(通道層3)的表面往 318086 12 1304263 苐2方向延伸。 第2電極層15係於閘極電極7及層間絕緣膜丨〇上， 设置成幾乎平坦狀者且與主體區域13接觸。由於層間絕緣 膜10填入溝渠5内，故第2電極層15係設置成在層間絕 緣膜ίο上沒有什麼斷差而幾乎呈平坦狀。第2電極層15 係於設置在主體區域13上之n—型磊晶層2(通道層3)的表 面而主第2方向延伸。 ⑩ 第1電極層14及第2電極層15係交互配置，並往溝 渠5的延伸方向之正交方向延伸。第i電極層14及第2 電極層15各自以預定間距分離設置，並藉由設置在該等之 表面的表面保護膜（未圖示）來絕緣。還有，在以型半導體 基板1内面，係由金屬蒸鍍等方式形成汲極電極（未圖示）。 藉由將層間絕緣膜1〇填入溝渠5内，於閘極電極7 上方第1電極層14幾乎平坦地接觸源極區域12、第2電 極層15幾乎平坦地接觸主體區域13。第丨電極層14及第 _ 2電極層15係為各自以條紋狀分離形成的圖案，可減低分 別與源極區域12及主體區域13間的接觸不良。此外，可 防止因階梯覆蓋率（Step c〇verage)惡化產生之空隙和導 線接合（wire bond)時的裂紋，提高信賴性。 根據本實施型態，於一個晶片構成的MQSFET20中，可 各自個別控制施加至第1電極層14之電位及施加至第2 電極層15之電位。亦即，能個別控制源極區域12與主體 區域13(以下稱為背閘極區域）的電位關係。 也就是說，本實施型態的MOSFET20可由一個晶片來實 318086 13 1304263 現進行雙向電流路徑之切替的雙向切換元件，以下針對此 點來說明。 第3圖到第5圖係表示使用第1圖之M〇SFET2〇雙向切 換70件之情形時之一例的圖式。第3圖係表示二次電池的 保邊電路之電路圖。第4圖及第5圖係表示MOSFET20切斷 狀態情形時之概要圖。 如第3圖，保護電路22係備置有一個切換元件M0SFET > 20及控制電路24。 -MOSFET20係與二次電池21串聯連接，而進行二次電 池21之充電及放電。於M〇SFET2〇係形成有雙向的電流路 徑。 控制電路24係備置有一個施加控制信號到M〇SFET2〇 之閘極G的控制端子29。 控制電路24在充放電動作的情形中，將M〇SFET2〇切 換成導通’並因應M0SFET之源極s及汲極D之電位使電流 .朝二次電池21的充電方向及二次電池21的放電方向流 通。此外，例如於充放電動作的切斷時及充放電的切換時 等情形，MOSFET20變為切斷（不導通）狀態。此時雖然因内 藏在MOSFET20内的寄生二極體令產生與期望路徑相反的 電流路徑，但在本實施型態中係遮斷逆向的電流路徑。亦 即，在MOSFET20之切斷時，係將源極s或汲極D之任一較 低電位之端子連接於背閘極，而遮斷因寄生二極體所致之 電流路徑。 具體來說，充電的情形中，筏监、n 丄 丨月❿T ’係將汲極D設為電源電位 318086 14 1304263 • VDD、將源極S設為接地電位㈣。再於開極g施加預定電 位而將MOSFET20設為導通狀態，形成往充電方向（箭頭χ) 的電流路徑。 ' 接著，放電的情形中，係將汲極D設為接地電位GND、 將源極S設為電源電位VDD。再於閑極以加預定電位而 將MOSFET20設為導通狀態，形成往放電方向（箭頭γ)的電 流路控。 鲁.^照第4圖及第5圖’針對MOSFET20的切斷狀態作說 .明。第4圖係表示充電時將M〇SFET2〇切斷的情形、第5 圖係表示放電時將MOSFET20切斷的情形。尚且，第4圖及 第5圖係相當於第！圖（4)之c_c線斷面的概要圖。 如第4圖，由充電切換到放電時，或者是過充電時等， 在充電狀態下將肋邡灯2〇切斷的情形中，藉由控制電路 24讓源極s及背閘極BG短路。 、此日寸，將電源電位VDD施加至汲極電極i6(沒極D)， _並將第2電極層15(背閘極BG)及第i電極層14(源極s) 短路接地。由於汲極])係為電源電位VDD，在p型之通路 層與n(n+/n—)型之基板1〇〇中形成之寄生二極體將變為逆 偏壓狀態。也就是說，由於將藉由寄生二極體所致之電流 路徑予以遮斷，故可防止逆流。還有，汲極D係較背閘極 高之電位，不會引發寄生雙極（bip〇lar)動作。 另一方面，如第5圖，由放電切換到充電時，或者是 過放電時等，在放電狀態下將MOSFET20切斷的情形中，係 藉由控制電路24讓汲極D及背閘極BG短路。 318086 15 1304263 . 此k，將;及極電極16(汲極D)與第2電極層15(背閘 極BG)短路接地，並將電源電位VDD施加至第i電極層14 (源極S)。 θ 由於源極S係為電源電位VDD，寄生二極體係變為逆 偏壓狀態’ #由於藉由|生二極體所致之電流路徑係被遮 斷，故可防止逆流。還有，汲極D係與背閘極BG同電位， 不會引發寄生雙極動作。 φ —如此，於本實施型態中，係個別形成連接源極區域丄2 之第1電極層14及連接背閘極區域13之第2電極層15。 因此，係將各預定電位施加至第丨電極層14與第2電極層 15，而能用一個MOSFET20控制雙向之切換。 曰 接著，參照第6圖至第11圖，以n通道型的溝渠構造 之M0SFET為例來說明第一實施型態的絕緣閘極型導 裝置之製造方法。 第一步驟（第6圖）：係在一導電型半導體基板層積一 鲁導電型半導體層，並在半導體層表面形成逆導電型的通道 層之步驟。 製備妥於η+型矽半導體基板！層積η_型磊晶層2等之 基板100,而形成汲極區域！)!^。在表面形成氧化膜（未圖 示）後，蝕刻預定之通道層3部分之氧化膜而露出基板 表面。將此氧化膜作為遮罩而全面性地植入例如摻雜份量 (d〇Se)l.〇xl〇12至i3cm'加速能量5〇KeV&右的硼等後里 將之擴散而形成p型之厚度約左右的通道層3。 第二步驟（第7圖）：形成於半導體層表面往第i方向 318086 16 1304263 •延伸，並具有貫穿通道層之深度的溝渠之步驟。 首先，全面地藉由CVD法生成厚度3〇〇〇 A的無摻雜矽 酸鹽玻璃（NSG ; Non-doped Silicate Glass)之 CVD 氧化膜 4。之後藉由阻劑膜所形成之遮罩將CVD氧化膜4乾式蝕刻 (dry etching)而部分去除，而露出通道層3，再去除阻劑 膜。接著，將CVD氧化膜4作為遮罩而藉由CF系及ΗΒγ 系氣體將露出之基板1〇〇進行異方性乾式蝕刻，形成貫穿 •通道層3且達至η-型磊晶層2之深度約2 〇//m的溝渠& 將溝渠5的寬度設為〇 左右。 溝渠5係於通道層3表面圖案化成往第丨方向延伸之 條紋狀（參照第1圖（B))。 第三步驟（第8 ®):係在溝渠㈣形成雜絕緣膜之 步驟。 、 …騎假性（dUmmy)氧化而在溝渠5内壁及通道層3表面 形成氧化膜（未圖示）而將乾式韻刻之際的餘刻損宝 •(价hing damage)予以去除，之後，藉由㈣去ς該氧化 膜，做為溝渠蝕刻之遮罩的CVD氧化膜4。之後，形成閘 ，氧化膜6。亦即’將全面予以熱氧化而因應驅動電壓將 氧化膜6形成例如約3〇〇 A至7〇〇 A的厚度。 第四步驟（第9圖）：係形成埋入溝渠内的閘極電極之 全面:隹，高度雜質之多晶物叫仙⑽ I、、二：、、曲王面性附著無摻雜(η，d〇Pe)之多晶矽層， /儿、同/辰度雜質並將之擴散以謀求高導電率化（第9圖 318086 17 1304263 (A))。之後，以遮罩之方式將全面予以乾式蝕刻。此時， 係進行過蝕刻以便使多晶矽膜層7a的上部位於溝渠之I] 口部之下方，從而設置埋設於溝渠5之閘極電極=閘= 電極7上部係位於較溝渠5開口部下方8〇〇〇 A左右之位 置，使溝渠5開口部附近的溝渠5侧壁之問極氧化膜 (第 9 圖（B))。 ' 第五步驟（第10圖及第丨丨圖）：係在鄰接溝渠之通道 層表面形成一導電型之源極區域的步驟，以及在鄰接溝渠 與源極區域之通道層表面形成逆導電型之主體區域的步 驟。 設置露出源極區域的形成區域的通道層3表面之條紋 狀遮罩（未圖示）。全面地例如離子注入摻雜量5. 〇xi〇l5cm_2 左右的砷，而在通道層3表面摻雜n+型雜質並形成η型雜 質區域12’。其中，此處係相當於第2圖（Α)所示的斷面圖 (第 10 圖（Α))。 接者’ u又置條紋狀之遮罩（未圖不）以便露出形成主體 區域之區域的通道層3表面（未圖示）。其中，此處係相當 於第2圖（Β)所示的斷面圖。 全面地例如離子注入摻雜量5.0xl〇14cnf2左右的硼， 而在露出的通道層3表面形成p型雜質區域13,（第1〇圖 ⑻）。 全面地層積2000A左右的TEOS膜（未圖示）後，藉由 CVD法附著6000 A左右的硼磷矽玻璃（BPSG ; Boron Phosphorus Silicate Glass)層 10a 後，形成 S0G(Spin On 18 318086 13042631304263 IX. INSTRUCTIONS: TECHNICAL FIELD The present invention relates to an insulated gate type semiconductor device and a method of fabricating the same, and more particularly to a two-way bidirectional bi-gate by separating a back gate An insulated gate type semiconductor device that switches operation and a method of manufacturing the same. [Prior Art] Fig. 16 shows an n-channel type MOS field effect transistor (M0SFET) as an example of a conventional semiconductor device. Fig. 16 (Α) is a plan view, and Fig. 16 (Β) is a sectional view taken on line f-f of Fig. 16 (Α). Further, Fig. 16(A) omits the interlayer insulating film and shows the source electrode by a broken line. As shown in Fig. 16(A), the trench 44 is formed in a stripe shape on the surface of the substrate, and the source region 48 and the body region 49 are disposed adjacent to the trench 44. The trench 44, the source region 48, and the body tegion 49 extend in the same direction. • As shown in Fig. 16(B), an n-channel type MOSFET is formed by laminating an n-type telecrystal (yin taxiai) layer on an n+ type semiconductor substrate 41 and providing a drain region DR, and a P-type channel is provided thereon. Layer 43. Further, a trench 44 extending from the channel layer 43 to the n-type epitaxial layer is provided, and the inner wall of the trench 44 is covered with a gate oxide film 45, and a gate electrode 46 is buried in the trench 44. An n+ type source region 48 is formed on the surface of the channel layer 43 adjacent to the trench 44, and a surface of the channel layer 43 between the source regions 48 of the adjacent two cells (cen) forms a P+ type body region 49. The trench 44 is covered by an interlayer, a peripheral film 5〇, and a contact source region 48 and a body region 49 318086 6 1304263, a source electrode 5 and a source electrode 51 are continuously disposed in the source region 48, and the body region 49 is provided. on. Further, the electrode electrode 52 is provided on the inner surface of the substrate. The MOSFET described above is used, for example, in a protection circuit device for performing battery management for charging and discharging a secondary battery. Fig. 4 is a circuit diagram showing an example of a protection circuit device. The primary battery LiB is connected in series with two M〇SFETs Q1 and Q2. M〇sfet卯 φ and Q2 are commonly connected to the drain D, and their respective source s are arranged at both ends, and the individual gate G is connected to the control circuit 1C. The control circuit 1C detects the voltage of the secondary battery LiB while performing two (four) deletion (10) and on/off (10)/0FF) control to protect the secondary battery ub from overcharging, overdischarging, and load shorting. (Refer to Patent Document D. > Control circuit 1 (: detects the battery voltage, when the detected voltage is at the lowest set voltage, _ΕΤ(10) is switched to cut (not guided) to prevent two In addition, when the detected electric charge is lower than the minimum set voltage, M〇smQ1 is switched to be cut off to prevent overdischarge of the secondary battery UB. Patent Document 1: 曰 National Patent Publication No. 2002_11825 [Problem to be Solved by the Invention] As shown in Fig. 16, a conventional body τ, a body region 49 and a source 4 48 are commonly connected to a source electrode 5, and the potentials are It is fixed ^ in the case of using the double-switch 4 as a two-way switch 4, the ship is connected in series, switching each source electrode 51, and forming a bidirectional 318086 7 1304263 current path. This is because, as shown in Figure 17, the MOSFET is built in There is a parasitic diode PD. That is, in In the M 〇 sm in which the potential of the body region 49 (that is, the back gate region) and the source region 48 are fixed, the forward operation of the parasitic diode 卯 at the time of cutting is unavoidable. Therefore, when the MOSFET is turned off It must be controlled so that there is no current path that is not formed due to the parasitic diode PD. σ For this, as shown in Figure 17, two identical number of cells, the same wafer size of the MGSFET are connected in series, and by The control circuit controls the μ 〇 Q Q Q2 and the respective parasitic diodes pD, thereby forming a desired current path. However, in order to reduce the on-resistance (〇n resistance) in the MOSFET, it is necessary to have a certain unit The number and the size of the wafer. In addition, the human battery has become very popular as a battery for carrying the terminal device. With the miniaturization of the portable terminal device, the requirements for miniaturization of the protection circuit are becoming higher and higher. The protection circuit in which two M〇SFETs Q1 and Q2 are connected in series has its limits in response to this requirement. (Means for Solving the Problem) The present invention has been developed in view of related problems, and the first means for solving the problem is a drain region of a conductive semiconductor layer laminated on a conductive semiconductor substrate; a reverse conductive channel layer provided on a surface of the semiconductor layer; extending in a second direction on the surface of the semiconductor layer; a trench having a depth of a layer; a gate insulating film disposed on an inner wall of the trench; a gate electrode filled in the trench; disposed on the surface of the channel 318086 8 1304263 and adjacent to the trench a source region; a reverse conductivity type body region disposed on the surface of the channel layer adjacent to the trench and the source region; and a working electrode extending in the second direction on the surface of the semiconductor layer a layer; and a second electrode layer extending in the second direction on the surface of the semiconductor layer provided on the second body region. A second means for solving the problem of the present invention includes: a step of laminating a conductive semiconductor layer on a conductive type semiconductor substrate, and forming a reverse conductive type channel layer on the surface of the semiconductor layer; forming the semiconductor a step 2 of the trench extending in the first direction and having a depth penetrating the via layer; a step of forming a gate insulating film on the inner wall of the trench; and a step of forming a gate electrode filled in the trench; a step of forming a conductive source region adjacent to the trench on the surface of the channel layer; forming a surface of the channel layer adjacent to the trench and the reverse conductivity type of the source region; forming the source a step of contacting a pole region in the second direction in the semiconductor layer, and a step of forming a second electrode layer that is in contact with the body region and extends in the second direction on the surface of the semiconductor layer. (Effect of the Invention) According to the present invention, first, the source electrode and the drain electrode can be individually connected to the body region (the back gate region can be used to switch the source region and the back region) by using the hall (4). (4) The state of short-circuit between the secret region and the back gate region. Thereby, the unnecessary current path (relative to the desired current path) due to the parasitic diode formed by the parasitic diode can be interrupted when the MOSFET is turned off. It is the opposite current path. Therefore, a MOSFET can be used to switch the bidirectional current path' and prevent current from flowing back. Second, by filling the interlayer insulating film into the trench, the IGBT layer and the The surface of the substrate that is in contact with the electrode layer is flattened, that is, the step coverage phenomenon caused by the interlayer insulating film is not caused by the formation of the first electrode layer and the second electrode layer in a stripe shape. Therefore, it is possible to ensure sufficient high adhesion with individual source regions and body regions. '' Second, although in the source region 12, the body region 丨3, the interlayer insulating film Three masks are used in the step, and only one slice is required for the mask alignment offset, that is, compared with the mask offset which is considered in the past three steps, for example, The distance between the trenches is close to the groove. Therefore, the expansion of the operating area is possible. Therefore, the on-resistance can be reduced as long as the same wafer size is used, and the wafer size can be reduced as long as the number of cells is the same. Fourthly, a device capable of bidirectional switching can be realized by using a wafer of a MOSFET, for example, when it is used in a protection circuit of a secondary battery, etc., the number of parts can be reduced and the device can be miniaturized. [Embodiment] 1 to 15 and an embodiment of the present invention will be described using m〇sfet of an n-channel type trench structure as an example. First, an implementation form of the second embodiment will be described with reference to Figs. 1 to 5D. 318086 10 1304263 - The figure is a perspective view showing the MOSFET. Fig. 1(A) shows a pattern in which the i-th and second electrode layers are arranged, and Fig. 1(B) shows a first and second electrode layer in a broken line. The pattern of the area. In addition, the second picture It is a sectional view, a second figure (A) is a sectional view of the a_a line of the first figure (a), and a second figure (B) is a section of the bb line of the first figure (A). The MOSFET 20 is composed of a semiconductor substrate i, a semiconductor layer 2, a channel layer 3, a 冓, a 5 gate, a 缘e edge film 6, a gate electrode 7, a source region 12, a body region _ domain 13, and an interlayer insulating film. 1〇, the working electrode layer 14, the second electrode layer 15, and the drain electrode 16. The germanium substrate 100 is formed by laminating an n-type epitaxial layer 2 on a n+ type germanium semiconductor substrate i and providing a drain electrode. In the region DR, a channel layer 3 which is a P-type impurity region is provided on the surface of the drain region (10). The trench 5 is provided to penetrate the channel layer 3 and reach the depth of the drain region 2. Further, a pattern on the surface of the η-type epitaxial layer 2 (channel layer 3) is formed by extending in a stripe shape in the first direction. (Refer to the drawing (Β)). - #照图2' The inner wall of the trench 5 is covered with a gate insulating film 6 corresponding to the film thickness of the driving voltage. The gate electrode 7 is a polysilicon which is introduced into the trench 5 by introducing impurities and reducing the resistance. The upper end of the gate electrode 7 is disposed lower than the opening portion of the trench 5 (i.e., the surface of the channel layer 3) by a few U. The type of trench source region 12 is provided by diffusing a high concentration of η impurities so as to be adjacent to the trench 5. The source region 12 is disposed on the surface of the channel layer 3 around the opening of the trench 5, and is disposed to extend in the depth direction of the trench 5 along the sidewall of the trench to reach the depth of the gate electrode 7. In the cross section shown in Fig. 2, 318086 11 1304263 (A), only the source region 12 is disposed between adjacent trenches 5. Further, the source regions 丄2 adjacent to each other in the first direction of the groove 5 are separated by a predetermined pitch, and the body regions 13 are disposed between the source regions. That is, one source region 12 is adjacent to the two body regions 13 disposed along the same side wall of the trench 5 (please refer to Figure 〇)). The main body region 13 is provided by diffusing a high-concentration p-type impurity so as to be adjacent to the trench 5. The body region 13 is provided on the surface of the channel layer 3 around the opening of the trench 5. In Figure 2. In the cross section shown, only the main body region 丨3 is disposed between adjacent trenches 5. Further, the body regions 丨3 adjacent to each other in the first direction along the extending direction of the trench 5 are disposed apart at a predetermined pitch, and the source regions 12 are disposed between the body regions. That is to say, one main body region 13 is connected to the two source regions 12 of the same side wall of the stone trench 5 (Fig. 1 (b)). That is, although only two source regions 12 and one body region are disposed in the i-th diagram, the source region 12 and the body region 丄3 are alternately arranged. • The interlayer insulating film 1 is filled into the trench 5 as a whole. The upper end (surface) of the gate electrode 7 is located about several thousand below the surface of the channel layer 3, and the interlayer insulating film 10 is completely embedded in the trench 5 from the upper end of the gate electrode 7 to the surface of the channel layer 3, without A portion that protrudes from the surface of the substrate (see Fig. 2). The first electrode layer 14 is formed on the gate electrode 7 and the interlayer insulating film 1A, and is provided to be almost flat and in contact with the source region 12. Since the interlayer insulating film 1 is filled in the trench 5, the source electrode 14 is provided so as to have almost no unevenness on the interlayer insulating film 10 and is almost flat. The first electrode layer 14 is extended in the direction of 318086 12 1304263 苐 2 by the surface of the n-type epitaxial layer 2 (channel layer 3) provided on the source region 12. The second electrode layer 15 is provided on the gate electrode 7 and the interlayer insulating film, and is provided in a substantially flat shape and is in contact with the body region 13. Since the interlayer insulating film 10 is filled in the trench 5, the second electrode layer 15 is provided so as to have almost no unevenness on the interlayer insulating film ίο. The second electrode layer 15 is formed on the surface of the n-type epitaxial layer 2 (channel layer 3) provided on the main body region 13 and extends in the main second direction. The first electrode layer 14 and the second electrode layer 15 are alternately arranged and extend in the direction orthogonal to the direction in which the trenches 5 extend. The i-th electrode layer 14 and the second electrode layer 15 are each provided at a predetermined pitch and insulated by a surface protective film (not shown) provided on the surfaces. Further, a drain electrode (not shown) is formed on the inner surface of the semiconductor substrate 1 by metal deposition or the like. By filling the interlayer insulating film 1 into the trench 5, the first electrode layer 14 is almost in flat contact with the source region 12 above the gate electrode 7, and the second electrode layer 15 is almost in flat contact with the body region 13. The second electrode layer 14 and the second electrode layer 15 are formed in a stripe shape, and the contact failure between the source electrode region 12 and the body region 13 can be reduced. Further, it is possible to prevent cracks generated during the deterioration of the step coverage and the wire bond, and to improve the reliability. According to this embodiment, in the MQSFET 20 composed of one wafer, the potential applied to the first electrode layer 14 and the potential applied to the second electrode layer 15 can be individually controlled. That is, the potential relationship between the source region 12 and the body region 13 (hereinafter referred to as the back gate region) can be individually controlled. That is to say, the MOSFET 20 of the present embodiment can be implemented by a single chip to implement a bidirectional switching element for switching a bidirectional current path, which will be described below. Figs. 3 to 5 are views showing an example of a case where 70 pieces of the M〇SFET 2 of Fig. 1 are used for bidirectional switching. Fig. 3 is a circuit diagram showing a margin maintaining circuit of a secondary battery. Fig. 4 and Fig. 5 are schematic views showing the state in which the MOSFET 20 is turned off. As shown in Fig. 3, the protection circuit 22 is provided with a switching element MOSFET > 20 and a control circuit 24. The MOSFET 20 is connected in series with the secondary battery 21 to charge and discharge the secondary battery 21. A bidirectional current path is formed in the M〇SFET2 system. The control circuit 24 is provided with a control terminal 29 for applying a control signal to the gate G of the M 〇 SFET 2 。. In the case of the charge and discharge operation, the control circuit 24 switches the M〇SFET 2 成 to be turned on and reacts the current to the charge of the secondary battery 21 and the secondary battery 21 in response to the potential of the source s and the drain D of the MOSFET. Circulate in the direction of discharge. Further, for example, in the case of the cutting of the charge and discharge operation and the switching of the charge and discharge, the MOSFET 20 is turned off (non-conducting). At this time, although the parasitic diode built in the MOSFET 20 causes a current path opposite to the desired path, in the present embodiment, the reverse current path is blocked. That is, when the MOSFET 20 is turned off, a terminal having a lower potential of either the source s or the drain D is connected to the back gate, and the current path due to the parasitic diode is blocked. Specifically, in the case of charging, the voltage is set to the power supply potential 318086 14 1304263 • VDD, and the source S is set to the ground potential (4). Further, a predetermined potential is applied to the open electrode g to turn the MOSFET 20 into an on state, thereby forming a current path to the charging direction (arrow χ). Then, in the case of discharging, the drain D is set to the ground potential GND, and the source S is set to the power supply potential VDD. Further, the MOSFET 20 is turned on by adding a predetermined potential to the idle electrode, and a current path to the discharge direction (arrow γ) is formed. Lu. Fig. 4 and Fig. 5' are for the cut-off state of the MOSFET 20. Fig. 4 shows a case where the M〇SFET 2 turns off during charging, and a fifth figure shows a case where the MOSFET 20 is turned off during discharge. Moreover, Figures 4 and 5 are equivalent to the first! A schematic view of the c_c line section of Fig. 4 (4). As shown in Fig. 4, in the case where the rib lamp 2 is turned off in the charged state when the charging is switched to the discharge, or when the battery is overcharged, the source s and the back gate BG are short-circuited by the control circuit 24. . At this time, the power supply potential VDD is applied to the drain electrode i6 (no electrode D), and the second electrode layer 15 (back gate BG) and the i-th electrode layer 14 (source s) are short-circuited to ground. Since the drain electrode] is the power supply potential VDD, the parasitic diode formed in the p-type via layer and the n (n+/n-) type substrate 1A will be in an inverted bias state. That is, since the current path by the parasitic diode is blocked, backflow can be prevented. Also, the bungee D system has a higher potential than the back gate and does not cause a parasitic bipolar action. On the other hand, as shown in Fig. 5, in the case where the MOSFET 20 is turned off in the discharged state when the discharge is switched to the charging or during the overdischarge, the gate D and the back gate BG are controlled by the control circuit 24. Short circuit. 318086 15 1304263 . This k, and the electrode electrode 16 (dip D) and the second electrode layer 15 (back gate BG) are short-circuited to ground, and the power supply potential VDD is applied to the i-th electrode layer 14 (source S). . θ Since the source S is the power supply potential VDD, the parasitic two-pole system becomes the reverse bias state. # Since the current path by the |diode is blocked, backflow can be prevented. Also, the drain D system has the same potential as the back gate BG, and does not cause parasitic bipolar action. Φ— As described above, in the present embodiment, the first electrode layer 14 that connects the source region 丄2 and the second electrode layer 15 that connects the back gate region 13 are formed separately. Therefore, each predetermined potential is applied to the second electrode layer 14 and the second electrode layer 15, and switching between the two directions can be controlled by one MOSFET 20. Next, referring to Fig. 6 to Fig. 11, a method of manufacturing the insulated gate type guide of the first embodiment will be described by taking an MOSFET of an n-channel type trench structure as an example. The first step (Fig. 6) is a step of laminating a Lu conductive type semiconductor layer on a conductive type semiconductor substrate and forming a reverse conductive type channel layer on the surface of the semiconductor layer. Prepare the η+ type germanium semiconductor substrate! The substrate 100 of the n-type epitaxial layer 2 or the like is laminated to form a drain region! )!^. After an oxide film (not shown) is formed on the surface, an oxide film of a portion of the predetermined channel layer 3 is etched to expose the surface of the substrate. The oxide film is implanted as a mask in a comprehensive manner, for example, a doping amount (d〇Se) l.〇xl〇12 to i3cm' acceleration energy 5〇KeV&; right boron is diffused to form a p-type The thickness of the channel layer 3 is about the left and right. The second step (Fig. 7): a step of forming a trench extending from the surface of the semiconductor layer to the ith direction 318086 16 1304263 and having a depth penetrating the channel layer. First, a CVD oxide film 4 of a non-doped silicate glass (NSG) having a thickness of 3 Å is formed by a CVD method. Thereafter, the CVD oxide film 4 is partially dry-etched by a mask formed of a resist film to expose the channel layer 3, and then the resist film is removed. Then, the CVD oxide film 4 is used as a mask, and the exposed substrate 1 is subjected to anisotropic dry etching by a CF system and a ΗΒγ-based gas to form a through-channel layer 3 and reaches the η-type epitaxial layer 2 Ditch & depth of about 2 〇 / / m The width of the ditch 5 is set to about 〇. The trench 5 is patterned on the surface of the channel layer 3 in a stripe shape extending in the second direction (see Fig. 1(B)). The third step (8th ®): the step of forming a hetero-insulating film in the trench (4). , ... dUmmy oxidation, and an oxide film (not shown) is formed on the inner wall of the trench 5 and the surface of the channel layer 3, and the residual damage of the dry rhyme is removed, and then The CVD oxide film 4 is used as a mask for trench etching by (d) removing the oxide film. Thereafter, a gate and an oxide film 6 are formed. That is, the thickness of the oxide film 6 is formed, for example, by about 3 Å to 7 Å in response to the driving voltage. The fourth step (Fig. 9): is to form a comprehensive electrode of the gate electrode buried in the trench: 隹, the polycrystalline matter of high impurity is called Xian (10) I, 2:, and the curvature of the surface is undoped (η , polyphosphonium layer of d〇Pe), /child, same/minus impurity and diffused to achieve high conductivity (Fig. 318086 17 1304263 (A)). Thereafter, the mask is completely dry etched. At this time, etching is performed so that the upper portion of the polysilicon film layer 7a is located below the I] mouth portion of the trench, thereby providing the gate electrode buried in the trench 5 = gate = the upper portion of the electrode 7 is located below the opening of the trench 5 The position of the left and right sides of the 〇〇〇A is such that the side oxide film of the side wall of the trench 5 near the opening of the trench 5 is formed (Fig. 9(B)). 'The fifth step (Fig. 10 and Fig. 3): a step of forming a conductive source region on the surface of the channel layer adjacent to the trench, and forming a reverse conductivity type on the surface of the channel layer adjacent to the trench and the source region The steps of the body area. A stripe mask (not shown) on the surface of the channel layer 3 exposing the formation region of the source region is provided. For example, arsenic is doped in an amount of about 5. 〇 xi 〇 5 cm 2 , and n + -type impurities are doped on the surface of the channel layer 3 to form an n-type impurity region 12'. Here, it is equivalent to the sectional view shown in Fig. 2 (Α) (Fig. 10 (Α)). The connector 'u is again provided with a stripe-shaped mask (not shown) to expose the surface of the channel layer 3 (not shown) forming the region of the body region. Here, it is equivalent to the sectional view shown in Fig. 2 (Β). For example, boron is implanted in a doping amount of about 5.0 x 1 〇 14 cnf 2 , and a p-type impurity region 13 is formed on the surface of the exposed channel layer 3 (Fig. 1 (8)). After a TEOS film (not shown) of about 2000 A is laminated, a layer of 10a of Boron Phosphorus Silicate Glass (BPSG) is attached by a CVD method to form a S0G (Spin On 18 318086 1304263).
Glass)層 10b 〇 之後，為了平坦化而施行熱處理，藉此，擴散n型雜 質區域12及p型雜質區域13，。再者，於相當第2圖q) 的斷面，將η型的源極區域12在通道層3表面形成。源極 區域12係經介閘極絕緣膜6鄰接閘極電極7 (第11圖（a ))° 同樣於相當第2圖（B)的斷面，將p型的主體區域13 在通道層3表面形成。主體區域13係經介閘極絕緣膜6 鄰接閘極電極7(第11圖（B))。 、 丄主體區域13及源極區域12係沿著溝渠5的相同側壁 父互配置。此外，正交於溝渠5延伸之第丨方向之第2方 向中，在相鄰的溝渠5之間，僅配置源極區域丨2或者主體 區域13其中一方（參照第1圖（B))。 之後將王面予以回姓（etch back)並露出通道層3 表面，形成填入溝渠5内的層間絕緣膜1〇。於此，在回蝕 f際，為防止膜殘留，較宜進行少許之過蝕刻。具體來說， #採用終點檢出而钱刻層間絕緣膜1〇直至露出通道層3表面 的石夕為止，之後再進一步進行過钱刻。藉在匕，層間絕緣膜 1〇在閘極電極7上方完全埋設於溝渠5内，由於沒有突出 到基板100表面，因此層間絕緣膜1〇形成後的基板ι〇〇 表面幾乎變得很平坦。 刀根據上述於本實施^{態中，不需設置遮罩就可形成層 間、、、巴緣膜1 〇。在此，雖然係顯示相當於第2圖（Α)的斷面， 仁在相當於第2圖（Β)的斷面同樣埋設層間絕緣膜1〇於溝 渠5内（第11圖（C))。 318086 19 1304263 ， 在以使’如第16圖，係將源極區域48及主體區域49 /、 ^ 44平行形成。但在層間絕緣膜5〇的形成步驟、於 源極區域48及主體區域49的三個步驟中係需要三片遮 罩，在溝渠44〜源極區域48及溝渠44_主體區域49的位 子準日守就須考慮所使用之三片份的遮罩對準偏移。 ^ 但是’在本實施型態中，源極區域12及主體區域13 系相對於溝渠5的延伸方向以垂直延伸之方式形成。因 鲁_此，在層間絕緣膜1〇形成步驟、源極區域12及主體區域 • 13形成步驟中，儘管需要三片料，亦僅需考慮一片份的 遮罩對準偏移。 ^也就是說，與習知相比，可以將為了考慮到遮罩的對 準偏移而予以確保的溝渠間距離予以接近。如此，即能擴 大動作面積。藉此，可達成只要是相同的晶片尺寸就能減 低‘通電阻、只要是相同的單元數就能將晶片尺寸縮小化。 尚且，也可替換源極區域12與主體區域13的形成順 •序。 第六步驟（第2圖（A)):係形成接觸源極區域、於上述 半導體層表面往第2方向延伸的第丨電極層之步驟。 以濺鍍裝置全面附著鋁，並圖案化成所需的形狀，形 成接觸源極區域12的第1電極層14。第！電極層14係設 置在源極區域12上，於通道層3表面以相對於溝渠5的延 伸方面為垂直方向的第2方向延伸。 在本實施型態中，層間絕緣膜10係填入於閘極電極7 上，由於能形成幾乎平坦的第丨電極層14，因此可改善階 318086 20 1304263 形覆蓋率（step coverage)。 第七步驟（第2圖（B)):係形成接觸主體區域、於半導 體層表面往第2方向延伸的第2電極層之步驟。 以濺錢裝置全面附著紹’並圖案化成所需的形狀，形 成接觸主體區域13的第2電極層15。第2電極層Η係設 置在主體區域13上，於通道層3表面往第2方向延伸。第 2電極層15與第1電極層14係平行地分離配置。 .在本實施型態中，層間絕緣膜1G係填人於閘極電極7 上’由+於能形成幾乎平坦的第2電極層15，因此可改 形覆蓋率。 二照第12圖至第15圖，說明本發明的第2實施型態。 处弟12圖係表示第2實施型態構造之圖式，第12圖⑴ 為斜視圖、第12圖⑻係為第12圖（A)的d-d線斷面圖、 第12圖⑹係為第12圖（_以_面圖。= '圖⑷以虛線表示第i電極層14及第 所： 置的區域。 曰^ W配 第2貝轭型悲係為不將層間絕緣膜μ 而是突出在通道層3表面的構造。 “5内，After the layer 10b 〇 is subjected to heat treatment for planarization, the n-type impurity region 12 and the p-type impurity region 13 are diffused. Further, the n-type source region 12 is formed on the surface of the channel layer 3 in a cross section corresponding to FIG. 2(q). The source region 12 is adjacent to the gate electrode 7 via the gate insulating film 6 (Fig. 11(a)). Similarly to the section corresponding to Fig. 2(B), the p-type body region 13 is in the channel layer 3. The surface is formed. The body region 13 is adjacent to the gate electrode 7 via the gate insulating film 6 (Fig. 11(B)). The 丄 body region 13 and the source region 12 are arranged along the same sidewall of the trench 5. Further, in the second direction orthogonal to the second direction in which the trench 5 extends, only one of the source region 丨2 or the main body region 13 is disposed between the adjacent trenches 5 (see Fig. 1(B)). Thereafter, the king face is returned to the etch back and the surface of the channel layer 3 is exposed to form an interlayer insulating film 1 填 filled in the trench 5. Here, in the etch back, in order to prevent the film from remaining, it is preferable to perform a little over-etching. Specifically, # endpoint detection is performed and the interlayer insulating film is engraved until the surface of the channel layer 3 is exposed, and then further engraved. By the 匕, the interlayer insulating film 1 完全 is completely buried in the trench 5 above the gate electrode 7, and since it does not protrude to the surface of the substrate 100, the surface of the substrate ITO after the formation of the interlayer insulating film 1 几乎 is almost flat. According to the above-described embodiment, the knives can form the interlayer, and the rim film 1 不 without providing a mask. Here, although the cross section corresponding to Fig. 2 (Α) is displayed, the interlayer insulating film 1 is embedded in the trench 5 in the same section as the second figure (Β) (Fig. 11(C)) . 318086 19 1304263, in the same manner as in Fig. 16, the source region 48 and the body regions 49 /, ^ 44 are formed in parallel. However, in the three steps of forming the interlayer insulating film 5, in the source region 48 and the body region 49, three masks are required, and the positions of the trench 44 to the source region 48 and the trench 44_body region 49 are The day guard must consider the mask alignment offset of the three pieces used. ^ However, in the present embodiment, the source region 12 and the body region 13 are formed to extend vertically with respect to the extending direction of the trench 5. Since the interlayer insulating film 1 〇 forming step, the source region 12 and the body region 13 are formed, it is only necessary to consider the mask alignment offset of one sheet in spite of the need for three sheets. ^ That is to say, the distance between the trenches to be ensured in consideration of the alignment offset of the mask can be approximated compared with the conventional one. In this way, the operating area can be enlarged. Thereby, it is possible to reduce the "on-resistance" as long as the same wafer size, and the wafer size can be reduced as long as the number of cells is the same. Still, the formation of the source region 12 and the body region 13 can be replaced. The sixth step (Fig. 2(A)) is a step of forming a contact source region and a second electrode layer extending in the second direction on the surface of the semiconductor layer. The aluminum is completely adhered by a sputtering apparatus and patterned into a desired shape to form the first electrode layer 14 contacting the source region 12. The first! The electrode layer 14 is provided on the source region 12, and extends on the surface of the channel layer 3 in a second direction perpendicular to the direction in which the trench 5 extends. In the present embodiment, the interlayer insulating film 10 is filled in the gate electrode 7, and since the almost flat second electrode layer 14 can be formed, the step coverage of the step 318086 20 1304263 can be improved. The seventh step (Fig. 2(B)) is a step of forming a contact electrode region and a second electrode layer extending in the second direction on the surface of the semiconductor layer. The second electrode layer 15 contacting the body region 13 is formed by being integrally attached to the desired shape by a splash device. The second electrode layer is provided on the body region 13 and extends in the second direction on the surface of the channel layer 3. The second electrode layer 15 is disposed apart from the first electrode layer 14 in parallel. In the present embodiment, the interlayer insulating film 1G is filled in the gate electrode 7 by + to form the almost flat second electrode layer 15, so that the coverage can be modified. A second embodiment of the present invention will be described with reference to Figs. 12 to 15 . Fig. 12 is a diagram showing the structure of the second embodiment. Fig. 12 (1) is a perspective view, Fig. 12 (8) is a dd line sectional view of Fig. 12 (A), and Fig. 12 (6) is a 12 ( _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The structure on the surface of the channel layer 3. "5,
=即’埋設閘極電極7直至溝渠5的開口部附近，並 沒置曰間絕緣膜1G以覆蓋住開極電極7 周狀源極區域12或者主體區域13的—部份在溝U 道声3夺面吟屮夕 電極層15係設置成覆蓋在於通 β 乂大 層間絕緣膜10的周圍，並接觸在居門π 緣膜10之間露出的源極區域12或者主體區域=層此^ 318086 21 1304263 第12圖(A)中，於平面圖案中雖然以 … 14與第2電極層15的配置區域，”γ表：弟！電極層 ⑻、(〇覆蓋基板_表面與層間絕；1G t第12圖 係因與第1實施L㈣省略說明。、、他的構造 參照第13圖至望1 ς、 施型態MGSFET的製造方法。η通道型為例說明第2實 步驟第4步驟（第13圖）：係形成填入溝渠内的閘極電極之 全：地堆積含有高濃度雜質的多晶矽層 入 雜的多晶石夕層’再沉積並擴散高濃度雜質: ί求南V電率化(第13圖⑴)。之後，全面以無遮罩之方 ，對王面進仃乾絲刻。藉此，形成埋設在溝渠5、内的問 極電極7。閘極電極7的表面係位於溝渠5的 φ (弟 13 圖（B))。 第5步驟U 14圖及第15圖）：係在鄰接溝渠的通道 層表面形成一導電型源極區域之步驟，以及在鄰接溝渠及 源極區域的通道層表面形成逆導電型的主體區域之步驟。 设置露出源極區域的形成區域之條紋狀遮罩，全面地 例如離子注入摻雜量5· Oxl 015cnf2左右的砷，而在通道層3 表面推雜n+型雜質並形成一導電型雜質區域12,。這裡相 當於第12圖（B)所示的斷面圖（第14圖（A))。 接著，設置條紋狀遮罩（未圖示）以便露出形成主體區 318086 22 1304263 域之預定的通道層3表面。這裡相當於第12圖（c)所示的 斷面圖。 全面地例如離子注入摻雜量5.0xl〇14cm-2左右的硼， 而在露出的通道層3表面形成逆導電型雜質區域13,（第14 圖（B)) 〇 之後，全面地層積2000 A左右的TE0S膜（未圖示）後， 藉由 CVD 法附著 6000 A 左右的 BPSG(Boron Ph〇sph〇rus 厂 Silicate Glass)層 l〇a 後，形成 S0G(Spin 〇n Glass)層 10b，並施行用於平坦化之熱處理（goo它左右）。 藉著此熱處理，如第15圖（A)，擴散一導電型雜質區 域12’的雜質，而在通道層3表面形成n型的源極區域12。 同時如第15圖（Β)，擴散逆導電型雜質區域13，的雜質， 在通道層3表面形成ρ型主體區域13。 源極區域12及主體區域13係經介閘極絕緣膜6鄰接 閘極電極7。 一主體區域13及源極區域12係沿著溝渠5的相同侧壁= that is, 'the gate electrode 7 is buried until the vicinity of the opening of the trench 5, and the interlayer insulating film 1G is not disposed to cover the peripheral source region 12 of the open electrode 7 or the portion of the body region 13 The three-faced electrode layer 15 is disposed so as to cover the periphery of the large interlayer insulating film 10, and is in contact with the source region 12 exposed between the gate π-edge film 10 or the body region=layer. 21 1304263 In Fig. 12(A), in the planar pattern, the arrangement area of the 14th and second electrode layers 15 is "γ: Mother! Electrode layer (8), (〇 〇 基板 _ _ surface and interlayer ;; 1G t Fig. 12 is a description omitted from the first embodiment L (d), and the structure thereof is referred to Fig. 13 to Fig. 1 and the manufacturing method of the MGSFET. The n channel type is taken as an example to explain the second step (the fourth step). Fig. 13): Forming the gate electrode filled in the trench: the polycrystalline layer containing the high concentration of impurities is deposited on the polycrystalline layer of the polycrystalline layer to redeposit and diffuse the high concentration of impurities: (Fig. 13 (1)). After that, the surface of the king’s face is inscribed in a full-faced manner. The electrode electrode 7 is embedded in the trench 5. The surface of the gate electrode 7 is located at the φ of the trench 5 (different figure 13 (B)). Step 5 U 14 and FIG. 15): adjacent to the trench a step of forming a conductive source region on the surface of the channel layer, and a step of forming a reverse conductivity type body region on a surface of the channel layer adjacent to the trench and the source region. A stripe mask covering the formation region of the source region is provided, comprehensive For example, ion implantation of arsenic having a doping amount of about 5·0x1 015cnf2 is performed, and n+ type impurities are pushed on the surface of the channel layer 3 to form a conductive impurity region 12, which corresponds to the section shown in Fig. 12(B). Fig. 14(A). Next, a stripe-shaped mask (not shown) is provided to expose the surface of the predetermined channel layer 3 forming the domain of the body region 318086 22 1304263. This is equivalent to that shown in Fig. 12(c). A cross-sectional view of, for example, ion implantation of boron having a doping amount of 5.0 x 1 〇 14 cm -2 , and forming a reverse conductive impurity region 13 on the surface of the exposed channel layer 3 (Fig. 14 (B)) After fully stratifying the TE0S film (not shown) of about 2000 A, After the CVD method is applied to the BPSG (Boron Ph〇sph〇rus Silicate Glass) layer l〇a of about 6000 A, a S0G (Spin 〇n Glass) layer 10b is formed, and heat treatment for planarization is performed (goo is left and right). By this heat treatment, as shown in Fig. 15 (A), the impurity of the one-electrode-type impurity region 12' is diffused, and the n-type source region 12 is formed on the surface of the channel layer 3. At the same time, as shown in Fig. 15, (D), the diffusion inverse The impurity of the conductive type impurity region 13 forms a p-type body region 13 on the surface of the channel layer 3. The source region 12 and the body region 13 are adjacent to the gate electrode 7 via the gate insulating film 6. A body region 13 and a source region 12 are along the same sidewall of the trench 5
之後，設置由新的阻劑所形成之遮罩（未圖示），蝕After that, a mask (not shown) formed by a new resist is provided, which is etched.
上（第15(C)圖）。尚且， 接溝渠5之源極區域12的一部份 雖省略圖示，但在主體區域13上 318086 23 1304263 也是相同。 之後的步驟，因與第1的實施型態相同，故省略說明。 尚且’如同上述，雖在本發明的實施型態中是以η通 道型M0SFET為例來說明，但也適用於逆導電型之ρ通道型 M0SFET。還有，同樣也可實施在將基板ι〇〇與逆導電型的 半導體層設置在基板1 〇 0下方而將雙極電晶體與功率 M0SFET以單片（mon〇iithic)方式複合化在一個晶片内的 絕緣閘雙極電晶體（IGBT ; Insuiated Gate Bipolar Transistor) ° 【圖式簡單說明】 弟1圖（A )及（B )係說明本發明之絕緣閘極型半導體裝 置的斜視圖。 弟2圖（A )及（B )係說明本發明之絕緣閘極型半導體裝 置的斷面圖。 第3圖係說明本發明之絕緣閘極型半導體裝置的電路 • 圖。 弟4圖係说明本發明之絕緣閘極型半導體裝置的電路 概要圖。 第5圖係說明本發明之絕緣閘極型半導體裝置的電路 概要圖。 第6圖係說明本發明之絕緣閘極型半導體裝置之製造 方法的斷面圖。 第7圖係說明本發明之絕緣閘極型半導體裝置之製造 方法的斷面圖。 318086 24 1304263 第8圖係說明本發明之絕緣閘極型半導體裝置之製造 方法的斷面圖。 第9圖（A)及（B)係說明本發明之絕緣閘極型半導體裝 置之製造方法的斷面圖。 第10圖（A)及（B)係說明本發明之絕緣閘極型半導體 裝置之製造方法的斷面圖。 第11圖（A)至（C)係說明本發明之絕緣閘極型半導體 裝置之製造方法的斷面圖。 第12圖係說明本發明之絕緣閘極型半導體裝置的（A) 電路圖、（B)斷面圖、（C)斷面圖。 第13圖（A)及（B)係說明本發明之絕緣閘極型半導體 裝置之製造方法的斷面圖。 裝置之製造方法的斷面圖。 第14圖（A)及（B)係說明本發明之絕緣閘極型半導體 _裝置之製造方法的斷面圖。 第15圖（A)至（C)係說明本發明之絕緣閘極型半導體 面圖、（B)斷面圖。 第16圖係說明習知之絕緣閘極型半導體裝置的⑴平Upper (Fig. 15(C)). Further, although a portion of the source region 12 of the trench 5 is omitted, the same is true for the body region 13 318086 23 1304263. Since the subsequent steps are the same as those of the first embodiment, the description thereof is omitted. Further, as described above, although the n-channel type MOSFET is described as an example in the embodiment of the present invention, it is also applicable to a reverse conductivity type p-channel type MOSFET. Further, in the same manner, the substrate ι and the reverse conductivity type semiconductor layer are disposed under the substrate 1 〇 0, and the bipolar transistor and the power MOSFET are multiplexed in a single chip in a monolithic manner. Insulated Gate Bipolar Transistor (Insulated Gate Bipolar Transistor) [A Brief Description of the Drawings] FIG. 1(A) and (B) are perspective views showing the insulated gate type semiconductor device of the present invention. Fig. 2 (A) and (B) are cross-sectional views showing the insulated gate type semiconductor device of the present invention. Fig. 3 is a view showing the circuit of the insulated gate type semiconductor device of the present invention. Fig. 4 is a schematic view showing the circuit of the insulated gate type semiconductor device of the present invention. Fig. 5 is a circuit diagram showing the circuit of an insulated gate type semiconductor device of the present invention. Fig. 6 is a cross-sectional view showing the manufacturing method of the insulated gate type semiconductor device of the present invention. Fig. 7 is a cross-sectional view showing the manufacturing method of the insulated gate type semiconductor device of the present invention. 318086 24 1304263 Fig. 8 is a cross-sectional view showing a method of manufacturing the insulated gate type semiconductor device of the present invention. Fig. 9 (A) and (B) are cross sectional views showing a method of manufacturing the insulated gate type semiconductor device of the present invention. Fig. 10 (A) and (B) are cross sectional views showing a method of manufacturing the insulated gate type semiconductor device of the present invention. Fig. 11 (A) to (C) are cross sectional views showing a method of manufacturing the insulated gate type semiconductor device of the present invention. Fig. 12 is a (A) circuit diagram, (B) sectional view, and (C) sectional view showing the insulated gate type semiconductor device of the present invention. Fig. 13 (A) and (B) are cross sectional views showing a method of manufacturing the insulated gate type semiconductor device of the present invention. A cross-sectional view of a method of manufacturing the device. Fig. 14 (A) and (B) are cross sectional views showing a method of manufacturing the insulated gate type semiconductor device of the present invention. Fig. 15 (A) to (C) are views showing an insulating gate type semiconductor and a sectional view (B) of the present invention. Figure 16 is a diagram showing the (1) flat of a conventional insulated gate type semiconductor device.
【主要元件符號說明】[Main component symbol description]
6 閘極氧化膜 11 一型磊基層 溝渠 閘極電極 318086 25 1304263 7a 多晶矽層 * 10a 硼磷矽玻璃 12 源極區域 14 第1電極層 16 汲極電極 21 二次電池 24 控制電路 "41 n+型矽半導體基板 • 43 通道層 45 閘極氧化膜 48 源極區域 50 層間絕緣膜 52 没極電極 As 石申 CH 接觸孔 • DR 汲極區域 LiB 二次電池 Q2 M0SFET S 源極 10 層間絕緣膜 10b SOG 13 主體（背閘極）區域 15 第2電極層 20 MOSFET 22 保護電路 29 控制端子 42 π-型蟲晶層 44 溝渠 46 閘極電極 49 主體區域 51 源極電極 100 基板 BG 背閘極 D 没極 G 閘極 Q1 MOSFET PD 寄生二極體 26 3180866 gate oxide film 11 type 1 base channel gate electrode 318086 25 1304263 7a polysilicon layer * 10a borophosphon glass 12 source region 14 first electrode layer 16 drain electrode 21 secondary battery 24 control circuit "41 n+ Type germanium semiconductor substrate • 43 channel layer 45 gate oxide film 48 source region 50 interlayer insulating film 52 electrodeless electrode As Shishen CH contact hole • DR drain region LiB secondary battery Q2 M0SFET S source 10 interlayer insulating film 10b SOG 13 main body (back gate) region 15 second electrode layer 20 MOSFET 22 protection circuit 29 control terminal 42 π-type worm layer 44 trench 46 gate electrode 49 body region 51 source electrode 100 substrate BG back gate D Pole gate Q1 MOSFET PD parasitic diode 26 318086