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TWI300963B - Structure of wire bonding over semiconductor chip - Google Patents

Structure of wire bonding over semiconductor chip Download PDF

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Publication number
TWI300963B
TWI300963B TW095138283A TW95138283A TWI300963B TW I300963 B TWI300963 B TW I300963B TW 095138283 A TW095138283 A TW 095138283A TW 95138283 A TW95138283 A TW 95138283A TW I300963 B TWI300963 B TW I300963B
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TW
Taiwan
Prior art keywords
layer
wire
wafer
metal
pad
Prior art date
Application number
TW095138283A
Other languages
Chinese (zh)
Other versions
TW200733271A (en
Inventor
Jin Yuan Lee
Ying Chih Chen
Original Assignee
Megica Corp
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Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Priority to TW095138283A priority Critical patent/TWI300963B/en
Publication of TW200733271A publication Critical patent/TW200733271A/en
Application granted granted Critical
Publication of TWI300963B publication Critical patent/TWI300963B/en

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Classifications

    • H10W72/90
    • H10W72/536
    • H10W72/59
    • H10W72/934

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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1300963 九、發明說明: 【發明所屬之技術領域】 本發明是有關於-種晶片,且_是有關於—種可以在晶片 之主動元件上所對應的打線塾片進行打線製程的晶片。 ' 【先前技術】 , 在現今資訊爆炸的社會,電子產品遍佈於日常生活中,無論 在食衣住行育樂方面’都會用到積體電路元件所組成的產品。隨 _ 著電子科技不斷地演進,功能性更複雜、更人性化的產品推陳出 新,而-般電子產品係藉由至少一晶片來控制其電子產品的作 動,一般可以利用打線(wire-bonding)的方式、覆晶(flip— _,F/C)的方式、軟片自動 s 貼合(taPe-automated b〇nding, • TAB)的方式,使晶片與一基板或導線架電性連接。 就打線製程而言’打線機台比如利用高週波振動及加壓的方 式’使導線190的一端部192和打線塾片136之表面結構重組, •以接合導線190與打線墊片136,導線⑽之端部I92並因壓力及 高週波振動加熱會聚集成狀的樣式’而形成如第丨圖所示的樣 式,其緣示習知適用於打線製程的晶片之剖面示意圖。 請參照第1圖,晶片110具有一基底120、一線路結構層⑽ -及一保護層140 ’基底120具有-表面122,可以區分為一主動區 124及-非主動區126 ’並且基底12〇還具有多個主動元件128, '比如是電晶體(transistor),形成在基底120之絲122的主動 區124上。線路結構層130係形成在基底12〇之表面122上,線 5 1300963 路結構層130係由-介電結構體132及一金屬微線路結構體以 所構咸,金屬微線路結構體134係交錯於介電結構體132中,並 且還形成在介電結構體132上,並且金屬微線路結構體134會與 主動元件128電性連接。保護層140係位在線路結構層丨加:了 並且保護層140具有至少-開口 142,會暴露出線路結構層⑽ 之金屬微線路結構體134,此暴露於外之金屬微線路結構體 丨即%為打線塾片136 ’而藉由打線的方武可以使導線⑽之端部 192與暴露於保護層14〇之開口 142外之打線墊片136接合。 由於在將導線190之端部192打到暴露於保護層14〇之開口 /42外的打線制136上時,會強烈地震動晶片加,因此在打線 處下方走不能配置有主動元件128,以避免當導線19〇之端部192 打到暴露於保護層14〇之開口 142外的打線塾片136上時,將主 動疋件128破壞’故打線墊片136必須要位在對應於基底⑽之 •非主動區126上’如此晶片11〇的基底12〇之表面122便必須特 別形成非主動區而增加晶片11G的尺寸。另外,當晶片ιι〇受到 社線襄私而產生的強烈震動時,亦有可能會破壞晶片⑽的介電 結構體132,使得介電結構體132產生裂痕。另外,由於保護層 的開口 142製作得很大,而打線塾片136係為大區域地與導線 9〇之端部192電性連接’因此必綱用以與導線19〇之端部192 連接之打線墊片136製作甚大的尺寸,故位在保護層14〇下之金 屬微線路結顧134⑽路佈敬财到侷限。 【發明内容】 6 1300963 ,本發_目岐在提供—種晶片製造方法,可叫加位在保 護層下之金屬微線路結構體的線路佈局·以縮減晶片尺寸,同 除打線触的震動對健層或介電結顧產生财的機會。 s在敘述本u之&,先對空間介詞的用法做界定,所謂空間 介詞L上”係指兩物之空間關係係為可接觸或不可接觸均可二 例而5 ’ A物在B物上,其所表達的意思係為A物可喊接配置在 B物上’ A物有與b物接觸;或者a物係配置在b物上的空間中,a 物沒有與B物接觸。 為達成本發明之上述和其他目的,提[種晶片,適用於藉 由一打線製程使至少—導線與晶片電性連接,晶片至少包括一^ 底、-線路結構層及至少—打線墊片。基底具有多個主動元件: 係位在基底之-表面上。線路結構層條在基底上,線路結構層 ^括-介電結構體及—金屬微線路結構體,金屬微線路結構體係 交錯於介電結構财,並且金屬微線騎構體齡動元件電性連 接。打線墊#係配置在位於主動元件上之線路結構層上,而打線 墊片與線路結構層之金屬微線路結構體紐連接,而導線係接合 在打線墊片上。而打線墊片的厚度比如介於i微米到5微米之間。 依照本發明的難實補,晶片還包括—保護層,配置在線 路結構層上,保護層具有至少—開口,暴露出線路結構層之金屬 微線_顧’打線墊μ係至少透過開口與金屬微線路結構體電 性連接’其中在製作完保護層之後,才製作打線墊片,而開口的 1300963 最大孔控比如介於0· 5微米至40微米之間。 另外,打線墊片包括至少一軟質金屬層,而軟質金屬層佔接 點打線塾片之體積至少—半,其巾軟質金屬層的硬度係小於 80Hv,而軟質金屬層的材質可以是金、銅、鉛或該等金屬之合金 等。 口、’ 此外,根據本發明的較佳實施例,晶片亦可包括一軟性介電 材質及一引線,軟性介電材質係配置在線路結構層上,而打線墊 片係配置在位於絲元件上之軟齡電材質上,⑽至少貫穿軟 性介電材㈣使打雜^與金屬微祕賴體電性連接。其中該 軟性介電材質比如為聚醯亞胺。 、、不上所述,本發明之晶片,由於打線墊片下具有軟性介電材 貝或打線墊片具有軟質金屬層的配置,因此在將導線之端部打 到打線墊片上時,可崎衝因為打線餘造成鶴“的程度, 如此導線之端部便可以打麻置在正位於絲元件上方的打線墊 片上’如此基底之絲便可以減少非主動區的面積,故可以 增加主動元件配置在基底之表面上的密度,進而降低晶片的尺 寸。另外,由於打線刻下具有軟性介電材f,或打線墊片具有 軟質金屬層的配置,因此在將導線之端部打到打線墊片上時,可 二緩衝因為打線製程造成震動晶片的程度,故可以避免晶片的保 護層或介電結構體產生裂痕的情形。再者,由於保護層的開口可 以製作得很小,因此金屬·路結構體僅需小區域地與打線塾片 1300963 或引線電性連接,而可以縮減用以與接點打線墊片或引線連接之 金屬微線路結構體的尺寸,故可以增加位在保護層下之金屬微線 路結構體的線路佈局空 為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明。 【實施方式】 第2圖繪示依照本發明第一較佳實施例之一種可以進行打線 製程的晶片之剖面放大示意圖。晶片21〇具有一基底22〇、一線路 結構層230、一保護層240及至少一打線墊片250,基底22〇具有 多個主動元件228,比如是金屬氧化半導體(Metal ohde1300963 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer, and is a wafer which can be subjected to a wire bonding process which can be performed on a corresponding bonding wire on an active component of a wafer. [Previous technology] In today's information-explosive society, electronic products are used throughout daily life, and products such as integrated circuit components are used in both food and clothing. With the continuous evolution of electronic technology, more complex and more user-friendly products are being introduced, and the general electronic products control the operation of their electronic products by at least one chip, which can generally utilize wire-bonding. The method, the flip chip (flip- _, F/C) method, and the taPe-automated b〇nding (TAB) method are used to electrically connect the wafer to a substrate or a lead frame. In the case of the wire bonding process, the wire bonding machine reassembles the surface structure of the one end portion 192 of the wire 190 and the wire splicing piece 136 by means of high-frequency vibration and pressure, for example, to bond the wire 190 and the wire bonding pad 136, and the wire (10) The end portion I92 is heated to form a concentrated pattern by pressure and high-frequency vibration to form a pattern as shown in the first drawing, which is a schematic cross-sectional view of a conventionally applicable wafer for a wire bonding process. Referring to FIG. 1, the wafer 110 has a substrate 120, a circuit structure layer (10) - and a protective layer 140. The substrate 120 has a surface 122 which can be divided into an active region 124 and an inactive region 126' and a substrate 12 There are also a plurality of active elements 128, such as a transistor, formed on the active region 124 of the filaments 122 of the substrate 120. The circuit structure layer 130 is formed on the surface 122 of the substrate 12, and the line 5 1300963 is formed by the dielectric structure 132 and a metal micro-circuit structure, and the metal micro-circuit structure 134 is interlaced. The dielectric structure 132 is also formed on the dielectric structure 132, and the metal micro-circuit structure 134 is electrically connected to the active device 128. The protective layer 140 is tied to the circuit structure layer and the protective layer 140 has at least an opening 142 that exposes the metal micro-circuit structure 134 of the circuit structure layer (10), which is exposed to the external metal micro-circuit structure. % is the wire tab 136' and the end portion 192 of the wire (10) can be joined to the wire spacer 136 exposed outside the opening 142 of the protective layer 14 by wire bonding. Since the wafer 136 is strongly vibrated when the end portion 192 of the wire 190 is applied to the wire 136 exposed to the opening / 42 of the protective layer 14 ,, the active component 128 cannot be disposed below the wire bonding to avoid When the end portion 192 of the wire 19 is hit onto the wire 136 which is exposed outside the opening 142 of the protective layer 14 ,, the active element 128 is broken. Therefore, the wire shims 136 must be positioned corresponding to the substrate (10). The surface 122 of the substrate 12 which is such a wafer 11 turns on the inactive region 126 must specifically form an inactive region to increase the size of the wafer 11G. In addition, when the wafer is subjected to strong vibration caused by social smuggling, it is also possible to damage the dielectric structure 132 of the wafer (10), causing the dielectric structure 132 to crack. In addition, since the opening 142 of the protective layer is made large, the wire 136 is electrically connected to the end 192 of the wire 9' in a large area. Therefore, it is necessary to connect with the end 192 of the wire 19〇. The wire gasket 136 is made of a large size, so that the metal microwire located under the protective layer 14 is 134 (10). SUMMARY OF THE INVENTION 6 1300963, the present invention provides a method for manufacturing a wafer, which can be called a circuit layout of a metal micro-circuit structure placed under a protective layer, to reduce the size of the wafer, and to eliminate the vibration of the wire contact. The health layer or the dielectric meets the opportunity to generate wealth. s in the narrative of the u &, first define the use of spatial prepositions, the so-called spatial preposition "on" means that the spatial relationship between the two objects is contactable or inaccessible, two cases can be used and 5 'A objects in B In the above, the meaning expressed is that the A object can be spoofed and disposed on the B object. The A object is in contact with the b material; or the a system is disposed in the space on the b object, and the a object is not in contact with the B object. To achieve the above and other objects of the present invention, there is provided a wafer suitable for electrically connecting at least a wire to a wafer by a wire bonding process, the wafer comprising at least a bottom, a wiring structure layer and at least a wire bonding pad. The utility model has a plurality of active components: the system is on the surface of the substrate, the circuit structure layer is on the substrate, the circuit structure layer comprises a dielectric structure and a metal microcircuit structure, and the metal microcircuit structure system is staggered in the dielectric The structure is electrically connected, and the metal microwire riding body is electrically connected. The wire mat # is disposed on the circuit structure layer on the active component, and the wire gasket is connected with the metal microcircuit structure body of the circuit structure layer. And the wire is bonded to the wire gasket The thickness of the wire spacer is, for example, between i micrometers and 5 micrometers. According to the invention, the wafer further includes a protective layer disposed on the circuit structure layer, the protective layer having at least an opening to expose the circuit. The metal microwire of the structural layer _ Gu' wire mat μ is electrically connected to the metal microcircuit structure through at least the opening. The wire shims are formed after the protective layer is formed, and the opening of the 1300963 maximum hole control is 0. 5 microns to 40 microns. In addition, the wire gasket includes at least one soft metal layer, and the soft metal layer occupies at least half of the volume of the wire, and the hardness of the soft metal layer of the towel is less than 80Hv. The material of the soft metal layer may be gold, copper, lead or an alloy of the metals, etc. Port, 'In addition, according to a preferred embodiment of the present invention, the wafer may also comprise a soft dielectric material and a lead, soft dielectric The material is arranged on the circuit structure layer, and the wire gasket is arranged on the soft electrical material on the wire component, and (10) at least runs through the soft dielectric material (4) to make the hybrid and the metal micro-secret electrical property. The soft dielectric material is, for example, a polyimide. The wafer of the present invention has a soft dielectric layer or a wire gasket having a soft metal layer under the wire gasket. When the end of the wire is hit on the wire shims, it can be roughed out because of the wire tying the crane, so that the end of the wire can be placed on the wire lining above the wire element. The wire can reduce the area of the inactive area, so that the density of the active component disposed on the surface of the substrate can be increased, thereby reducing the size of the wafer. In addition, since the soft dielectric material f is cut by the wire, or the wire gasket has a soft metal layer configuration, when the end of the wire is hit onto the wire bonding pad, the degree of vibration of the wafer due to the wire bonding process can be doubled. Therefore, it is possible to avoid the occurrence of cracks in the protective layer or the dielectric structure of the wafer. Furthermore, since the opening of the protective layer can be made small, the metal structure can be electrically connected to the wire 1300963 or the lead in a small area, and can be reduced for connection with the contact wire pad or lead. The size of the metal micro-circuit structure, so that the line layout of the metal micro-circuit structure under the protective layer can be increased, so that the above and other objects, features, and advantages of the present invention can be more clearly understood. A preferred embodiment will be described in detail in conjunction with the drawings. [Embodiment] FIG. 2 is a schematic enlarged cross-sectional view showing a wafer which can be subjected to a wire bonding process according to a first preferred embodiment of the present invention. The wafer 21 has a substrate 22, a circuit structure layer 230, a protective layer 240 and at least one wire spacer 250. The substrate 22 has a plurality of active elements 228, such as a metal oxide semiconductor (Metal ohde).

Semiconductor ’M0S)或電晶體(transistor)等,係形成在基底 220 之一表面222上。線路結構層230係形成在基底22〇之表面222 上,線路結構層230係由一介電結構體232及一金屬微線路結構 體234所構成’金屬微線路結構體234係交錯於介電結構體232 中並且還形成在介電結構體232上,並且金屬微線路結構體234 ^與主動元件228電性連接。保護層24Q係位在線路結構層23〇 上,亚且保護層240具有至少-開口 242,會暴露出線路結構層 230之金屬微線路結構體234,而開口 2犯的最大孔徑係介於⑴$ 微米至40微米之間。 在製作完保護層240之後,還會製作打線墊片25〇在位於主 動兀件228上方的保護層240上及暴露於保護層24〇之開口 242 1300963 外的金屬微線路結構體234上,打線墊片250的厚度t比如是介 於1微米到5微米之間,在本實施例中,打線墊片250係直接正 位於開口 242上,並且暴露於外。打線墊片250包括一黏著層252 、 及至少一軟質金屬層(未繪示),而黏著層252係位在保護層240 上、開口 242的側壁上及暴露於保護層240之開口 242外的金屬 微線路結構體234上,並且至少一軟質金屬層係位在黏著層2 上,軟質金屬層的材質比如是銅、金或鉛合金等,在較佳的情況 ® 下,軟質金屬層的硬度係小於80Hv,而黏著層252的材質比如是 鈦、鉻、鈦鎮合金及鈦氮化合物等。打線塾片250比如可以是下 列數種結構,弟一種結構係由黏著層252、銅層、鎳層及金層所構 成’黏著層252係位於打線墊片25 0的底層,用以使打線塾片250 月匕夠固疋在晶片210的表面,而銅層係位在黏著層π?上,鎳層 係位在銅層上,金層係位在鎳層上,第二種結構係由黏著層252、 籲銅層及金層所構成’黏著層脱係位於打線墊片25〇的底層,用 以使打線墊片250能夠固定在晶片21G的表面,而銅層係位在黏 著層252上’金細立在銅層上,第三種結構係由黏著層脱、鉛 合金層及金層所構成,黏著層252係位於打線塾片25〇的底層, 用以使打線刻250能夠固定在晶片21〇的表面,而錯合金層係 '位在黏著層252上,金層係位在錯合金層上。在上述之三種打線 _墊片中,銅層、金層及鉛合金層的結構均為軟質金屬層,因 此虽文到外力時’可以有大幅度的形變,而緩衝外力對晶片210 !300963 所造成的衝擊’其中在較佳的情況下,軟質金屬層所加總的厚度 要大於1微米。而藉由打線的方武可以使一導線29G之一端部观 與打線墊片250之金層接合。 在上述的結構中,由於打線墊片250具有軟質金屬層,因此 在將導線290之端部292打到打線塾片250上時,可以緩衝因為 打線製程造成震動晶片21G的程度,如此導線29〇之端部292便 可以打到配置在正位於主動元件228上方的打線墊片25〇上,如 此基底220之表面222便可以減少預留非主動區的面積,故可以 增加主動元件228配置在基底220之表面222上的密度,進而降 低晶片210的尺寸。另外,由於打線塾片25()具有軟質金屬層, 因此在將導線29G之端部292打到打線墊片上時,可以緩衝 因為打線製程造成震動晶片21G的程度,故可以避免晶片21〇的 保護層240或介電結構體232產生裂痕。另外,由於保護層· 的開口 242可以製作得很小,因此金屬微線路結構體2料僅需小 區域地與打線墊片25()電性連接,而可以縮減用以與打線塾片· 連接之金屬微線路結構體234的尺寸,故可以增加位在保護層24〇 下之金屬微線路結構體234的線路佈局空間。 在上述的結構中,打線墊片係位在開口的正上方,然而本發 月的應用並非僅限於此’如第3圖所示,其纟會示依照本發明第二 較佳實施例之一種可崎衡線製程的晶片之剖面放大示意圖, 其中若是本實施例中的標號與第—較佳實施例—樣者,則表示在 1300963 本實施例中所指明的構件係雷同於在第一較佳實施例中所指明的 構件,在此便不再贅述。請參照第3圖,晶片212還具有一引線 256,而打線墊 片254係位在開口 242周圍的保護層240上,如此藉由引線256 可以使打線墊片254與暴露於保護層240之開口 242外的金屬微 線路結構體234電性連接,而打線墊片254位在主動元件228的 上方。打線墊片254及引線256的結構均至少包括一黏著層258 及至少一車人貝金屬層(未繪示),其比如是由黏著層258、銅層、鎳 層及金層所構成,黏著層258係位於打線墊片254及引線256的 底層,用以使打線墊片254及引線256能夠固定在晶片212的表 面,而銅層係位在黏著層258上,鎳層係位在銅層上,金層係位 在鎳層上。另外’打線塾片254及引線256亦可以是由黏著層258、 銅層及金層所構成,黏著層258係位於打線墊片254及引線256 的底層,用以使打線墊片254及引線256能夠固定在晶片212的 表面,而銅層係位在黏著層258上,金層係位在銅層上;再者, 打線塾片254及引線256亦可以是由黏著層258、錯合金層及金層 所構成,黏著層258係位於打線墊片254及引線256的底層,用 以使打線墊片254及引線256能夠固定在晶片212的表面,而錯 合金層係位在黏著層258上,金層係位在鉛合金層上。其中黏著 層258的材質比如是鈦、鉻、鈦鎢合金或鈦氮化合物等。 在上述的實施例中,保護層之開口係為甚小的結構,然而本 12 1300963 發明的應用並非僅限於此,如第4圖所示,其繪示依照本發明第 三較佳實施例之一種可以進行打線製程的晶片之剖面放大示意 圖。請參照第4圖,保護層340的開口 342亦可以是具有甚大的 截面積,其開口 342的最大徑寬比如是60微米,而保護層34〇的 開〇 342可以暴露出金屬微、線路結構體334。在製作完保護層34〇 後,可以進行製作打線墊片350的步驟,其中打線墊片35〇可以 是僅形成在暴露於保護層340之開口 342外的金屬微線路結構體 • 334上’而打線塾片可以位在主動元件328的上方。打線墊片 350包括-黏著層352及至少一軟質金屬層,其金屬|的結構如前 所述’在此财再魏H亦可以如第5崎示的結構,其 :繚讀照本發明第四較佳實施例之—種可以進行打線製程的晶片 之d面放大不忍圖,其中若是本實施例中的標號與第三較佳實施 例-樣者,則麵在本實關巾所指明的構件係雷同於在第一較 φ ^土貝施例中所指明的構件’在此便不再贅述。如第5圖所示,打 線^ 354亦可以還延伸到保護層340之開口 342的侧壁上及位 在罪近保護層340之開口 342周圍的保護層34〇上。 “在前述的實施例中,係藉由具有軟質金屬層的打線塾片來緩 衝打線製程對打線墊片所造成的衝擊,然而本發明並非僅限於上 j的應用。如第6圖所示’其緣示依照本發明第五較佳實施例之 ‘:種可以進行打線製程的晶片之放大示意圖。請參照第6圖, 4 410亦可以還包括—軟性介電材質柳及—引線,如此藉 13 1300963A semiconductor 'M0S' or a transistor or the like is formed on one surface 222 of the substrate 220. The circuit structure layer 230 is formed on the surface 222 of the substrate 22, and the circuit structure layer 230 is composed of a dielectric structure 232 and a metal micro-circuit structure 234. The metal micro-circuit structure 234 is interlaced with the dielectric structure. The body 232 is also formed on the dielectric structure 232, and the metal micro-circuit structure 234^ is electrically connected to the active device 228. The protective layer 24Q is tied to the line structure layer 23, and the protective layer 240 has at least an opening 242, which exposes the metal micro-circuit structure 234 of the line structure layer 230, and the maximum aperture diameter of the opening 2 is (1) From $ microns to 40 microns. After the protective layer 240 is formed, a wire spacer 25 is also formed on the protective layer 240 above the active element 228 and on the metal micro-circuit structure 234 exposed outside the opening 242 1300963 of the protective layer 24, The thickness t of the spacer 250 is, for example, between 1 micrometer and 5 micrometers. In the present embodiment, the wire bonding spacer 250 is directly on the opening 242 and exposed to the outside. The wire spacer 250 includes an adhesive layer 252 and at least one soft metal layer (not shown), and the adhesive layer 252 is fastened on the protective layer 240, on the sidewall of the opening 242, and exposed outside the opening 242 of the protective layer 240. The metal microcircuit structure 234 is on the at least one soft metal layer on the adhesive layer 2. The soft metal layer is made of copper, gold or lead alloy. In the preferred case, the hardness of the soft metal layer is The material of the adhesive layer 252 is less than 80 Hv, and the material of the adhesive layer 252 is titanium, chromium, titanium alloy, titanium nitride, and the like. The wire splicing piece 250 may be, for example, the following structures. The structure of the wire is composed of an adhesive layer 252, a copper layer, a nickel layer and a gold layer. The adhesive layer 252 is located on the bottom layer of the wire shims 25 0 for tying the wire. The film is fixed on the surface of the wafer 210 for 250 months, and the copper layer is on the adhesion layer π?, the nickel layer is on the copper layer, the gold layer is on the nickel layer, and the second structure is adhered. The layer 252, the copper layer and the gold layer constitute an adhesive layer which is located on the bottom layer of the wire bonding pad 25 ,, so that the wire bonding pad 250 can be fixed on the surface of the wafer 21G, and the copper layer is tied on the adhesive layer 252. 'The gold is standing on the copper layer. The third structure is composed of the adhesive layer, the lead alloy layer and the gold layer. The adhesive layer 252 is located on the bottom layer of the 25-inch wire, so that the wire 250 can be fixed. The surface of the wafer 21 is, and the wrong alloy layer is located on the adhesive layer 252, and the gold layer is on the wrong alloy layer. In the above three types of wire-shieldings, the structures of the copper layer, the gold layer and the lead alloy layer are all soft metal layers, so that although the external force can be greatly deformed, the external force is applied to the wafer 210 ! 300963 The resulting impact 'wherein the preferred thickness of the soft metal layer is greater than 1 micron. By wire bonding, one end of a wire 29G can be joined to the gold layer of the wire spacer 250. In the above structure, since the wire bonding pad 250 has a soft metal layer, when the end portion 292 of the wire 290 is hit onto the wire clamping blade 250, the degree of vibration of the wafer 21G due to the wire bonding process can be buffered, and thus the wire 29〇 The end portion 292 can be disposed on the wire bonding pad 25 正 disposed above the active component 228, so that the surface 222 of the substrate 220 can reduce the area of the reserved inactive region, so that the active component 228 can be disposed on the substrate. The density on surface 222 of 220, in turn, reduces the size of wafer 210. In addition, since the wire splicing sheet 25() has a soft metal layer, when the end portion 292 of the wire 29G is hit onto the wire grooving pad, the degree of the vibration of the wafer 21G due to the wire splicing process can be buffered, so that the wafer 21 can be prevented from being smashed. The protective layer 240 or the dielectric structure 232 is cracked. In addition, since the opening 242 of the protective layer can be made small, the metal micro-circuit structure 2 only needs to be electrically connected to the wire bonding pad 25 () in a small area, and can be reduced for connection with the wire bonding piece. Since the size of the metal micro-circuit structure 234 is increased, the line layout space of the metal micro-circuit structure 234 located under the protective layer 24 can be increased. In the above structure, the wire bonding pad is located directly above the opening, but the application of the present month is not limited to this. As shown in FIG. 3, a wire according to a second preferred embodiment of the present invention will be described. A cross-sectional enlarged view of a wafer that can be used in the process of the present invention. If the reference numerals in the present embodiment are the same as those in the first preferred embodiment, it means that the components specified in the embodiment are identical to those in the first comparison. The components specified in the preferred embodiment will not be described herein. Referring to FIG. 3, the wafer 212 further has a lead 256, and the wire bonding pad 254 is fastened on the protective layer 240 around the opening 242, so that the wire bonding pad 254 and the opening exposed to the protective layer 240 can be made by the wire 256. The metal microcircuit structure 234 outside the 242 is electrically connected, and the wire spacer 254 is located above the active component 228. The wire pad 254 and the wire 256 are each provided with at least one adhesive layer 258 and at least one metal layer (not shown), which is composed of an adhesive layer 258, a copper layer, a nickel layer and a gold layer, and is adhered thereto. The layer 258 is located on the bottom layer of the wire bonding pad 254 and the lead 256, so that the wire bonding pad 254 and the wire 256 can be fixed on the surface of the wafer 212, and the copper layer is tied to the adhesive layer 258, and the nickel layer is tied to the copper layer. Upper, the gold layer is on the nickel layer. In addition, the wire 254 and the wire 256 may also be composed of an adhesive layer 258, a copper layer and a gold layer. The adhesive layer 258 is located on the bottom layer of the wire bonding pad 254 and the lead 256 for the wire bonding pad 254 and the lead wire 256. Can be fixed on the surface of the wafer 212, and the copper layer is on the adhesive layer 258, and the gold layer is on the copper layer; further, the wire 254 and the lead 256 can also be formed by the adhesive layer 258, the wrong alloy layer and The gold layer is formed, and the adhesive layer 258 is located on the bottom layer of the wire bonding pad 254 and the lead wire 256, so that the wire bonding pad 254 and the wire 256 can be fixed on the surface of the wafer 212, and the wrong alloy layer is tied on the adhesive layer 258. The gold layer is tied to the lead alloy layer. The material of the adhesive layer 258 is, for example, titanium, chromium, titanium tungsten alloy or titanium nitride compound. In the above embodiments, the opening of the protective layer is a small structure. However, the application of the present invention is not limited thereto, as shown in FIG. 4, which is illustrated in accordance with the third preferred embodiment of the present invention. A cross-sectional enlarged view of a wafer that can be subjected to a wire bonding process. Referring to FIG. 4, the opening 342 of the protective layer 340 may have a large cross-sectional area, and the maximum diameter of the opening 342 is, for example, 60 micrometers, and the opening 342 of the protective layer 34 可以 may expose the metal micro and the circuit structure. Body 334. After the protective layer 34 is formed, the step of fabricating the wire bonding pad 350 may be performed, wherein the wire bonding pad 35 may be formed only on the metal microcircuit structure body 334 exposed outside the opening 342 of the protective layer 340. The wire slap can be positioned above the active component 328. The wire spacer 350 includes an adhesive layer 352 and at least one soft metal layer, and the structure of the metal| is as described above. Here, the structure of the metal can also be as shown in the fifth, and it is: In the fourth preferred embodiment, the d-side enlargement of the wafer which can be subjected to the wire bonding process is not allowed. If the reference numerals in the embodiment are the same as those in the third preferred embodiment, the surface is specified in the actual cover towel. The components are the same as those specified in the first comparative example, and will not be described here. As shown in Fig. 5, the wire 354 may also extend over the sidewall of the opening 342 of the protective layer 340 and over the protective layer 34 of the opening 342 of the smear protective layer 340. "In the foregoing embodiment, the impact of the wire bonding process on the wire bonding pad is buffered by the wire clamping blade having the soft metal layer, but the present invention is not limited to the application of the upper j. As shown in Fig. 6' According to the fifth preferred embodiment of the present invention, an enlarged schematic view of a wafer that can be subjected to a wire bonding process can be referred to. Referring to FIG. 6, the 4 410 can also include a soft dielectric material and a lead wire. 13 1300963

由軟ί生”電材貝460可以緩衝在打線時對晶片·的衝擊。軟性 介電材f獅係位在保護層_上,而打線墊請係位在軟性 ’|电材貝460上’引線470係貫穿軟性介電材質棚,用以使暴露 於保護層44G之開口 442外的金屬微線路結構體伽與打線塾片 450電性連接’其中打線塾片係位在主動元件的上方,並 且打線墊片45G亦位在保護層物之開口 442的正上方,而軟性 ;ι電材質46G比如為聚醯亞胺。由於軟性介電材質棚已經可以 緩衝打線製㈣晶;U1G所造成的衝擊,因此打線刻亦可 以是不需具有軟質金屬層的結構;當断線亦可以是具有 軟質金屬層的結構,如此在進行打線製程時,會有更加的緩衝效 果打線墊片450及引線470所構成的金屬結構係位在軟性介電 材質460上、軟性介電材質460之開孔4肋上、保護層44〇上、 保濩層440之開口 442的側壁上及暴露於保護層44〇之開口 442 外的金屬微線路結構體434上。打線墊片450及引線470所構成 的金屬結構可以包括一黏著層452及至少一軟質金屬層(未繪 示)’比如是由黏著層452、銅層、鎳層及金層所構成,黏著層452 係位於打線墊片450及引線470所構成的金屬結構之底層,用以 使打線墊片450及引線470能夠固定在晶片41〇的表面,而銅層 係位在黏著層452上,鎳層係位在銅層上,金層係位在鎳層上;另 外,打線墊片450及引線470所構成的金屬結構亦可以是由黏著 層452、銅層及金層所構成,黏著層452係位於打線墊片450及引 1300963 線470所構成的金屬結構之底層,用以使打線墊片450及引線470 能夠固定在晶片410的表面,而銅層係位在黏著層452上,金層 係位在銅層上··再者,打線墊片450及引線470所構成的金屬結構 亦可以是由黏著層452、鉛合金層及金層所構成,黏著層452係位 於打線墊片450及引線470所構成的金屬結構之底層,用以使打 線墊片450及引線470能夠固定在晶片410的表面,而鉛合金層 係位在黏者層452上,金層係位在錯合金層上。其中黏著層452 的材質比如是鈦、鉻、鈦鶴 合金或欽說化合物等。 在上述第五較佳實施例的結構中,由於打線墊片Ago下具有 軟性介電材質460,同時打、線墊片450亦可以具有軟質金屬層,因 此在將導線490之端部492打到打線墊片450上時,可以緩衝因 為打線製程造成震動晶片·的程度,如此導線·之端部舰 便可以打到配置在正位於主動元件428上方的打線塾片伽上, 如此基底420之表面422便可以減少預留非主動區的面積,故可 以增加主動元件428配置在基底·之表面似上的密度,進而 降低晶片410的尺寸。另外,由於打線墊片下具有軟性介電 材質,同時打線塾片亦可以具有軟質金屬層,因此在將導 線490之端部492打到打線墊片上時,可以緩衝因為打線製 程造成震動晶片·的程度,故可以避免晶片_的保護層· 或介電結構體432產生裂痕的情形。再者,由於保護層姻的開 15 1300963 口 442可以製作得很小,約略為〇· 5微米到4〇微米之間,因此金 屬微線路結構體434僅需小區域地與引線470電性連接,而可以 縮減用以與引線連接之金屬微線路結構體434的尺寸,故可 以增加位在保護層下之金屬微線路結構體佩的線路佈局空 間。 口工 在上述的第五較佳實施例中,打線墊片係位在保護層之開口 的正上方,然而本發明的應用並非僅限於此,如第7圖所示,其 繪示依照本發日⑽六錄實補之-種可以進行打職程的晶片' 之剖面放大示意圖,其中若是本實施例中的標號與第五較佳實施 例一樣者,則表示在本實施例中所指明的構件係雷同於在第一較 佳實施例中所指明的構件,在此便不再贅述。請參照第7圖,晶 片41 2之引線 472除了在軟性介電材質46〇的開孔4防中延伸之外,還在軟性介 電材質460上延伸,而打線墊片454係位在軟性介電材質46〇之 開孔462周圍的軟性介電材質460上,如此藉由引線4γ2可以使 打線墊片454與暴露於保護層440之開口 442 外的金屬微線路結構體434電性連接,而打線塾片454位在主動 凡件428的上方。打線墊片454及引線472所構成的金屬結構如 第五較佳實施例所述,在此便不再贅述。 綜上所述,本發明至少具有下列優點·· 1·本發明之晶片,由於打線墊片下具有軟性介電材質,或打 1300963 線制具有軟質金屬層的配置,因此在將導線之端部打到打線塾 才可乂緩衝因為打線製程造成震動晶片的程度,如此導線 之瑞部便可以打到配置在正位於絲元件上方的打線㈣上,如 此基底之表面便可以減少預留非主動區的面積,故可以增加主動 ,70件配置在基底之表面上的密度,進而降低晶片的尺寸。 本么月之阳片’由於打線翻下具有軟性介電材質,或打 雜片士具有軟質金屬層的配置,因此在將導線之端部打到打線塾 片上時,可以緩衝因為打線製程造成震動晶片的程度,故可以避 免晶片的保護層或介電結構體產生裂痕的情形。 3·本發明之晶片,由於保護層的開口可以製作得很小,因此 金屬微線路結構體僅需小區域地與打線墊片或引線電性連接,而 可以縮減用以與打線墊片或引線連接之金屬微線路結構體的尺 寸故可以增加位在保護層下之金屬微線路結構體的線路佈局空 間。 雖然本發明已[較佳實施觸露如上,财並_以限定 本發明,任何熟習此技#者,在不麟本發明之精神和範圍内, 當可作些許之更動與潤飾,因此本發明之保護範圍#視後附之申 請專利範圍所界定者為準。 • 【圖式簡單說明】 • 第1圖繪示習知適用於打線製程的晶片之剖面示意圖。 第2圖繪示依照本發明第一較佳實施例之一種可以進 行打線製程的晶片之剖面放大示意圖。 17 1300963 第3 ®繪示依照本發二較佳實關之—種可以進 行打線製程的晶片之剖敝大示意圖。 ® 4崎示賴本發明第三較佳實補之_種可以進 • 行打線製程的晶片之剖面放大示意圖。 , 第5圖繪示依照本發明第四較佳實施例之一種可以進 行打線製程的晶片之剖面放大示意圖。 _ 第6圖繪示依照本發明第五較佳實施例之一種可以進 行打線製程的晶片之剖面放大示意圖。 第7圖繪示依照本發明第六較佳實施例之一種可以進 行打線製程的晶片之剖面放大示意圖。 【主要元件符號說明】 圖式之標示說明·· 110 ·晶片 魯 120 ·基底 122 :表面 124 :主動區 126 :非主動區 128 :主動元件 130 :線路結構層 132 :介電結構體 134 :金屬微線路結構體 18 1300963 打線墊片 保護層 開口 導線 端部 晶片 晶片 基底 表面 主動元件 線路結構層 介電結構體 金屬微線路結構體 保護層 開口 打線墊片 黏著層 接點打線墊片 引線 黏著層 導線 19 1300963 端部 主動元件 金屬微線路結構體 保護層 開口 打線墊片 黏著層 打線墊片 晶片 晶片 基底 表面 主動元件 介電結構體 金屬微線路結構體 保護層 開口 打線墊片 黏著層 打線墊片 軟性介電材質 20 1300963 462 :開孔 470 :引線 472 :引線 490 :導線 492 :端部The soft material "electric material 460 can buffer the impact on the wafer when the wire is hit. The soft dielectric material f lion is on the protective layer _, and the wire pad should be tied to the soft '|Electric material 460' lead The 470 series extends through the flexible dielectric material shed for electrically connecting the metal micro-circuit structure body exposed outside the opening 442 of the protective layer 44G to the wire splicing plate 450, wherein the wire splicing film is tied above the active component, and The wire gasket 45G is also located directly above the opening 442 of the protective layer, and is soft; the electric material 46G is, for example, polyimine. Since the soft dielectric material shed can already buffer the wire (four) crystal; the impact caused by the U1G Therefore, the wire-cutting can also be a structure that does not need to have a soft metal layer; when the wire breakage can also be a structure having a soft metal layer, when the wire-bonding process is performed, there is a more buffering effect, and the wire spacer 450 and the lead wire 470 are formed. The metal structure is on the flexible dielectric material 460, the open dielectric 4 rib of the flexible dielectric material 460, the protective layer 44, the sidewall of the opening 442 of the protective layer 440, and the opening exposed to the protective layer 44. Gold outside 442 The metal structure formed by the wire bonding pad 450 and the wire 470 may include an adhesive layer 452 and at least one soft metal layer (not shown), such as an adhesive layer 452, a copper layer, a nickel layer, and The gold layer is formed, and the adhesive layer 452 is located on the bottom layer of the metal structure formed by the wire bonding pad 450 and the wire 470, so that the wire bonding pad 450 and the wire 470 can be fixed on the surface of the wafer 41, and the copper layer is in the On the adhesive layer 452, the nickel layer is on the copper layer, and the gold layer is on the nickel layer. In addition, the metal structure formed by the wire spacer 450 and the wire 470 may also be an adhesive layer 452, a copper layer and a gold layer. The adhesive layer 452 is located on the bottom layer of the metal structure formed by the wire bonding pad 450 and the 1300963 wire 470, so that the wire bonding pad 450 and the wire 470 can be fixed on the surface of the wafer 410, and the copper layer is stuck. On the layer 452, the gold layer is on the copper layer. Further, the metal structure formed by the wire spacer 450 and the wire 470 may be composed of an adhesive layer 452, a lead alloy layer and a gold layer, and the adhesive layer 452 is Located in the wire gasket 450 and the lead 470 The bottom layer of the metal structure is used to enable the wire bonding pad 450 and the lead wire 470 to be fixed on the surface of the wafer 410, and the lead alloy layer is on the adhesive layer 452, and the gold layer is on the wrong alloy layer. The material of 452 is, for example, titanium, chrome, titanium alloy or compound, etc. In the structure of the fifth preferred embodiment, since the wire gasket Ago has a soft dielectric material 460, the wire and wire gasket 450 are simultaneously It is also possible to have a soft metal layer, so that when the end portion 492 of the wire 490 is hit onto the wire bonding pad 450, the degree of vibration of the wafer due to the wire bonding process can be buffered, so that the end of the wire can be placed in the configuration. The surface of the substrate 420 can reduce the area of the reserved inactive area, so that the density of the active element 428 disposed on the surface of the substrate can be increased, thereby reducing the wafer. The size of 410. In addition, since the wire gasket has a soft dielectric material and the wire can also have a soft metal layer, when the end portion 492 of the wire 490 is hit on the wire gasket, the wafer can be buffered due to the wire bonding process. To the extent that the protective layer of the wafer_ or the dielectric structure 432 is cracked. Furthermore, since the opening 15 1300963 opening 442 of the protective layer can be made very small, approximately between 5 μm and 4 μm, the metal microcircuit structure 434 only needs to be electrically connected to the lead 470 in a small area. The size of the metal micro-circuit structure 434 for connecting to the leads can be reduced, so that the line layout space of the metal micro-circuit structure under the protective layer can be increased. In the fifth preferred embodiment described above, the wire bonding pad is fastened directly above the opening of the protective layer, but the application of the present invention is not limited thereto, as shown in FIG. 7, which is shown in accordance with the present invention. A cross-sectional enlarged view of a wafer that can be used for a job, wherein the reference numerals in the embodiment are the same as those in the fifth preferred embodiment, and the same is indicated in the embodiment. The components are the same as those specified in the first preferred embodiment and will not be described again. Referring to FIG. 7, the lead wire 472 of the wafer 41 2 is extended on the flexible dielectric material 460 except for the opening of the open dielectric 4 of the flexible dielectric material 46, and the wire bonding pad 454 is in the soft medium. The dielectric material 46 is electrically connected to the flexible dielectric material 460 around the opening 462. Thus, the wire bonding pad 454 can be electrically connected to the metal micro-circuit structure 434 exposed outside the opening 442 of the protective layer 440 by the lead 4γ2. The 454 piece of the wire is above the active piece 428. The metal structure of the wire spacer 454 and the wire 472 is as described in the fifth preferred embodiment, and will not be described herein. In summary, the present invention has at least the following advantages: 1. The wafer of the present invention has a soft dielectric material under the wire bonding pad, or a 1300963 wire having a soft metal layer, so that the end of the wire is After hitting the wire, the buffer can be buffered because of the degree of vibration of the wafer caused by the wire-cutting process, so that the wire of the wire can be placed on the wire (4) located above the wire component, so that the surface of the substrate can reduce the reserved inactive zone. The area can be increased, and the density of 70 pieces disposed on the surface of the substrate, thereby reducing the size of the wafer. This month's positive film 'has a flexible dielectric material due to the wire being turned down, or the configuration of the soft metal layer of the murderer. Therefore, when the end of the wire is hit on the wire smashing piece, the vibration chip can be buffered due to the wire bonding process. To the extent that cracks in the protective layer or dielectric structure of the wafer can be avoided. 3. In the wafer of the present invention, since the opening of the protective layer can be made small, the metal micro-circuit structure only needs to be electrically connected to the wire pad or the lead in a small area, and can be reduced for use with the wire pad or lead. The size of the connected metal microcircuit structure can increase the layout space of the metal microcircuit structure under the protective layer. Although the present invention has been described as a preferred embodiment, it is intended to limit the invention, and any skilled person in the art can make some modifications and refinements within the spirit and scope of the present invention. The scope of protection # is subject to the definition of the patent application scope attached. • [Simple Description of the Drawings] • Figure 1 is a schematic cross-sectional view of a conventional wafer suitable for wire bonding processes. Fig. 2 is a schematic enlarged cross-sectional view showing a wafer which can be subjected to a wire bonding process in accordance with a first preferred embodiment of the present invention. 17 1300963 3X shows a schematic cross-sectional view of a wafer that can be wire-bonded in accordance with the preferred embodiment of the present invention. The fourth preferred embodiment of the present invention can be used to enlarge the cross-section of the wafer in which the wire bonding process is performed. FIG. 5 is a schematic enlarged cross-sectional view showing a wafer which can be subjected to a wire bonding process according to a fourth preferred embodiment of the present invention. Figure 6 is a cross-sectional enlarged view showing a wafer which can be subjected to a wire bonding process in accordance with a fifth preferred embodiment of the present invention. Figure 7 is a cross-sectional enlarged view showing a wafer which can be subjected to a wire bonding process in accordance with a sixth preferred embodiment of the present invention. [Explanation of main component symbols] Description of the description of the drawings · 110 · Wafer 120 · Substrate 122 : Surface 124 : Active region 126 : Inactive region 128 : Active device 130 : Line structure layer 132 : Dielectric structure 134 : Metal Microcircuit structure 18 1300963 wire gasket protective layer open wire end wafer wafer substrate surface active component circuit structure layer dielectric structure metal microcircuit structure protective layer opening wire gasket adhesive layer contact wire gasket wire adhesion layer wire 19 1300963 End Active Components Metal Microcircuit Structure Protective Layer Opening Wire Washer Adhesive Layer Wire Washer Wafer Wafer Surface Active Component Dielectric Structure Metal Microcircuit Structure Protective Layer Opening Wire Washer Adhesive Layer Wire Washer Soft Media Electrical material 20 1300963 462 : Opening 470 : Lead 472 : Lead 490 : Wire 492 : End

Claims (1)

1300963 申請專利範圍: L 一種晶片,適用於藉由一打線製程使至少一導線與該晶 片電性連接,該晶片至少包括: 一基底’該基底具有複數個主動元件,係位在該基底 之一表面上; 一線路結構層,係位在該基底之該表面上,該線路結 構層包括一介電結構體及一金屬微線路結構體,該金屬微 線路結構體係交錯於該介電結構體中,並且該金屬微線路 結構體與該些主動元件電性連接;以及 至少一打線墊片,係配置在該線路結構層上,該打線 墊片與該線路結構層之該金屬微線路結構體電性連接,且 該打線墊片係配置在該些主動元件之至少其中之一上,而 在進行該打線製程時,該導線適於接合在該打線墊片上。 2. 如申請專利範圍第1項所述之晶片,包括一保護層,配 置在該線路結構層上,該保護層有至少一開口,暴露出 該線路結構層之該金屬微線路結構體,該打線墊片係至 少透過該開口與該金脣微線路結構體電性連接,其中在 製作完該保護之後,才製作該打線墊片。 3. 如申請專利範圍第1項所述之晶片,該開口的最大孔徑 係介於0. 5微米至40微米之間。 4. 如申請專利範圍第2項所述之晶片,其中該打線墊片係 直接正位於該開口上。 5. 如申請專利範圍第2項所述之晶片,還包括一引線,分 別電性連接該打線墊片及暴露於該開口外之該金屬微 22 1300963 線路結構體。 6·如申請專利範圍第5項所述之晶片,該引線係依附在該 保護層上延伸,並且暴露於外。 7·如申請專利範圍第2項所述之晶片,該打線墊片係位在 該保護層上。 8.如=請專利範圍第2項所述之晶片,該打線墊片係位在 暴路於該保護層外之該金屬微線路結構體上。 3.如申請專利範圍第i項所述之晶片,其中該打線塾片包 括至少一軟質金屬層’該軟質金屬層之厚度大於!微 米0 10·如申請專利範圍第9項所述之晶片,其中該軟質金 屬層的硬度係小於80Ην。 、 11 · 如申請專利範圍第9 屬層的材質係選自於金、 群中的一種材質。 項所述之晶片,其中該軟質金 鋼、錯及該等之合金所組成族1300963 Patent Application Range: L A wafer suitable for electrically connecting at least one wire to the wafer by a wire bonding process, the wafer comprising at least: a substrate having a plurality of active components, one of the substrates a circuit structure layer on the surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit structure interlaced in the dielectric structure And the metal microcircuit structure is electrically connected to the active components; and at least one wire gasket is disposed on the circuit structure layer, and the wire gasket and the metal microcircuit structure of the circuit structure layer are electrically And the wire bonding pad is disposed on at least one of the active components, and the wire is adapted to be engaged on the wire bonding pad during the wire bonding process. 2. The wafer of claim 1, comprising a protective layer disposed on the circuit structure layer, the protective layer having at least one opening exposing the metal micro-circuit structure of the circuit structure layer, The wire gasket is electrically connected to the gold lip microcircuit structure through at least the opening, wherein the wire gasket is fabricated after the protection is completed. 5微米至40微米之间。 The maximum aperture of the opening is between 0.5 microns and 40 microns. 4. The wafer of claim 2, wherein the wire gasket is directly on the opening. 5. The wafer of claim 2, further comprising a lead electrically connected to the wire spacer and the metal micro 22 1300963 circuit structure exposed outside the opening. 6. The wafer of claim 5, wherein the lead is attached to the protective layer and exposed to the outside. 7. The wafer of claim 2, wherein the wire spacer is attached to the protective layer. 8. The wafer of claim 2, wherein the wire spacer is located on the metal microcircuit structure outside the protective layer. 3. The wafer of claim i, wherein the wire splicing comprises at least one layer of soft metal. The thickness of the layer of soft metal is greater than! The wafer of claim 9, wherein the soft metal layer has a hardness of less than 80 Ην. , 11 · The material of the ninth genus of the patent application is selected from the group consisting of gold and group. The wafer of the item, wherein the soft gold steel, the alloy of the wrong alloys 項所述之晶片,其中該打線墊 ’該些軟質金屬層所加總之厚 12· 如申請專利範圍第9 片包括複數個軟質金屬層 度大於1微米。 全屬声1=利範圍第12項所述之晶片,其中該些軟 金屬層的硬度均小於80HV。 14金屬:1::利範圍第12項所述之晶片,其中該些軟 入/中至少—材質係選自於金、鋼、錯及兮等 合金所級成族群中的一種材質。及該等 15.如申請專利範圍第1項所述之晶片,其中該打線 23 1300963 片還包括一黏著層,該黏著層的材質係選自於由鈦、 鉻、鈦鎢合金及鈦氨化合物所組成的族群中之一種材 質。 16.如申請專利範圍第1項所述之晶片,其中與該導線 接合之該打線墊片的表面金屬材質係為金。 17·如申請專利範圍第1項所述之晶片,還包括一軟性 介電材質及一引線,該軟性介電材質係配置在該線路結 構層上,而該打線墊片係配置在直接正位於該些主動元 • 件上之該軟性介電材質上,該引線至少貫穿該軟性介電 材貝以使該打線墊片與該金屬微線路結構體電性連接。 18·如申請專利範圍第17項所述之晶片,其中該引線還 - 依附在該軟性介電材質上延伸,並且暴露於外。 I9·如申請專利範圍第17項所述之晶片,其中該軟性介 電材質係為聚醯亞胺。 20· 如申請專利範圍第1項所述之晶片,其中該打線塾 片的厚度係介於1微米到5微米之間。 21· 一種晶片,至少包括: 一基底,包括至少一主動元件; 線路結構層’係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 • 墊; 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護層並暴露出該金屬墊; 24 1300963 一打線墊片,位於該金屬墊上,該打線墊片包括一金 層,其中該打線墊片係經由該開口連接至該金屬墊;以及 一打線導線,連接該打線墊片,該打線導線與該打線 墊片之連接處係位在該主動元件正上方。 22. 如申請專利範圍第21項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 23. 如申請專利範圍第21項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層。 24. 如申請專利範圍第21項所述之晶片,其中,該打線墊 片還包括一銅層,位在該金層下。 25. 如申請專利範圍第24項所述之晶片,其中,該打線墊 片還包括一鎳層,位在該銅層與該金層之間。 26. 如申請專利範圍第21項所述之晶片,其中,該打線墊 片還包括一含鈦之金屬層,位在該金層下。 27. 如申請專利範圍第21項所述之晶片,其中,該打線墊 片還包括一含欽鶴合金之金展層,位在該金層下。 28. 如申請專利範圍第21項所述之晶片,其中,該打線墊 片還包括一含鉻之金屬層,位在該金層下。 29. 如申請專利範圍第21項所述之晶片,其中,該打線墊 片還包括一含鈦氮化合物之金屬層,位在該金層下。 30. 如申請專利範圍第21項所述之晶片,更包括一介電層 位在該保護層上,位在該介電層内之一開口暴露出該保 護層之該開口所暴露出之該金屬墊,且部分之該打線接 墊係位在該介電層上。 25 1300963 31. 如申請專利範圍第30項所述之晶片,其中,該介電層 包括聚醯亞胺(polyimide)。 32. 如申請專利範圍第21項所述之晶片,其中,該打線接 墊之厚度係介於1微米至5微米之間。 33. 如申請專利範圍第21項所述之晶片,其中該打線墊片 係位在該開口上。 34. —種晶片,適用於藉由一打線製程使至少一導線與該晶 片電性連接,該晶片至少包括: • -基底; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 墊·, 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護層並暴露出該金屬墊;以及 一打線墊片,係經由該開口連接至該金屬墊上,該打 W 線墊片包括含一金層且厚度大於2微米之一軟質金屬層, 該打線墊片係用於連接該導線。 35. 如申請專利範圍第34項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 36. 如申請專利範圍第34項所述之晶片,其中,該打線墊 片更包括一延伸接墊,由俯視透視圖觀之該延伸接墊與 該保護層之該開口之位置不同,該導線形成在該延伸接 塾上。 26 1300963 37. 如申請專利範圍第34項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層。 38. 如申請專利範園第37項所述之晶片,其中,該打線墊 片還包括一銅層’位在該金層下。 39. 如申請專利範圍第37項所述之晶片,其中,該軟質金 屬層包括一鎳層及一銅層,該鎳層位在該銅層上,而該 金層位在該鎳層上。 40. 如申請專利範圍第34項所述之晶片,其中,該打線墊 B 片還包括一含鈦之金屬層,位在該打線墊片與該保護層 之間。 41. 如申請專利範圍第34項所述之晶片,其中,該打線墊 片還包括一鈦鎢合金層,位在該打線墊片與該保護層之 間。 42. 如申請專利範圍第34項所述之晶片,其中,該打線墊 片還包括一鉻層,位在該打線墊片與該保護層之間。 43. 如申請專利範圍第34項所述之晶片,其中,該打線墊 I 片還包括一鈦氮化合物層,位在該打線墊片與該保護層 之間。 44. 如申請專利範圍第34項所述之晶片,更包括一介電層 位在該保護層上,位在該介電層内之一開口暴露出該保 護層之該開口所暴露出之該金屬墊,且部分之該打線接 墊係位在該介電層上。 45. 如申請專利範圍第44項所述之晶片,其中,該介電層 包括聚醯亞胺(polyimide)。 27 1300963 46. 如申請專利範圍第34項所述之晶片,其中,該打線接 墊之厚度係介於1微米至5微米之間。 47. 如申請專利範圍第34項所述之晶片,其中談打線墊片 係位在該開口上。 48. —種晶片,至少包括: 一基底; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構具有一金屬 塾; 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護層並暴露出該金屬墊; 一打線墊片,談打線塾片包括一金層及一銅層,該金 層位在該銅層上,其中該打線墊片係經由該開口連接至該 金屬墊;以及 一打線導線,連接在該打線墊片上。 49. 如申請專利範圍第48項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 50. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片更包括一延伸接墊,由俯視透視圖觀之該延伸接墊與 該保護層之該開口之位置不同,該導線形成在該延伸接 墊上。 51. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層。 28 1300963 52. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片還包括一鎳層,位在該金層與該銅層之間。 53. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片還包括一含鈦之金屬層,位在該打線墊片與該保護層 之間。 54. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片還包括一鈦鎢合金層,位在談打線墊片與該保護層之 55. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片還包括一鉻層,位在該打線墊片與該保護層之間。 56. 如申請專利範圍第48項所述之晶片,其中,該打線墊 片還包括一鈦氮化合物層,位在該打線墊片與該保護層 之間。 57. 如申請專利範圍第48項所述之晶片,更包括一介電層 位在該保護層上,位在該介電層内之一開口暴露出該保 護層之該開口所暴露出之該金屬墊,且部分之該打線接 墊係位在該介電層上。 58. 如申請專利範圍第57項所述之晶片,其中,該介電層 包括聚醯亞胺(polyimide)。 59. 如申請專利範圍第48項所述之晶片,其中,該打線接 墊之厚度係介於1微米至5微米之間。 60. 如申請專利範圍第48項所述之晶片,其中該打線墊片 係位在該開口上。 61. —種晶片,至少包括: 29 1300963 一基底; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 墊; 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護脣並暴露出該金屬墊; 一打線塾片,位於該金屬塾上,該打線墊片包括一銅 層及一鎳層,該鎳層位在該銅層上,其中該打線墊片係經 由該開口連接至該金屬墊;以及 一打線導線,連接在該打線墊片上。 62. 如申請專利範圍第61項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 63. 如申請專利範圍第61項所述之晶片,其中,該打線墊 片更包括一延伸接墊,由俯視透視圖觀之該延伸接墊與 該保護層之該開口之位置不同,該導線形成在該延伸接 塾上。 64. 如申請專利範圍第61項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層,位在該 鎳層上。 65. 如申請專利範圍第64項所述之晶片,其中,該軟質金 屬層包括一金層。 66. 如申請專利範圍第61項所述之晶片,其中,該打線墊 片還包括一含鈦之金屬層,位在該打線墊片與該保護層 30 1300963 之間。 67. 如申請專利範圍第61項所述之晶片,其中,該打線墊 片還包括一鈦鎢合金層,位在該打線墊片與該保護層之 間。 68. 如申請專利範圍第61項所述之晶片,其中,該打線墊 片還包括一鉻層,位在該打線墊片與該保護層之間。 69. 如申請專利範圍第61項所述之晶片,其中,該打線墊 片還包括一鈦氮化合物層,位在該打線墊片與該保護層 之間。 70. 如申請專利範圍第61項所述之晶片,更包括一介電層 位在該保護層上,位在該介電層内之一開口暴露出該保 護層之該開口所暴露出之該金屬墊,且部分之該打線接 墊係位在該介電層上。 71. 如申請專利範圍第70項所述之晶片,其中,該介電層 包括聚贐亞胺(polyimide)。 72. 如申請專利範圍第61項所述之晶片,其中,該打線接 墊之厚度係介於1微米至5微米之間。 73. 如申請專利範圍第61項所述之晶片,其中該打線墊片 係位在該開口上。 74. —種晶片,至少包括: 一基底; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 31 1300963 墊; 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護層並暴露出該金屬墊; 一打線墊片,位於該金屬墊上,該打線墊片包括至少 一黏著金屬層及一鎳層,該黏著金屬層包括鈦鎢合金,該 鎳層位在該黏著金屬層上,該打線墊片係經由該開口連接 至該金屬墊;以及 一打線導線,連接在該打線墊片上。 ^ 75.如申請專利範圍第74項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 76. 如申請專利範圍第74項所述之晶片,其中,該打線墊 片更包括一延伸揍墊,由俯視透視圖觀之該延伸接墊與 該保護層之該開口之位置不同,該導線形成在該延伸接 塾上。 77. 如申請專利範圍第74項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層。 i 78. 如申請專利範圍第77項所述之晶片,其中,該打線墊 片還包括一銅層,位在該鎳層下。 79. 如申請專利範圍第77項所述之晶片,其中,該軟質金 屬層包括一金層,該金層位在該鎳層上。 80. 如申請專利範圍第74項所述之晶片,更包括一介電層 位在該保護層上.,位在該介電層内之一開口暴露出該保 護層之該開口所暴露出之該金屬墊,且部分之該打線接 墊係位在該介電層上。The wafer of the item, wherein the layer of the soft metal layer is added to a total thickness of 12. The ninth sheet of the patent application includes a plurality of layers of soft metal greater than 1 micron. The wafer of claim 12, wherein the soft metal layers have a hardness of less than 80 HV. 14: The wafer of claim 12, wherein the soft in/out of at least the material is selected from the group consisting of alloys of gold, steel, and bismuth. The wafer of claim 1, wherein the wire 23 1300963 further comprises an adhesive layer selected from the group consisting of titanium, chromium, titanium tungsten alloy and titanium ammonia compound One of the constituents of the group. 16. The wafer of claim 1, wherein the surface metal material of the wire bonding pad bonded to the wire is gold. 17. The wafer of claim 1, further comprising a flexible dielectric material and a lead, the flexible dielectric material being disposed on the circuit structure layer, and the wire spacer is disposed directly on the line In the flexible dielectric material on the active components, the lead wire penetrates at least the flexible dielectric material to electrically connect the wire bonding pad to the metal microcircuit structure. 18. The wafer of claim 17, wherein the lead is further attached to the flexible dielectric material and exposed to the outside. The wafer according to claim 17, wherein the flexible dielectric material is polyimine. The wafer of claim 1, wherein the wire has a thickness of between 1 micrometer and 5 micrometers. A wafer comprising at least: a substrate comprising at least one active component; a wiring structure layer being positioned on a surface of the substrate, the wiring structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit a structure interleaved in the dielectric structure, the metal micro-circuit structure comprising a metal pad; a protective layer on the circuit structure layer, the protective layer having at least one opening extending through the protective layer and exposing the metal a pad; 24 1300963 a wire gasket on the metal pad, the wire gasket includes a gold layer, wherein the wire gasket is connected to the metal pad via the opening; and a wire bonding wire connecting the wire gasket The connection between the wire bonding wire and the wire bonding pad is located directly above the active component. 22. The wafer of claim 21, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 23. The wafer of claim 21, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron. 24. The wafer of claim 21, wherein the wire pad further comprises a copper layer underlying the gold layer. 25. The wafer of claim 24, wherein the wire spacer further comprises a layer of nickel between the copper layer and the gold layer. 26. The wafer of claim 21, wherein the wire pad further comprises a titanium-containing metal layer underlying the gold layer. 27. The wafer of claim 21, wherein the wire mat further comprises a gold layer comprising a zihe alloy, located below the gold layer. 28. The wafer of claim 21, wherein the wire mat further comprises a chromium-containing metal layer underlying the gold layer. 29. The wafer of claim 21, wherein the wire mat further comprises a metal layer comprising a titanium nitride compound underlying the gold layer. 30. The wafer of claim 21, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. The wafer of claim 30, wherein the dielectric layer comprises a polyimide. The wafer of claim 21, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 33. The wafer of claim 21, wherein the wire gasket is fastened to the opening. 34. A wafer suitable for electrically connecting at least one wire to the wafer by a wire bonding process, the wafer comprising at least: a substrate; a circuit structure layer on the surface of the substrate, the circuit structure The layer includes a dielectric structure and a metal micro-circuit structure interlaced in the dielectric structure, the metal micro-circuit structure including a metal pad, a protective layer, located on the circuit structure layer, The protective layer has at least one opening extending through the protective layer and exposing the metal pad; and a wire gasket is connected to the metal pad via the opening, the W wire spacer comprising a gold layer and a thickness greater than 2 One of the micron soft metal layers, which is used to connect the wire. 35. The wafer of claim 34, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 36. The wafer of claim 34, wherein the wire bonding pad further comprises an extension pad, the extension pad being different from the opening of the protective layer by a top perspective view, the wire Formed on the extension joint. The wafer of claim 34, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron. 38. The wafer of claim 37, wherein the wire pad further comprises a copper layer positioned below the gold layer. 39. The wafer of claim 37, wherein the soft metal layer comprises a nickel layer and a copper layer, the nickel layer being on the copper layer, and the gold layer being on the nickel layer. 40. The wafer of claim 34, wherein the wire pad B further comprises a titanium-containing metal layer between the wire spacer and the protective layer. The wafer of claim 34, wherein the wire mat further comprises a titanium-tungsten alloy layer positioned between the wire-bonding pad and the protective layer. 42. The wafer of claim 34, wherein the wire pad further comprises a chrome layer positioned between the wire spacer and the protective layer. 43. The wafer of claim 34, wherein the wire pad I further comprises a layer of titanium nitride compound between the wire spacer and the protective layer. 44. The wafer of claim 34, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. The wafer of claim 44, wherein the dielectric layer comprises polyimide. The wafer of claim 34, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 47. The wafer of claim 34, wherein the wire spacer is seated on the opening. 48. A wafer comprising at least: a substrate; a wiring structure layer on a surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit structure being staggered In the dielectric structure, the metal micro-circuit structure has a metal ruthenium; a protective layer is disposed on the circuit structure layer, the protective layer has at least one opening extending through the protective layer and exposing the metal pad; The tablet has a gold layer and a copper layer, the gold layer being on the copper layer, wherein the wire gasket is connected to the metal pad via the opening; and a wire bonding wire connected to the wire pad Chip. 49. The wafer of claim 48, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 50. The wafer of claim 48, wherein the wire bonding pad further comprises an extension pad, the extension pad being different from the opening of the protective layer by a top perspective view, the wire Formed on the extension pad. The wafer of claim 48, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron. The wafer of claim 48, wherein the wire pad further comprises a nickel layer positioned between the gold layer and the copper layer. 53. The wafer of claim 48, wherein the wire pad further comprises a metal layer comprising titanium between the wire spacer and the protective layer. 54. The wafer of claim 48, wherein the wire bonding pad further comprises a titanium-tungsten alloy layer, located between the wire bonding pad and the protective layer. 55. The wafer, wherein the wire bonding pad further comprises a chrome layer positioned between the wire bonding pad and the protective layer. 56. The wafer of claim 48, wherein the wire pad further comprises a layer of titanium nitride compound between the wire spacer and the protective layer. 57. The wafer of claim 48, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. 58. The wafer of claim 57, wherein the dielectric layer comprises polyimide. The wafer of claim 48, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 60. The wafer of claim 48, wherein the wire gasket is fastened to the opening. 61. A wafer comprising at least: 29 1300963 a substrate; a wiring structure layer on the surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit structure Interleaved in the dielectric structure, the metal micro-circuit structure comprises a metal pad; a protective layer is disposed on the circuit structure layer, the protective layer has at least one opening extending through the protective lip and exposing the metal pad; a wire splicing plate, the wire screed comprising a copper layer and a nickel layer, wherein the nickel layer is located on the copper layer, wherein the wire bonding pad is connected to the metal pad via the opening; Wire the wire and connect it to the wire gasket. 62. The wafer of claim 61, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 63. The wafer of claim 61, wherein the wire bonding pad further comprises an extension pad, the extension pad being different from the opening of the protection layer in a top perspective view, the wire Formed on the extension joint. 64. The wafer of claim 61, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron on the nickel layer. 65. The wafer of claim 64, wherein the soft metal layer comprises a gold layer. 66. The wafer of claim 61, wherein the wire mat further comprises a titanium-containing metal layer between the wire spacer and the protective layer 30 1300963. The wafer of claim 61, wherein the wire mat further comprises a titanium-tungsten alloy layer positioned between the wire bonding pad and the protective layer. The wafer of claim 61, wherein the wire pad further comprises a chrome layer positioned between the wire spacer and the protective layer. The wafer of claim 61, wherein the wire mat further comprises a titanium nitride compound layer between the wire spacer and the protective layer. 70. The wafer of claim 61, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. The wafer of claim 70, wherein the dielectric layer comprises a polyimide. The wafer of claim 61, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 73. The wafer of claim 61, wherein the wire gasket is seated on the opening. 74. A wafer comprising at least: a substrate; a wiring structure layer on a surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit structure being staggered In the dielectric structure, the metal micro-circuit structure comprises a metal 31 1300963 pad; a protective layer is disposed on the circuit structure layer, the protective layer has at least one opening extending through the protective layer and exposing the metal pad; a wire gasket on the metal pad, the wire gasket comprising at least one adhesive metal layer and a nickel layer, the adhesive metal layer comprising a titanium tungsten alloy, the nickel layer being on the adhesive metal layer, the wire gasket being via The opening is connected to the metal pad; and a wire bonding wire is connected to the wire bonding pad. The wafer of claim 74, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 76. The wafer of claim 74, wherein the wire bonding pad further comprises an extension pad, the extension pad being different from the opening of the protection layer by a top perspective view, the wire Formed on the extension joint. 77. The wafer of claim 74, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron. The wafer of claim 77, wherein the wire pad further comprises a copper layer underlying the nickel layer. 79. The wafer of claim 77, wherein the soft metal layer comprises a gold layer on which the gold layer is located. 80. The wafer of claim 74, further comprising a dielectric layer on the protective layer. The opening in the dielectric layer exposing the opening of the protective layer is exposed. The metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. 32 1300963 81. 如申請專利範圍第80項所述之晶片,其中,該介電層 包括聚醯亞胺(polyimide)。 82. 如申請專利範圍第74項所述之晶片,其中,該打線接 墊之厚度係介於1微米至5微米之間。 83. 如申請專利範圍第74項所述之晶片,其中該打線墊片 係位在該開口上。 84. —種晶片,至少包括: 一基底; 一線路結構層^係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 墊; 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護層並暴露出該金屬墊; 一打線墊片,位於該金屬墊上,該打線墊片包括至少 一黏著金屬層及一鎳層,該黏著金屬層包括鈦,該鎳層位 在該黏著金屬層上,該打線墊片係經由該開口連接至該金 屬墊;以及 一打線導線,連接在該打線墊片上。 85. 如申請專利範圍第84項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 86. 如申請專利範圍第84項所述之晶片,其中,該打線墊 片更包括一延伸接墊,由俯視透視圖觀之該延伸接墊與 該保護層之該開口之位置不同,該導線形成在該延伸接 33 1300963 墊上。 87。 如申請專利範圍第84項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層。 88. 如申請專利範圍第87項所述之晶片,其中,該打線墊 片還包括一銅層,位在該鎳層下。 89·如申請專利範圍第87項所述之晶片,其中,該軟質金 屬層包括一金層,該金層位在該鎳層上。 90. 如申請專利範圍第84項所述之晶片,更包括一介電層 位在談保護層上,位在該介電層内之一開口暴露出該保 護層之該開口所暴露出之該金屬墊,且部分之該打線接 墊係位在該介電層上。 91. 如申請專利範圍第90項所述之晶片,其中,該介電層 包括聚醯亞胺(polyimide)。 92. 如申請專利範圍第84項所述之晶片,其中,該打線接 墊之厚度係介於1微米至5微米之間。 93. 如申請專利範圍第84項所述之晶片,其中該打線墊片 係位在該開口上。 94. 一種晶片,至少包括: 一基底; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電詰構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結槔包括一金屬 墊; 一保護層,位在該線路結構層上,該保護層具有至少 34 1300963 一開口,貫穿該保護層並暴露出該金屬塾; 一打線塾片,位於該金屬墊上,該打線塾片包括至少 一黏著金屬層及一鎳層,該黏著金屬層包括鉻,該鎳層位 在該黏著金屬層上,該打線墊片係經由該開口連接至該金 屬墊;以及 一打線導線,連接在該打線墊片上。 95. 如申請專利範圍第94項所述之晶片,其中,該開口之 最大孔徑係介於0.5微米至40微米之間。 96. 如申請專利範圍笫94項所述之晶片,其中,該打線墊 片更包括一延伸接墊,由俯視透視圖觀之該延伸接墊與 該保護層之該開口之位置不同,談導線形成在該延伸接 塾上。 97. 如申請專利範圍第94項所述之晶片,其中,該打線墊 片更包括至少一厚度大於1微米之軟質金屬層。 98. 如申請專利範圍第97項所述之晶片,其中,該打線墊 片還包括一銅層,位在該鎳層下。 99. 如申請專利範圍第97項所述之晶片,其中,該軟質金 展層包括一金層,該金層位在該鎳層上。 100•如申請專利範圍第94項所述之晶片,更包括一介電 層位在該保護層上,位在該介電層内之一開口暴露出該 保護層之該開口所暴露出之該金屬墊,且部分之該打線 接墊係位在該介電層上。 101. 如申請專利範圍第100項所述之晶片,其中,該介 電層包括聚酸亞胺(polyimide)。 35 1300963 102. 如申請專利範圍第94項所述之晶片,其中,該打線 接墊之厚度係介於1微米至5微米之間。 103. 如申請專利範圍第94項所述之晶片,其中該打線墊 片係位在該開口上。 104. —種晶片,至少包括: 一基底; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬徵線路結 > 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 墊; 一保護層,位在該線路結構層上,該保護層具有至少 一開口,貫穿該保護層並暴露出該金屬微線路結構; 一打線墊片,位於該保護層上,由俯視透視觀之該打 線墊片與該開口為不同位置,該打線墊片係經由該開口連 接至該金屬墊,其中該打線墊片包括一金層,且該金層厚 度大於2微米;以及 t 一打線導線,連接在該打線墊片上。 105. 如申請專利範圍第104項所述之晶片,其中,該開 口之最大孔徑係介於0.5微米至40微米之間。 106. 如申請專利範圍第104項所述之晶片,其中,該打 線墊片更包括至少一厚度大於1微米之軟質金屬層。 107. 如申請專利範圍第106項所述之晶片,其中,該打 線塾片還包括一銅層,位在該金層下。 108. ·如申請專利範圍第106項所述之晶片,其中,該軟 36 I 1300963 質金屬層包括一鎳層及一銅層,該鎳層位在該鋼層上, 而該金層位在該鎳層上。 109·如申請專利範圍第104項所述之晶片,其中,該打 線墊片還包括一含鈦之金屬層,位在該打線墊片與該保 護層之間。 110·如申請專利範圍第104項所述之晶片,其中,該打 線墊片還包括一鈦鎢合金層,位在該打線墊片與該保護 層之間。 111·如申請專利範圍第1〇4項所述之晶片,其中,該打 線墊片還包括一鉻層,位在該打線墊片與該保護層之 間。 112·如申請專利範圍第1〇4項所述之晶片,其中,該打 線墊片還包括一鈦氮化合物層,位在該打線墊片與該保 護層之間。 113·如申請專利範圍第104項所述之晶片,更包括一介 電層位在該保護層上,位在該介電層内之一開口暴露出 該保護層之該開口所暴露出之該金屬墊,且部分之該打 線接墊係位在該介電層上。 114·如申請專利範圍第113項所述之晶片,其中,該介 笔層包括聚醯亞胺(polyimide)。 出.如申請專利範圍第104項所述之晶片,其中,該打 線接墊之厚度係介於1微米至5微米之間。 116· —種晶片,至少包括·· 一基底; 37 1300963 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係父錯於該介電結構中,該金屬微線路結構包括一金屬 墊; 一保護層,位在該線路結構層上,該保護層具有至少 一開口’貫穿該保護層並暴露出該金屬墊; 一打線塾片,位於該金屬墊上,該打線墊片包括至少 一黏著金屬層及一鎳層,該黏著金屬層包括鈦氮化合物, 談鎳層位在該黏著金屬層上,該打線墊片係經由該開口連 接至該金屬塾;以及 一打線導線,連接在該打線墊片上。 117·如申請專利範圍第116項所述之晶片,其中,該開 口之最大孔徑係介於〇·5微米至4〇微米之間。 118·如申請專利範圍第116項所述之晶片,其中,該打 線墊片更包括一延伸接墊,由俯視透視圖觀之該延伸接 墊/、該保遵層之該開口之位置不同,談導線形成在該延 伸接墊上。 119. 如申請專利範圍帛116項所述之晶片,其中,該打 線塾片更包括至少-厚度大於!微米之软質金屬層。 120. 如申請專利範圍第119項所述之晶片,其中,該打 線墊片還包括一銅層,位在該鎳層下。 121. 如申請專利範圍第119項所述之晶片,其中,該軟 質金屬層包括-金層,該金層位在該鎳層上。 122·如申請專利範圍第116項所述之晶片’更包括一介 38 1300963 電層位在該保護層上,位在該介電層内之一開口暴露出 該保護層之該開口所暴露出之該金屬墊,且部分之該打 線接墊係位在該介電層上。 123· 如申請專利範園第122項所述之晶片,其中,該介 電層包括聚蕴亞胺(polyimide)。 124. 如申請專利範圍第116項所述之晶片,其中,該打 線接墊之厚度係介於1微米至5微米之間。 125. —種晶片,適用於藉由一打線製程使至少一導線與 I 該晶片電性連接,該晶片至少包括: 一基底,包括至少一主動元件; 一線路結構層,係位在該基底之表面上,該線路結構 層包括一介電結構及一金屬微線路結構,該金屬微線路結 構係交錯於該介電結構中,該金屬微線路結構包括一金屬 塾; 一保護層,位在該線路結構層上,該保護層具有至少 一孔徑係介於0.5微米至40微米之開口,貫穿該保護層並 > 暴露出該金屬墊; 一打線墊片,經由該開口連接至該金屬墊;以及 一打線導線’連接該打線塾片。 126. 如申請專利範圍第125項所述之晶片,其中,該打 線墊片更包括一延伸接墊,由俯視透視圖觀之該延伸接 墊與該保護層之該開口之位置不同,該導線形成在該延 伸接墊上。 127. 如申請專利範圍第125項所述之晶片,其中,該打 39 1300963 線墊片更包括至少一厚度大於1微米之軟質金屬層。 128. 如申請專利範圍第127項所述之晶片,其中,該軟 質金屬層包括一厚度大於2微米之金層。 129. 如申請專利範圍第127項所述之晶片,其中,該軟 質金屬層包括一厚度大於1微米之銅層。 130. 如申請專利範圍第127項所述之晶片,其中,該軟 質金屬層包括一厚度大於1微米之鎳層。The wafer of claim 80, wherein the dielectric layer comprises a polyimide. The wafer of claim 74, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 83. The wafer of claim 74, wherein the wire gasket is fastened to the opening. 84. A wafer comprising at least: a substrate; a wiring structure layer on the surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit structure being staggered In the dielectric structure, the metal micro-circuit structure comprises a metal pad; a protective layer is disposed on the circuit structure layer, the protective layer has at least one opening extending through the protective layer and exposing the metal pad; a wire on the metal pad, the wire bonding pad comprising at least one adhesive metal layer and a nickel layer, the adhesive metal layer comprising titanium, the nickel layer being located on the adhesive metal layer, the wire bonding pad being connected to the through the opening The metal pad; and a wire harness connected to the wire pad. 85. The wafer of claim 84, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. The wafer of claim 84, wherein the wire lining further comprises an extension pad, the extension pad being different from the opening of the protection layer in a top perspective view, the wire Formed on the pad of the extension 33 1300963. 87. The wafer of claim 84, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron. 88. The wafer of claim 87, wherein the wire pad further comprises a copper layer underlying the nickel layer. The wafer of claim 87, wherein the soft metal layer comprises a gold layer on which the gold layer is located. 90. The wafer of claim 84, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. The wafer of claim 90, wherein the dielectric layer comprises polyimide. The wafer of claim 84, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 93. The wafer of claim 84, wherein the wire gasket is fastened to the opening. 94. A wafer comprising: at least: a substrate; a wiring structure layer on a surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal micro-circuit structure being staggered In the dielectric structure, the metal micro-circuit junction includes a metal pad; a protective layer is disposed on the circuit structure layer, the protective layer has an opening of at least 34 1300963, extending through the protective layer and exposing the metal crucible; a wire splicing piece on the metal pad, the wire splicing piece comprising at least one adhesive metal layer and a nickel layer, the adhesive metal layer comprising chrome, the nickel layer being located on the adhesive metal layer, the wire lining An opening is connected to the metal pad; and a wire bonding wire is connected to the wire bonding pad. 95. The wafer of claim 94, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 96. The wafer of claim 94, wherein the wire spacer further comprises an extension pad, wherein the extension pad is different from the opening of the protection layer in a top perspective view, Formed on the extension joint. 97. The wafer of claim 94, wherein the wire mat further comprises at least one soft metal layer having a thickness greater than 1 micron. 98. The wafer of claim 97, wherein the wire pad further comprises a copper layer underlying the nickel layer. 99. The wafer of claim 97, wherein the soft gold layer comprises a gold layer on which the gold layer is located. 100. The wafer of claim 94, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. The wafer of claim 100, wherein the dielectric layer comprises a polyimide. The wafer of claim 94, wherein the wire bonding pad has a thickness of between 1 micrometer and 5 micrometers. 103. The wafer of claim 94, wherein the wire mat is tied to the opening. 104. A wafer comprising at least: a substrate; a wiring structure layer on the surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal micro-circuit structure, the metal wiring structure > Interleaved in the dielectric structure, the metal micro-circuit structure includes a metal pad; a protective layer is disposed on the circuit structure layer, the protective layer has at least one opening extending through the protective layer and exposing the metal micro-circuit a wire gasket on the protective layer, the wire gasket is different from the opening in a top perspective view, and the wire gasket is connected to the metal pad via the opening, wherein the wire gasket includes a wire gasket a gold layer, and the gold layer has a thickness greater than 2 micrometers; and a t-wire conductor is attached to the wire bonding pad. 105. The wafer of claim 104, wherein the opening has a maximum pore size between 0.5 microns and 40 microns. 106. The wafer of claim 104, wherein the wire gasket further comprises at least one layer of soft metal having a thickness greater than 1 micron. 107. The wafer of claim 106, wherein the wire has a copper layer underlying the gold layer. 108. The wafer of claim 106, wherein the soft 36 I 1300963 metal layer comprises a nickel layer and a copper layer, the nickel layer being on the steel layer, and the gold layer is On the nickel layer. The wafer of claim 104, wherein the wire gasket further comprises a metal layer comprising titanium disposed between the wire bonding pad and the protective layer. 110. The wafer of claim 104, wherein the wire gasket further comprises a titanium-tungsten alloy layer positioned between the wire-bonding gasket and the protective layer. The wafer of claim 1, wherein the wire gasket further comprises a chrome layer positioned between the wire spacer and the protective layer. 112. The wafer of claim 1, wherein the wire gasket further comprises a titanium nitride compound layer positioned between the wire spacer and the protective layer. 113. The wafer of claim 104, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. 114. The wafer of claim 113, wherein the interposer layer comprises a polyimide. The wafer of claim 104, wherein the wire bond has a thickness of between 1 micrometer and 5 micrometers. a wafer comprising at least one substrate; 37 1300963 a line structure layer on the surface of the substrate, the circuit structure layer comprising a dielectric structure and a metal microcircuit structure, the metal microcircuit structure In the dielectric structure, the metal micro-circuit structure comprises a metal pad; a protective layer is disposed on the circuit structure layer, the protective layer has at least one opening through the protective layer and exposing the metal pad a wire slap on the metal pad, the wire screed comprising at least one adhesive metal layer and a nickel layer, the adhesive metal layer comprising a titanium nitride compound, wherein the nickel layer is on the adhesive metal layer, the wire gasket Connected to the metal crucible through the opening; and a wire bonding wire connected to the wire bonding pad. 117. The wafer of claim 116, wherein the opening has a maximum pore size between 55 microns and 4 microns. The wafer of claim 116, wherein the wire lining further comprises an extension pad, wherein the extension pad/the opening of the compliant layer is different in position from a top perspective view. The wire is formed on the extension pad. 119. The wafer of claim 116, wherein the smashing film further comprises at least - a thickness greater than! Micron soft metal layer. 120. The wafer of claim 119, wherein the wire spacer further comprises a copper layer underlying the nickel layer. The wafer of claim 119, wherein the soft metal layer comprises a gold layer on which the gold layer is located. 122. The wafer of claim 116 further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening The metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. 123. The wafer of claim 122, wherein the dielectric layer comprises polyimide. 124. The wafer of claim 116, wherein the wire bond is between 1 micrometer and 5 micrometers thick. 125. A wafer suitable for electrically connecting at least one wire to a wafer by a wire bonding process, the wafer comprising at least: a substrate comprising at least one active component; and a wiring structure layer on the substrate In a surface, the circuit structure layer comprises a dielectric structure and a metal micro-circuit structure interlaced in the dielectric structure, the metal micro-circuit structure comprises a metal raft; a protective layer is located at the On the circuit structure layer, the protective layer has at least one opening having a pore size of 0.5 micrometers to 40 micrometers, penetrates the protective layer and > exposes the metal pad; and a wire gasket is connected to the metal pad via the opening; And a dozen wire conductors 'connect the wire. 126. The wafer of claim 125, wherein the wire bonding pad further comprises an extension pad, the extension pad being different from the opening of the protection layer in a top perspective view, the wire Formed on the extension pad. 127. The wafer of claim 125, wherein the 39 1300963 wire gasket further comprises at least one soft metal layer having a thickness greater than 1 micrometer. 128. The wafer of claim 127, wherein the soft metal layer comprises a gold layer having a thickness greater than 2 microns. 129. The wafer of claim 127, wherein the soft metal layer comprises a copper layer having a thickness greater than 1 micron. 130. The wafer of claim 127, wherein the soft metal layer comprises a nickel layer having a thickness greater than 1 micron. 131. 如申請專利範圍第125項所述之晶片,其中,該打 線墊片還包括一含鈦之金屬層,位在該打線墊片與該保 護層之間。 132. 如申請專利範圍第125項所述之晶片,其中,該打 線墊片還包括一鈦鎢合金層,位在該打線墊片與該保護 層之間。 133. 如申請專利範圍第125項所述之晶片,其中,該打 線墊片還包括一鉻層,位在該打線墊片與該保護層之 間。 134. 如申請專利範圍第125項所述之晶片,其中,該打 線墊片還包括一鈦氮化合物層,位在該打線墊片與該保 護層之間。 135. 如申請專利範圍第125項所述之晶片,更包括一介 電層位在該保護層上,位在該介電層内之一開口暴露出 該保護層之該開口所暴露出之該金屬墊,且部分之該打 線接墊係位在該介電層上。 136. 如申請專利範圍第134項所述之晶片,其中,該介 1300963 電層包括聚醯亞胺(polyimide)。 137.如申請專利範圍第125項所述之晶片,其中,該打 線接墊之厚度係介於1微米至5微米之間。The wafer of claim 125, wherein the wire gasket further comprises a metal layer comprising titanium between the wire spacer and the protective layer. The wafer of claim 125, wherein the wire gasket further comprises a titanium-tungsten alloy layer positioned between the wire-bonding gasket and the protective layer. 133. The wafer of claim 125, wherein the wire gasket further comprises a chrome layer positioned between the wire spacer and the protective layer. 134. The wafer of claim 125, wherein the wire gasket further comprises a layer of titanium nitride compound between the wire spacer and the protective layer. 135. The wafer of claim 125, further comprising a dielectric layer on the protective layer, the opening in the dielectric layer exposing the opening of the protective layer exposed by the opening A metal pad, and a portion of the wire bonding pad is tied to the dielectric layer. 136. The wafer of claim 134, wherein the dielectric layer 1300963 comprises a polyimide. 137. The wafer of claim 125, wherein the wire bond is between 1 micron and 5 microns thick. 41 1300963 七、指定代表圖: (一) 本案指定代表圖為:第(7 )圖。 (二) 本代表圖之元件符號簡單說明: 428 ·•主動元件 434 :金屬微線路結構體 440 :保護層 442 ··開口 454 :打線墊片 460 ··軟性介電材質 462 :開孔 472 :引線 八、本案若有化學式時,請揭示最能顯示發明特徵的化學式:41 1300963 VII. Designated representative map: (1) The representative representative of the case is: (7). (2) A brief description of the component symbols of this representative diagram: 428 ·•Active component 434: Metal microcircuit structure 440: Protective layer 442 ·· Opening 454: Wire spacer 460 ··Soft dielectric material 462 : Opening 472 : Lead 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention:
TW095138283A 2002-09-25 2002-09-25 Structure of wire bonding over semiconductor chip TWI300963B (en)

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