1300645 九、發明說明： 【發明所屬之技術領域】 本發明有_〜種電翻服器之電源順序控制電 【先前技術】 兒 村学枝賴妙，電子製造#的高速發 的日常生活和工作㈣來越普及。人們在腦在人們 大的功能的同時也希望著電腦的價格越來越偏宜、。二=來越強 性價比成為推動電子產業界工作人員不斷探索的=腦， S^empsey伺服器系統用於控制諸如處理器、記2二3 式，針對此種情況，本發明作者提出了寫控制程 電路，其可簡化電路，節約成本，提^==易貫現之替換 【發明内容】 Λ t ° 妨畚ίί明？!目的在於提供一種電源順序控制電路及j：方牛苴 放棄了先所英特爾Dempsey飼服系統葬由接田=及”方法，其1300645 IX. Description of the invention: [Technical field to which the invention pertains] The present invention has a power supply sequence control system of the electric discharge device [Prior Art] The daily life and work of the high-speed transmission of the children's school (4) More and more popular. While people are brains in the big function of people, they also hope that the price of computers will become more and more appropriate. Second, the stronger the price/performance ratio has become the brain that drives the electronics industry to continuously explore, the S^empsey server system is used to control such as the processor, and the author of the present invention proposes write control. Circuit circuit, which can simplify the circuit and save cost, and replace it with ^== easy to replace [invention] Λ t ° 畚 畚 ί ί ? The purpose is to provide a power supply sequence control circuit and j: Fang Niu gave up the first Intel Dempsey feeding system to be buried by the field and the "method"
EPGA hxf3iR 控制器和小包裝的零件，卻達到了同樣的效果。㈣統邈輯 槪組電路、四降壓模提制ί”括-穩 按下電源按鈕後，得到一高雷平1味才t、、且电路，其猎由使用者 路，依次啟動各模組電路，藉此透過該穩顧組電 理器等，部件，北橋晶片、南橋晶片、中央處 理器飼服系原先英特爾De即sey令央處 -些供因的：：電:件為- 些小包裝零件，以及 積及降低了工成二具有=了咖電路板)的面 JMl不思我。另，本發明根據英特爾 1300645 關於電源配送指導以及電源與重置邏輯順序 特爾晶片組的使用規格。 k、凡王付σ央 為使對本發_目的、構造特徵及其功能有進—步的瞭解， 配合圖不詳細說明如下： 、 【實施方式】 參關1所示，其為本發明電路設計的方塊示賴。所 括五組電源滅，主要由電職源接頭的電源（ps—爾❿， Powei· Sufpply—Po· Gcx)d，電源供應良好）訊號1〇1控制兮 電源訊號101確定舰器電源是否開啟，其為高電平有效 啟後，該電源訊號m為高電平，其利用 ^ 依次給北橋晶片（MCH)、南橋晶片卿2)、全緩 g ^(FBDIMM,Fully-Buffered-Dual-Inllne-Mem〇^ Γ匯ΙΐΤΐΓSlde Bus)以及中央處理器核心電壓_ Vcore)提供工作電源。 一為避免该電源喊1〇1控制上述多組電源電壓的啟動時產生 衰弱現^ ’该電源訊號1〇1須先經過一穩壓模組1〇再輸入下一 組。巧壓模組10起到提高該訊號1〇1的負載驅動能力的作用： 而降壓模組20、3G、4G、6G起到降壓的作用，分別將各自輸 電，轉換為所需要的電壓，且各自致能端（Enable，簡稱EN) J 為冋電，吋動作同時電源良好端(p〇Wer G〇〇d，簡稱pG)輸出一高 電平訊號：另、，延時模組5°、7° _彳延時穩定各自輸人訊號的作 用，該訊號經過延時穩定後才輸入下一模組。 當使用者接通対腦電源接頭的電源後，該電源訊號101就 為高電平，其_穩顯組H)後輸出—高電伟號。第—降麵 組20之致能端⑽)接收到該高電平訊號後開始動作，其將電 入端⑽，壓P12V—F轉化為電源輸出端⑽τ)之第—電源訊號 源ίί，再分別送至北橋晶片⑽)和南橋晶 片（ESB2)作為，、工作電壓，同時，第一降壓模組2〇還輸出 平訊號PWRGD—1. 5V—MCH給下個模組。 1300645 PWRGD-L 5V-ra P1V8且於絲輸入端電壓P12^化為第二電源訊號 號pwi®，8V^衝=嵌f憶體模組，同時還輸出一高電平訊 拉弟二卜壓杈組40之致能端（EN)〇 組40開始動作’其將電源輸人端⑽電壓 好端ώ‘的—-ΐ 輸送，端匯流排，其電源良 後輸出一 VTT pwpr^ !：千讯唬猎由弟一延打模組50延時穩定作用 第四降顧线===，該敗_峨接著輸入到 並送入Λρ12ν，其輸出第四電源訊射—徹 至第^賴組频PG触的高電平訊號再送 哕電組70輸出一第五電源訊號SYS-PWRGD給The EPGA hxf3iR controller and the small packaged parts achieved the same effect. (4) Reconciliation of the group circuit, four step-down mode extraction ί" bracket - steady press the power button, get a high Leiping 1 flavor only t, and the circuit, its hunting by the user road, in turn start each module circuit Through this stable group of power processors, components, North Bridge chip, South Bridge chip, central processor feeding system, the original Intel De is the sey order office - some of the supply:: electricity: pieces for - some small package parts JMl does not bother me, and the invention is based on Intel 1300645 guidelines for power distribution and power and reset logic sequence. In order to make the understanding of the present _ purpose, structural features and functions, the details of the matching diagram are not described in detail as follows: [Embodiment] As shown in Figure 1, it is designed for the circuit of the present invention. The squares are shown. The five sets of power supply are eliminated, mainly by the power supply connector (ps-er, Powei·Sufpply-Po·Gcx), the power supply is good. Signal 1〇1 control 兮 power signal 101 determines the ship Whether the power of the device is turned on, it is high power After the effective start, the power signal m is a high level, which is used to sequentially give the north bridge chip (MCH), the south bridge chip 2), the full slow g ^ (FBDIMM, Fully-Buffered-Dual-Inllne-Mem〇^ ΙΐΤΐΓSlde Bus) and the central processing unit core voltage _ Vcore) provide working power. One is to avoid the power supply shouting 1〇1 control the above-mentioned multiple sets of power supply voltages when starting to weaken now ^ 'The power signal 1〇1 must pass a stable The pressure module 1〇 is then input to the next group. The pressure module 10 functions to increase the load driving capability of the signal 1〇1: and the step-down modules 20, 3G, 4G, and 6G function as a step-down function. The respective transmissions are converted into the required voltages, and the respective enable terminals (Enable, referred to as EN) J are 冋, the 吋 action and the power good end (p〇Wer G〇〇d, referred to as pG) output a high power Ping signal: In addition, the delay module 5°, 7° _彳 delay stabilizes the function of each input signal, and the signal is input into the next module after the delay is stabilized. When the user turns on the power of the camphor power connector The power signal 101 is at a high level, and its output is stable after the H) output - high power The enable terminal (10) of the first-down face group 20 starts to operate after receiving the high level signal, and converts the power input terminal (10) and the voltage P12V-F into the power source output terminal (10) τ) - the power signal source ίί, Then, it is sent to the north bridge chip (10) and the south bridge chip (ESB2) as the working voltage. At the same time, the first step-down module 2〇 also outputs the flat signal PWRGD-1. 5V-MCH to the next module. 1300645 PWRGD- L 5V-ra P1V8 and the voltage P12 at the input end of the wire is converted into the second power signal number pwi®, 8V ^ punch = embedded in the memory module, and also outputs a high level signal pull the second two pressure group 40 The enabling end (EN) 〇 group 40 starts to operate 'it will send the power input terminal (10) voltage end ώ '-- 输送 transport, end bus, its power supply will output a VTT pwpr^!: 千讯唬猎The fourth descending line ===, the defeat _峨 is then input to and sent to Λρ12ν, which outputs the fourth power signal--to the second group frequency PG touch The high level signal is sent to the power group 70 to output a fifth power signal SYS-PWRGD to
IntPrr>nnnM〇 入H牛連（PCI，Penpheral Component 部件送電的電Li序^件。藉此，伺服器完成啟動時給各功能 降壓m且3明ίίΐί於提供三種模組電路’即穩壓、 功能，進行減部件^^ I自依縣臨的致能峨完成各自的 本發明為實# ιοί 2 = S穩壓模組1G核心部分電路。電源訊號 « NTO 210 J ^ 弟NMOS210源極接地，其汲極藉由一電阻22 :第^咖的 1300645 …請參閱圖3所示，其為第一降壓模組2〇核心部 该電路採用了一整流器3〇〇,於本實施方式中苴梭用雔 (脈寬調製）控制和驅動積體電路（刪146)，該^器^ = 反相的工作，它能降低輸人和輸出濾波器的要求，藉此兩i 敗二2。其致能端（SS1/SD)接收到高電平訊號2301後而該 正抓态300開始工作。其電壓輸入端（vcm)經過一電阻，= 到一 P5V電源訊號上且同時該輸入端（VCH1)經過一電容 ^ 地。其輸出電壓回饋端（FBI)藉由一電阻33〇連接到1 ™ΓΓ} (FB1) =串連之紐連在該電阻330兩端。藉此，調= ί Ξ 值。f本_彳巾，賴議為1. G5 ^姆 2時’該整流器300的電源良好端⑽⑹還輸出一I: 給=個模組。3，降壓模組3G、4G、6Q轉照第 ^ 2路’根據輸人的P12V、簡、⑽電源訊號，調“電^ 麵組20中電阻33〇、電阻⑽的電阻之阻值/，、I 到所需之電源訊號HV8、P_VTT、PJ(XP。 兮:茶晒4所不，其為第—延時模組5G核心部分電路。 该氣路訊號輸入端訊號4〇〇1依次串連一電阻41〇、一 電阻並連一二極體傷，且該二極體43 ^ ^ ^接該電容。另，該電容420 一端接地，另二ί 兮妾到-起隔離内外部電路且能穩定訊號作用的緩衝器姻 =衝器、440輸出訊號棚2。該電路中，藉由調節電阻細 各420可以調節該電路的延時時間，電阻之阻值和電^电 J電容值的乘積即為所需的延時時間。於本實 =55. 容，1微法特，其乘積即為戶^的^ Γ ，延時模組70也可參照該延時模組5〇的電 路，调整其相應於電阻權及電阻伽之電阻阻值，得到所= 1300645 時的時間。 全邱，=出本务明的實質重點，故上述並非為實施本發明的 S，ϊί”知電路部分以及重複類似部分均有所略去3 負述、参照本實施方式完全可再ί見本發日月。 作 限定施?含本= 月il，佳實施例而已，並非用來 艾化與修飾，料本發明專利範騎涵蓋。 彳作的均專 【圖式簡單說明】 圖1為本發明電路設計的方塊示意圖。 圖2為穩壓模組1〇核心部分電路。 圖3為第一降壓模組2〇核心部分電路。 圖4為第一延時模組50核心部分電路。 101 10 20 30 40 50 60 70 210 220 230 240 300 310 320 330 【主要元件符號說明】 ° 電源訊號 穩壓模組 第一降壓模組 第二降壓模組 第三降壓模組 第一延時模組 第四降壓模組 第二延時模組 第一 NM0S電晶體 電阻 第二NM0S電晶體 電容 整流器 第一電阻 第一電容 第二電阻 9 1300645 340 第三電阻 ’ 350 第二電容 360 第四電阻 2301 南電平訊號 3001 訊號 4001 訊號 4002 訊號 410 電阻 420 電容 φ 430 二極體 440 反向器IntPrr>nnnM breaks into the H cattle connection (PCI, the Penthal Component component power supply Li sequence device. By this, when the server completes the startup, the function is stepped down and the three modules are provided. Function, to reduce the part ^ ^ I from the county to enable the completion of the invention of the invention # ιοί 2 = S voltage regulator module 1G core part of the circuit. Power signal « NTO 210 J ^ Brother NMOS210 source grounded, The bungee pole is provided by a resistor 22: 1300645 of the second coffee ... Please refer to FIG. 3 , which is the first step-down module 2 〇 core part, the circuit adopts a rectifier 3 〇〇, in this embodiment 苴The shuttle uses 雔 (pulse width modulation) to control and drive the integrated circuit (deleted 146). The ^^^ is inverted, which reduces the input and output filter requirements, thereby reducing the two. After the enable terminal (SS1/SD) receives the high level signal 2301 and the positive grab state 300 starts to work, its voltage input terminal (vcm) passes through a resistor, = to a P5V power signal and at the same time the input terminal (VCH1) Passing through a capacitor, its output voltage feedback terminal (FBI) is connected to 1 TM by a resistor 33〇 (FB1) = the series of new contacts are connected across the resistor 330. By this, the value of 调 ί 。 f f 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖 赖Also output an I: give = module. 3, buck module 3G, 4G, 6Q transfer the ^ 2 way 'according to the input P12V, simple, (10) power signal, adjust the "electricity ^ 20 resistance 33〇, the resistance of the resistor (10) /, I to the required power signal HV8, P_VTT, PJ (XP. 兮: tea drying 4, it is the first delay module 5G core part of the circuit. The signal input signal 4〇〇1 is connected in series with a resistor 41〇, a resistor and a diode wound, and the diode 43 ^ ^ ^ is connected to the capacitor. In addition, the capacitor 420 is grounded at one end, and the other ί 兮妾 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到The product of the resistance value and the electric capacitance J is the required delay time. In this case, the actual value is 55. The capacity is 1 microfarad, and the product is the ^^ of the household ^, and the delay module 70 can also refer to The circuit of the delay module 5〇 adjusts the resistance value corresponding to the resistance weight and the resistance gamma to obtain the time when the voltage is 1300645. All of Qiu, = the essential focus of the present invention, so the above is not for the implementation of the present invention. S, ϊί" knows that the circuit part and the repeated similar parts have omitted the three negative descriptions, and the present embodiment can fully refer to the present day and the month. The limited application includes the present = month il, the preferred embodiment is only used. To Aihua and the modification, it is expected that the patent of the invention is covered by Fan. Detailed Description of the Drawings [Schematic Description of the Drawings] Fig. 1 is a block diagram showing the circuit design of the present invention. Figure 2 shows the core part circuit of the voltage regulator module. FIG. 3 is a circuit diagram of the core part of the first step-down module 2 . 4 is a circuit diagram of a core portion of the first delay module 50. 101 10 20 30 40 50 60 70 210 220 230 240 300 310 320 330 [Main component symbol description] ° Power signal regulator module first step-down module second step-down module third step-down module first delay Module fourth step-down module second delay module first NM0S transistor resistance second NM0S transistor capacitor rectifier first resistor first capacitor second resistor 9 1300645 340 third resistor '350 second capacitor 360 fourth resistor 2301 South Level Signal 3001 Signal 4001 Signal 4002 Signal 410 Resistance 420 Capacitor φ 430 Diode 440 Inverter