TWI399909B - Power conversion system and power control method for reducing different regulation effect - Google Patents
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本發明係關於一種電源轉換系統,特別是關於一種應用於單電感多輸出直流/直流轉換器之減少互穩壓效應之電源轉換系統與電源控制方法。The present invention relates to a power conversion system, and more particularly to a power conversion system and a power supply control method for reducing mutual voltage stabilization effects of a single inductor multi-output DC/DC converter.
現今電源管理晶片已廣泛應用於手機、PDA、筆記型電腦等可攜式電子產品。在系統晶片發展的趨勢下,為了減少晶片面積,將採用單電感多輸出直流/直流轉換器的架構。然而,此多輸出架構將存有穩定度不佳與互穩壓效應的問題。Today's power management chips are widely used in portable electronic products such as mobile phones, PDAs, and notebook computers. In the trend of system chip development, in order to reduce the chip area, a single-inductor multi-output DC/DC converter architecture will be adopted. However, this multi-output architecture will have problems with poor stability and mutual voltage regulation.
傳統主要為將多輸出相互獨立,使得輸出端不被彼此負載變化所干擾,以解決互穩壓效應問題。可利用連續假導通(Pseudo-CCM)電流技術,整體系統有如不連續電流模式(DCM)的狀態,將使系統易於穩定。且由於具有相當於不連續電流模式之零電流,每個切換週期內具有一緩衝階段,使得瞬間負載變化不會影響下一週期,以減少互穩壓效應。然而,此方式必須在整個脈衝寬度調變(PWM)週期內加入一續流(Freewheel)階段,由於非理想導通開關的等效電組效應,將使大量功率會於此階段內消耗,整體系統的導通損(Conduction Loss)將因此增加,進而影響效率轉換。此外,續流階段電感中儲存的能量無法傳至輸出端,平均電感電流將大於輸出負載的總和。且因單電感多輸出模組架構之輸出電感電流不連續的特性,較大的平均電感電流會造成較大之輸出電壓漣波,因此,需一高效能後級穩壓電路對輸出電壓進一步處理。The tradition is mainly to make the multiple outputs independent of each other, so that the output terminals are not interfered by the load changes of each other to solve the mutual voltage regulation effect problem. Continuous pseudo-conduction (Pseudo-CCM) current technology can be used, and the overall system has a state like discontinuous current mode (DCM), which will make the system easy to stabilize. And because it has a zero current equivalent to the discontinuous current mode, there is a buffer phase in each switching cycle, so that the instantaneous load change does not affect the next cycle to reduce the mutual voltage stabilization effect. However, this mode must be added to the Freewheel phase throughout the Pulse Width Modulation (PWM) cycle. Due to the equivalent group effect of the non-ideal turn-on switch, a large amount of power will be consumed during this phase. The conduction loss (Conduction Loss) will increase, which in turn affects the efficiency conversion. In addition, the energy stored in the inductor during the freewheeling phase cannot be transmitted to the output, and the average inductor current will be greater than the sum of the output loads. Due to the discontinuous output inductor current of the single-inductor multi-output module architecture, a large average inductor current will cause a large output voltage ripple. Therefore, a high-performance post-stage voltage regulator circuit is required to further process the output voltage. .
另一種做法,為採取優先次序能量分配流程。然而,此方式僅僅適用於某特定之負載狀態,並且其係利用比較器控制輸出電壓,相較於閉迴路中採用誤差放大器做控制,整體穩壓效果不盡理想。Another approach is to prioritize the energy distribution process. However, this method is only applicable to a specific load state, and it uses the comparator to control the output voltage. Compared with the closed loop, the error amplifier is used for control, and the overall voltage regulation effect is not satisfactory.
此外,可使用電感搭配電荷幫浦(Charge Pump)的架構。不過,此架構必須額外使用外部電容與二極體,且會有較大的輸出電壓漣波。並且由於負電壓輸出係由電荷幫浦達成,因此,負電壓輸出會有較差的穩壓情況,實際應用上相當不理想。In addition, an inductor can be used in conjunction with the charge pump architecture. However, this architecture must additionally use external capacitors and diodes, and there will be a large output voltage ripple. And because the negative voltage output is achieved by the charge pump, the negative voltage output will have a poor voltage regulation, which is quite unsatisfactory in practical applications.
有鑑於此,本發明係針對上述該些困擾與目標,同時結合電子電路技術與能量控制概念,提出一減少互穩壓效應之電源轉換系統與電源控制方法。In view of the above, the present invention is directed to the above-mentioned problems and targets, and at the same time, combining the electronic circuit technology and the energy control concept, proposes a power conversion system and a power supply control method for reducing mutual voltage stabilization effects.
本發明之主要目的係在提供一種減少互穩壓效應之電源轉換系統與電源控制方法,其係利用電壓迴授調整電路調變誤差訊號,以有效消除互穩壓效應,達到穩定之雙輸出電源。The main object of the present invention is to provide a power conversion system and a power supply control method for reducing the mutual voltage stabilizing effect, which utilizes a voltage feedback adjustment circuit to adjust the error signal to effectively eliminate the mutual voltage stabilization effect and achieve a stable dual output power supply. .
本發明之另一目的係在提供一種減少互穩壓效應之電源轉換系統與電源控制方法,其係利用預先偵測輸出電壓能量變化,反應輸出端負載狀態變動情況,以快速調整系統責任週期,使得系統具備良好輸出穩態與暫態響應,功率轉換效率極佳。Another object of the present invention is to provide a power conversion system and a power supply control method for reducing the mutual voltage stabilizing effect, which utilizes a pre-detection of an output voltage energy change and a reaction load state change at the output end to quickly adjust the system duty cycle. The system has good output steady state and transient response, and the power conversion efficiency is excellent.
本發明之又一目的係在提供一種減少互穩壓效應之電源轉換系統與電源控制方法,其係可整合於各式電源管理模組,實際應用層面極為廣泛。Another object of the present invention is to provide a power conversion system and a power supply control method for reducing mutual voltage stabilization effects, which can be integrated into various power management modules, and the practical application level is extremely wide.
為達到上述之目的,本發明提出之減少互穩壓效應之電源轉換系統,其係包括一開關電路、一電流偵測器、複數個誤差放大器、一電壓迴授調整電路、一峰值產生器、一比較器組與一控制電路。開關電路電性連接至少一電感,藉由開關電路之開啟與閉合控制電感之充放電,以輸出複數個輸出電壓,且流經電感之電感電流將藉由電流偵測器偵測,以感測電感電壓。並且誤差放大器接收迴授之輸出電壓,計算輸入電壓之誤差訊號。電壓迴授調整電路係接收與調變誤差訊號,產生複數個誤差調變訊號。且誤差調變訊號將經由峰值產生器所接收,產生峰值電壓。並且以比較器組將誤差調變訊號與峰值電壓及電感電壓分別與電感電壓比較,產生複數個電壓訊號,且電壓訊號經由控制電路接收,以產生複數個控制訊號用以控制開關電路,控制電感之充放電。In order to achieve the above object, the power conversion system for reducing the mutual voltage stabilization effect of the present invention comprises a switching circuit, a current detector, a plurality of error amplifiers, a voltage feedback adjustment circuit, a peak generator, A comparator group and a control circuit. The switch circuit is electrically connected to at least one inductor, and the charge and discharge of the control inductor is turned on and off by the switch circuit to output a plurality of output voltages, and the inductor current flowing through the inductor is detected by the current detector to sense Inductor voltage. And the error amplifier receives the feedback output voltage and calculates the error signal of the input voltage. The voltage feedback adjustment circuit receives and modulates the error signal to generate a plurality of error modulation signals. And the error modulation signal will be received by the peak generator to generate a peak voltage. And comparing the error modulation signal and the peak voltage and the inductor voltage with the inductor voltage by the comparator group to generate a plurality of voltage signals, and the voltage signal is received by the control circuit to generate a plurality of control signals for controlling the switch circuit and controlling the inductance Charge and discharge.
本發明提出之減少互穩壓效應之電源控制方法,其步驟係包括,首先,依據複數個輸出電壓之負載狀態,計算複數個輸出電壓之各別誤差訊號。之後,調變誤差訊號,計算符合負載狀態之輸出電壓之能量,並產生複數個誤差調變訊號。接著,依據誤差調變訊號計算峰值電壓,並藉由峰值電壓計算充放電週期之能量總值,使得充電周期之能量總值為系統所需之總能量,放電週期之能量總值為輸出電壓之能量的總合。最後,依據峰值電壓充電至至少一電感,電感係將儲存充電周期之能量總值。The power control method for reducing mutual voltage stabilization effect proposed by the present invention comprises the steps of: first, calculating respective error signals of a plurality of output voltages according to load states of the plurality of output voltages. After that, the error signal is modulated, the energy of the output voltage according to the load state is calculated, and a plurality of error modulation signals are generated. Then, the peak voltage is calculated according to the error modulation signal, and the total energy value of the charge and discharge cycle is calculated by the peak voltage, so that the total energy of the charging cycle is the total energy required by the system, and the total energy of the discharge cycle is the output voltage. The sum of energy. Finally, charging to at least one inductor based on the peak voltage, the inductor will store the total energy of the charging cycle.
底下藉由具體實施例配合所附的圖式詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.
本發明提出一種減少互穩壓效應之電源轉換系統與電源控制方法,其係利用迴授控制,於輸出端負載狀態變動時,預先偵測輸出端能量的變化,使得系統能夠依據負載狀態調整責任週期,快速驅於穩態,以降低互穩壓效應(Cross Regulation)的發生。底下則將以較佳實施例詳述本發明之技術特徵。The invention provides a power conversion system and a power supply control method for reducing the mutual voltage stabilizing effect, which utilizes feedback control to detect the change of the energy of the output end in advance when the load state of the output changes, so that the system can adjust the responsibility according to the load state. Cycles, quickly driving steady state, to reduce the occurrence of the Cross Regulation. The technical features of the present invention will be described in detail below with reference to preferred embodiments.
第一圖為本發明電路架構之示意圖,如圖所示,一開關電路50電性連接至少一電感L,其包含有複數個電晶體開關M1 、M2 與M3 ,透過控制電晶體開關M1 、M2 與M3 開啟或閉合控制電感L充放電,以輸出正輸出電壓(Vop )與負輸出電壓(Von )。且流經電感L上之電感電流將透過一電流偵測器52進行偵測,以感測出電感L之電感電壓(Vs )。The first figure is a schematic diagram of the circuit architecture of the present invention. As shown in the figure, a switch circuit 50 is electrically connected to at least one inductor L, which includes a plurality of transistor switches M 1 , M 2 and M 3 , and a control transistor switch. M 1 , M 2 and M 3 turn on or off to control the charge and discharge of the inductor L to output a positive output voltage (V op ) and a negative output voltage (V on ). The inductor current flowing through the inductor L is detected by a current detector 52 to sense the inductor voltage (V s ) of the inductor L.
輸出之正輸出電壓(Vop )及負輸出電壓(Von )將分別經由電阻(Rp1 )與電阻(Rp1 )以及電阻(Rn1 )與電阻(Rn1 )分壓成為迴授電壓(Vfp )與迴授電壓(Vfn )迴授至誤差放大器(EA)54與56,且誤差放大器(EA)54與56係以參考電壓(Vref )為基準,產生正輸出電壓誤差訊號(Vep )及負輸出電壓誤 差訊號(Ven )。The output positive output voltage (V op ) and the negative output voltage (V on ) are respectively divided into resistance voltages via resistors (R p1 ) and resistors (R p1 ) and resistors (R n1 ) and resistors (R n1 ). V fp ) and the feedback voltage (V fn ) are fed back to the error amplifiers (EA) 54 and 56, and the error amplifiers (EA) 54 and 56 are based on the reference voltage (V ref ) to generate a positive output voltage error signal ( V ep ) and negative output voltage error signal (V en ).
正輸出電壓誤差訊號(Vep )及負輸出電壓誤差訊號(Ven )係經由與誤差放大器(EA)54、56電性連接之一電壓迴授調整電路58接收,其係將正輸出電壓誤差訊號(Vep )、負輸出電壓誤差訊號(Ven )相互迴授,正輸出電壓誤差訊號(Vep )係利用迴授之負輸出電壓誤差訊號(Ven )進行電壓位準的調變,產生正輸出電壓誤差調變訊號(Vemp );負輸出電壓誤差訊號(Ven )係利用迴授之正輸出電壓誤差訊號(Vep )進行電壓位準的調變,產生負輸出電壓誤差調變訊號(Vemn )。The positive output voltage error signal (V ep ) and the negative output voltage error signal (V en ) are received via a voltage feedback adjustment circuit 58 electrically coupled to the error amplifiers (EA) 54 , 56 , which are positive output voltage errors The signal (V ep ) and the negative output voltage error signal (V en ) are mutually feedback, and the positive output voltage error signal (V ep ) is used to adjust the voltage level by using the feedback negative output voltage error signal (V en ). A positive output voltage error modulation signal (V emp ) is generated; a negative output voltage error signal (V en ) is a voltage output level modulation using a feedback positive output voltage error signal (V ep ) to generate a negative output voltage error adjustment Change signal (V emn ).
正輸出電壓誤差調變訊號(Vemp )及負輸出電壓誤差調變訊號(Vemn )再將輸入至與電壓迴授調整電路58電性連接之一峰值產生器60,其係利用正輸出電壓誤差調變訊號(Vemp )與負輸出電壓誤差調變訊號(Vemn )產生峰值電壓(Vepn )。此峰值電壓將為電感L之充電週期內最大的充電限制。The positive output voltage error modulation signal (V emp ) and the negative output voltage error modulation signal (V emn ) are further input to a peak generator 60 electrically connected to the voltage feedback adjustment circuit 58 , which utilizes a positive output voltage. The error modulation signal (V emp ) and the negative output voltage error modulation signal (V emn ) generate a peak voltage (V epn ). This peak voltage will be the maximum charge limit during the charging cycle of inductor L.
一比較器組(CMP)62係與電流偵測器52、電壓迴授調整電路58及峰值產生器60電性連接,且接收電感電壓(Vs )、峰值電壓(Vepn )與正輸出電壓誤差調變訊號(Vemp ),並將峰值電壓(Vepn )以及正輸出電壓誤差調變訊號(Vemp )分別與電感電壓(Vs )進行比較,產生複數個電壓訊號(VCAB )與(VCA ),並且電壓訊號(VCAB )與(VCA )將傳送至一控制電路64。控制電路64包含一路徑決策邏輯641與一偏壓調整電路642,路徑決策邏輯641係接收電壓訊號(VCAB )與(VCA )以及系統時脈訊號(Vclk ),控制偏壓調整電路642產生控制訊號VG1 、VG2 與VG3 ,以控制開關電路50之電晶體開關M1 、M2 與M3 開啟或閉合,以達到控制電感L之充放電。A comparator group (CMP) 62 is electrically connected to the current detector 52, the voltage feedback adjustment circuit 58 and the peak generator 60, and receives the inductor voltage (V s ), the peak voltage (V epn ) and the positive output voltage. The error modulation signal (V emp ) compares the peak voltage (V epn ) and the positive output voltage error modulation signal (V emp ) with the inductor voltage (V s ) to generate a plurality of voltage signals (V CAB ) and (V CA ), and the voltage signals (V CAB ) and (V CA ) will be transmitted to a control circuit 64. The control circuit 64 includes a path decision logic 641 and a bias adjustment circuit 642. The path decision logic 641 receives the voltage signals (V CAB ) and (V CA ) and the system clock signal (V clk ), and controls the bias adjustment circuit 642. The control signals V G1 , V G2 and V G3 are generated to control the transistor switches M 1 , M 2 and M 3 of the switch circuit 50 to be turned on or off to achieve charge and discharge of the control inductor L.
此外,一斜率補償器68係電性連接電流偵測器52,用以補償電感電流變動所產生之次諧波振盪,以及產生所需之系統時脈訊號(Vclk )。且參考電壓(Vref )及負輸出電壓(Von )分壓側之電壓(Vnn )將由一能隙參考電路70產生。並且一基體切換電路66設置於開關電路50之電晶體開關M3 ,防止基體效應。另外,電壓迴授調整電路58係可與誤差放大器(EA)54及56整合。In addition, a slope compensator 68 is electrically coupled to the current detector 52 for compensating for subharmonic oscillations caused by variations in the inductor current and for generating a desired system clock signal (V clk ). And the voltage (V nn ) on the voltage dividing side of the reference voltage (V ref ) and the negative output voltage (V on ) will be generated by a band gap reference circuit 70. And a substrate switching circuit 66 is provided to the transistor switch M 3 of the switching circuit 50 to prevent the matrix effect. Additionally, voltage feedback adjustment circuit 58 can be integrated with error amplifiers (EA) 54 and 56.
以上為本發明之電路系統架構的詳細說明,底下將對於本發明電源控制方法做進一步說明。The above is a detailed description of the circuit system architecture of the present invention, and the power control method of the present invention will be further described below.
第二圖為本發明電源控制之流程圖,請同實參閱第一圖,如圖所示,首先,如步驟S10,誤差放大器(EA)54與56依據輸出電壓(Vop )及(Von )之負載狀態所迴授之迴授電壓(Vfp )及(Vfn ),計算輸出電壓之誤差訊號(Vep )及(Ven )。The second figure is a flow chart of the power control of the present invention. Please refer to the first figure as shown in the figure. First, as step S10, the error amplifiers (EA) 54 and 56 are based on the output voltage (V op ) and (V on The feedback voltages (V fp ) and (V fn ) that are fed back by the load state calculate the error signals (V ep ) and (V en ) of the output voltage.
之後,如步驟S12,電壓迴授調整電路58調變誤差訊號(Vep )及(Ven ),產生誤差調變訊號(Vemp )及(Vemn ),以使得輸出電壓之能量與負載狀態相符合。Then, in step S12, the voltage feedback adjustment circuit 58 modulates the error signals (V ep ) and (V en ) to generate an error modulation signal (V emp ) and (V emn ) to make the energy and load state of the output voltage. Compatible.
接著,如步驟S14,峰值產生器60依據誤差調變訊號(Vemp )及(Vemn )計算峰值電壓(Vepn ),藉由峰值電壓(Vepn )計算充放電週期之能量總值,此峰值電壓(Vepn )係為充電周期之最大充電限制,充電周期之能量總值將為系統所需之總能量,並且放電週期之能量總值係為輸出電壓之能量的總合。Next, in step S14, the peak generator 60 calculates the peak voltage (V epn ) according to the error modulation signals (V emp ) and (V emn ), and calculates the total energy value of the charge and discharge cycle by the peak voltage (V epn ). The peak voltage (V epn ) is the maximum charging limit of the charging cycle. The total energy of the charging cycle will be the total energy required by the system, and the total energy of the discharging cycle is the sum of the energy of the output voltage.
最後,如步驟S16,依據峰值電壓(Vepn )充電至電感L,電感L將儲存充電周期之能量總值。Finally, as in step S16, charging to the inductance L according to the peak voltage (V epn ), the inductance L will store the total energy value of the charging period.
上述為本發明之電源控制方法的說明,底下將以能量觀點,對於本發明在負載狀態變動時,透過預先偵測輸出電壓能量變化,達到減少互穩壓效應加以進一步說明。The above description of the power control method of the present invention will further explain the effect of reducing the mutual voltage regulation effect by detecting the change of the output voltage energy in advance when the load state fluctuates according to the present invention.
第三圖為本發明電感充放電週期之波形圖,並請同時參閱第一圖之電路架構示意圖與第二圖之電源控制流程圖,以及第四(a)圖與第四(b)圖之正負輸出電壓能量變化示意圖,如圖所示,於穩態時,輸出電壓之能量分別為負輸出電壓能量20與正輸出電壓能量22。在考慮未設置電壓迴授調整電路58的情況下,當正輸出電壓(Vop )之負載狀態變化,負輸出電壓(Von )之負載狀態不變時,由於正輸出電流(Iop )將突然增加,正輸出電壓誤差訊號(Vep )係上升,連帶使得峰值電壓(Vepn )上升。因此,負輸出電壓能量20及正輸出電壓能量22係將增加為負輸出電壓能量30及正輸出電壓能量32。然而,由於負輸出電壓(Von )之負載狀態並未變化,負輸出電壓能量20確增加成為負輸出電壓能量30,此時互穩壓效應即發生。The third figure is a waveform diagram of the charge and discharge cycle of the inductor of the present invention, and please refer to the circuit diagram of the first figure and the power control flow chart of the second figure, and the fourth (a) and fourth (b) Schematic diagram of positive and negative output voltage energy changes, as shown, at steady state, the output voltage energy is negative output voltage energy 20 and positive output voltage energy 22, respectively. Considering that the voltage feedback adjustment circuit 58 is not provided, when the load state of the positive output voltage (V op ) changes and the load state of the negative output voltage (V on ) does not change, since the positive output current (I op ) will Suddenly, the positive output voltage error signal (V ep ) rises, causing the peak voltage (V epn ) to rise. Therefore, the negative output voltage energy 20 and the positive output voltage energy 22 will increase to a negative output voltage energy 30 and a positive output voltage energy 32. However, since the load state of the negative output voltage ( Von ) does not change, the negative output voltage energy 20 does increase to become the negative output voltage energy 30, at which time the mutual voltage regulation effect occurs.
故藉由電壓迴授調整電路58在正輸出電壓(Vop )負載狀態變化,正輸出電流(Iop )增加時,對正輸出電壓誤差訊號(Vep )及負輸出電壓誤差訊號(Ven )進行調變,利用相互迴授方式,拉升正輸出電壓誤差訊號(Vep )位準,成為正輸出電壓誤差調變訊號(Vemp ),同時降低負輸出電壓誤差訊號(Ven )位準,成為負輸出電壓誤差調變訊號(Vemn )。如此將能夠下拉峰值電壓(Vepn ),使得正輸出電流(Iop )變動的瞬間,負輸出電壓能量40與負輸出電壓能量20相等,僅有正輸出電壓能量22增加為正輸出電壓能量42。因此,在同一脈衝寬度調變(PWM)週期內,負載狀態未有變化之負輸出電壓(Von )所獲得的能量並不有所變化,將不會發生輸出電壓變異的互穩壓效應。Therefore, when the positive output voltage (V op ) load state changes by the voltage feedback adjustment circuit 58 and the positive output current (I op ) increases, the positive output voltage error signal (V ep ) and the negative output voltage error signal (V en ) Modulation, using the mutual feedback method, pull up the positive output voltage error signal (V ep ) level, become the positive output voltage error modulation signal (V emp ), and reduce the negative output voltage error signal (V en ) It becomes a negative output voltage error modulation signal (V emn ). Thus, the peak voltage (V epn ) can be pulled down so that the positive output current (I op ) changes, the negative output voltage energy 40 is equal to the negative output voltage energy 20, and only the positive output voltage energy 22 is increased to the positive output voltage energy 42. . Therefore, during the same pulse width modulation (PWM) period, the energy obtained by the negative output voltage (V on ) whose load state has not changed does not change, and the mutual voltage stabilizing effect of the output voltage variation will not occur.
以上為正輸出電壓(Vop )負載狀態變化,正輸出電流(Iop )增加之狀態說明。其他各種負載狀態下之負載電流、迴授電壓、誤差調變訊號、峰值電壓之變化情形係如表(1)所示。相對應之能量變化情形係可依據電壓、電流變化進而推知,在此不在加以贅述。The above is a description of the state in which the positive output voltage (V op ) load state changes and the positive output current (I op ) increases. The changes of load current, feedback voltage, error modulation signal and peak voltage under various other load conditions are shown in Table (1). The corresponding energy change situation can be inferred according to the voltage and current changes, and will not be described here.
經由上述實施例說明可知本發明係將藉由電壓迴授調整電路58調變誤差訊號,達到依據負載狀態,預先偵測輸出電壓能量的目的。使得充電週期之能量為系統所需之總能量,且負載未變化之輸出電壓的能量將保持固定,大幅消除降低互穩壓效應,系統將具有極佳輸出穩態與暫態響應。此外,本發明係適用於非隔離式之昇壓式、降壓式、昇降壓式電源轉換電路及隔離式之順向式、全橋式、半橋式、推挽式之電源轉換電路等各式電源轉換電路及電源轉換電路組合。It can be seen from the above description that the present invention will adjust the error signal by the voltage feedback adjustment circuit 58 to achieve the purpose of detecting the output voltage energy in advance according to the load state. The energy of the charging cycle is the total energy required by the system, and the energy of the output voltage of the unchanging load will remain fixed, greatly eliminating the effect of reducing the mutual voltage regulation, and the system will have excellent output steady state and transient response. In addition, the present invention is applicable to non-isolated boost, buck, buck-boost power conversion circuits and isolated forward, full-bridge, half-bridge, push-pull power conversion circuits, etc. Combination of power conversion circuit and power conversion circuit.
以上所述之實施例僅係為說明本發明之技術思想及特點,其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施,當不能以之限定本發明之專利範圍,即大凡依本發明所揭示之精神所作之均等變化或修飾,仍應涵蓋在本發明之專利範圍內。The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.
20‧‧‧負輸出電壓能量20‧‧‧Negative output voltage energy
22‧‧‧正輸出電壓能量22‧‧‧ Positive output voltage energy
30‧‧‧負輸出電壓能量30‧‧‧Negative output voltage energy
32‧‧‧正輸出電壓能量32‧‧‧ Positive output voltage energy
40‧‧‧負輸出電壓能量40‧‧‧Negative output voltage energy
42‧‧‧正輸出電壓能量42‧‧‧ Positive output voltage energy
50‧‧‧開關電路50‧‧‧Switch circuit
52‧‧‧電流偵測器52‧‧‧ Current Detector
54‧‧‧誤差放大器54‧‧‧Error amplifier
56‧‧‧誤差放大器56‧‧‧Error amplifier
58‧‧‧電壓迴授調整電路58‧‧‧Voltage feedback adjustment circuit
60‧‧‧峰值產生器60‧‧‧peak generator
62‧‧‧比較器組62‧‧‧Comparator group
64‧‧‧控制電路64‧‧‧Control circuit
641‧‧‧路徑決策邏輯641‧‧‧Path Decision Logic
642‧‧‧偏壓調整電路642‧‧‧bias adjustment circuit
66‧‧‧基體切換電路66‧‧‧Base switching circuit
68‧‧‧斜率補償器68‧‧‧Slope compensator
70‧‧‧能隙參考電路70‧‧‧Gap reference circuit
第一圖為本發明電路架構之示意圖。The first figure is a schematic diagram of the circuit architecture of the present invention.
第二圖為本發明電源控制之流程圖。The second figure is a flow chart of the power control of the present invention.
第三圖為本發明電感充放電週期之波形圖。The third figure is a waveform diagram of the charge and discharge cycle of the inductor of the present invention.
第四(a)圖為本發明負輸出電壓能量變化之示意圖。The fourth (a) diagram is a schematic diagram of the change in the energy of the negative output voltage of the present invention.
第四(b)圖為本發明正輸出電壓能量變化之示意圖。The fourth (b) diagram is a schematic diagram of the positive output voltage energy variation of the present invention.
50...開關電路50. . . Switch circuit
52...電流偵測器52. . . Current detector
54...誤差放大器54. . . Error amplifier
56...誤差放大器56. . . Error amplifier
58...電壓迴授調整電路58. . . Voltage feedback adjustment circuit
60...峰值產生器60. . . Peak generator
62...比較器組62. . . Comparator group
64...控制電路64. . . Control circuit
641...路徑決策邏輯641. . . Path decision logic
642...偏壓調整電路642. . . Bias adjustment circuit
66...基體切換電路66. . . Substrate switching circuit
68...斜率補償器68. . . Slope compensator
70...能隙參考電路70. . . Bandgap reference circuit
Claims (17)
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| US11581795B2 (en) | 2020-07-22 | 2023-02-14 | Mediatek Inc. | Current sensing circuit for generating sensed current signal with average value being constant under different input voltages of direct current to direct current converter and associated current-mode control circuit |
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| US6057607A (en) * | 1999-07-16 | 2000-05-02 | Semtech Corporation | Method and apparatus for voltage regulation in multi-output switched mode power supplies |
| TW200514341A (en) * | 2003-10-08 | 2005-04-16 | Univ Nat Cheng Kung | Single-stage isolation-type high-power-factor power converter |
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| US6057607A (en) * | 1999-07-16 | 2000-05-02 | Semtech Corporation | Method and apparatus for voltage regulation in multi-output switched mode power supplies |
| TW200514341A (en) * | 2003-10-08 | 2005-04-16 | Univ Nat Cheng Kung | Single-stage isolation-type high-power-factor power converter |
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