TWI714204B - Three quarter bridge for buck-derived switch-mode power supplies - Google Patents

Abstract

Some apparatus and associated methods relate to a three quarter bridge (TQB) applied across an output inductor of a buck-derived power converter， the TQB operated in a first mode such that when a high-side switch of the power converter is turned on， the TQB configured to pass a first controlled current to combine with a first output inductor current to a load， the TQB configured to control the first controlled current to minimize a negative voltage transient on the load， the TQB operated in a second mode such that when the high-side switch of the power converter is turned off the TQB configured to divert a second controlled current away from the load and to circulate the second controlled current through the output inductor， the TQB configured to control the second controlled current to minimize a positive voltage transient on the output of the power converter.

Description

Three-quadrant bridge for step-down derivative switch mode power supply

The present invention is a three-quadrant bridge used for step-down derivative switch mode power supplies. At the same time, this application is a partial continuation of the US patent, which requires US Patent No. 16/029,407 filed on July 6, 2018 Rights to apply. This application also requires the filing of the relevant rights and interests of the US provisional patent application No. 62/642,717 on March 14, 2018. This application hereby incorporates each of the aforementioned applications as a whole into this case by reference.

Press, electronic devices receive power in various ways. For example, consumer electronic devices can receive power from a wall socket (eg, power supply) or from various portable power sources (eg, batteries, renewable energy, generators). Battery-powered devices have operating times that depend on battery capacity and average current consumption. Manufacturers of battery-powered devices can work to reduce the average battery current of their products in order to provide longer device usage between battery replacement or charging operations. In some examples, manufacturers of utility power equipment may strive to improve the power efficiency of their products in order to minimize the thermal load and/or maximize the performance of the power consumed per watt.

In some electronic devices, the input voltage source (for example, battery input, rectified mains power supply, intermediate DC power supply) can be converted to different voltages by various voltage conversion circuits. Switch-mode power supplies have become popular as voltage conversion circuits due to their high efficiency, and therefore are often used in various electronic devices.

Switching power supplies use switching devices to convert voltages. The switching devices are turned on with a very low resistance and turned off with a very high resistance. The switch-mode power supply can charge the output inductor for a period of time, and can release part or all of the inductor energy during a subsequent period of time. The output energy can be delivered to a set of output capacitors, which provide filtering to produce a DC output voltage. In a step-down switch-mode power supply, the steady-state output voltage can be approximated as the input voltage multiplied by the duty cycle, where the duty cycle is the on-time of the switch divided by the duration of the duty cycle. The total on-time and off-time of a switch cycle through the switch.

It can be seen that there are still many deficiencies in the above-mentioned conventional items, and they are not a good designer, and urgently need to be improved.

In view of this, the inventor of this case has been engaged in the manufacturing, development and design of related products for many years. Aiming at the above-mentioned goals, after detailed design and careful evaluation, he finally obtained a practical invention.

One purpose of the present invention is a three-quadrant bridge (TQB) applied to the output inductor of a step-down derivative power converter. The TQB operation in the first mode includes: when the high-side switch of the power converter is turned on, the TQB configuration is used to conduct the first controlled current in combination with the first output inductor current to conduct to the load; the TQB configuration is used to control the first Controlled current to minimize negative voltage transients on the load. TQB also has a second mode of operation including: when the high-side switch of the power converter is turned off, TQB is configured to shunt a second controlled current from the load and loop the second controlled current through the output inductor; The TQB configuration is used to control the second controlled current to minimize positive voltage transients on the output of the power converter.

According to the above objectives, various examples of the present invention can achieve one or more advantages. For example, certain TQB operations can improve power supply stability, especially during step transient loading events. In some cases, various TQB operations can provide improved performance with reduced output capacitance, thereby reducing cost and size. In some typical power converter applications, the generated output voltage may include a lower voltage deviation from the rated output voltage and may include a voltage deviation of less duration. Certain implementations may provide loads with higher undershoot or/and overshoot than the load requirements of modern computing devices.

In order to help your examiners understand the technical features, content and advantages of the present invention and its achievable effects, the present invention is described in detail with the accompanying drawings and in the form of embodiment expressions as follows. The drawings used therein are: The subject matter is only for the purpose of illustration and auxiliary description, and may not be the true proportions and precise configuration after the implementation of the invention. Therefore, it should not be interpreted in terms of the proportions and configuration relationships of the accompanying drawings, and should not limit the scope of rights of the invention in actual implementation. Hexian stated.

First, Figure 1 shows a typical switch-mode power supply circuit with a typical integrated three-quadrant bridge. The switch mode power supply circuit 100 includes a bypass switch 105. The bypass switch 105 is composed of field effect transistors (FETs) Q3 and Q4. A group of TQB drive lines 110 can control the bypass switch 105. The bypass drive circuit 115 drives the TQB drive line. The switch mode controller 120 can control the bypass driving circuit 115. The switch mode controller 120 can control the switch mode driving circuit 125. The switch mode driving circuit 125 drives the high-side FET Q1 and the low-side FET Q2. The high-side FET Q1 and low-side FET Q2 drive the output inductor L1. The output inductor L1 supports the output capacitor C1 and the output load I _LOAD . The output capacitor C1 can represent the output capacitor combination. The switch mode controller 120 receives the current detection signals I _T , I _B and I _L.

I _B can be the bypass current flowing through the bypass switch. In some operations, the bypass current I _B may be positive, and is a support current that illustrates the transient boost of the negative output voltage. In other operations, the bypass current I _B can be negative, and as a loop current, it indicates that the current is transferred from the output voltage transient that has risen due to the excess current of the switch mode power supply.

The switch mode controller 120 also receives the voltage detection signal VIN (for example: input body voltage supply) and VOUT (for example: output voltage supply). In various instances, the switch mode controller 120 receives the voltage error signal VERR, which (for example) may reflect the difference between VOUT and the stable reference voltage. Referring to Figure 1, the switch mode controller 120 controls the output of PWM signals and BP1/BP2 signals (for example, signals transmitted to the drivers 125 and 115) according to the function of receiving current and voltage signals. Drivers 125 and 115 respond to the reception of relevant PWM signals and BP1/BP2 signals to generate relevant output gate control signals DRV-H/DRV-L and DRV-BP1/DRV-BP2. In various examples, the driver 115 can be integrated/packaged with the bypass switch 105 so that the two form a single package integrated circuit device. In some examples, the driver may be a separate component from the bypass switch 105, causing the two to become discrete components of the circuit 100.

During a step transient or a load event on I _LOAD , when the high-side FET switch Q1 is turned on (for example: "boost mode"), the bypass switch 105 can be controlled via the TQB control line 110 to reduce the additional current I _B (I _B > 0 at this time) is drawn from VIN, and I _B is connected in parallel with the output inductor L1. The additional current I _B can advantageously support the output voltage supply VOUT, thereby greatly reducing the negative voltage transient (undershoot) on the output voltage supply VOUT. For example, during the boost mode, the switch mode controller 120 may set Q1, Q3, and Q4 to the on state, thereby allowing both currents I _B and I _L to provide power at VOUT.

Conversely, during a step-down transient or an unloading event on I _LOAD , when the FET switch Q1 is turned off (for example: "sag mode"), the bypass switch 105 can be controlled via the TQB control line 110 to output the inductor Part of the inverter current I _L is redirected out through the bypass switch 105 instead of through the load I _LOAD . The bypass current I _B (at this time I _B > 0) can be advantageously transferred out of the load and output voltage supply VOUT, thereby greatly reducing the positive voltage transient on the output voltage supply VOUT. For example, during the sinking mode, the switch mode controller 120 can set Q2 and Q1 to a high impedance (off) state (or Q2 is in an on/on state), thereby passing the current I _L through the bypass switch 105 to illustrate The current I _{B is} transferred out of the load.

In some examples, there can be at least two options in the settlement mode. In the first option, Q2 is on, and Q3 and Q4 are also on. In this case, part of the energy is dissipated in the bypass branch, and part of the current flows back to ground through the low-side FET Q2. In this case, the voltage on the inductor may be approximately VOUT. In the second option, both Q1 and Q2 are disconnected (for example: high impedance mode), so that the inductor current I _L can circulate inside the loop formed by Q3, Q4 and L1, with at least part of the energy (depending on Q3 and Q4's on-resistance) dissipates, and the rest eventually enters the load. In this second option, there will not be any (or negligible amount) of current flowing back to the power supply or ground via Q1 or Q2.

In various examples, the value of the bypass current I _B can be controlled by the gate-to-source voltage VGS of FETs Q3 and Q4. Various methods can be applied to control VGS. For example, referring to Fig. 6, a VGS control method suitable for controlling the current through FETs Q3 and Q4 can be explained.

In some completed examples, various methods can be applied to dynamically detect the bypass current I _B. The bypass current detection can be combined with the current detection method of a controller such as the switch mode controller 120 to determine (for example, by calculation) the current flowing through the output inductor L1 and/or FETs Q3 and Q4. The output inductor current _IL as a function of the input supply current minus the bypass current IB, once it is determined (for example), a false overcurrent protection (OCP) shutdown event can be initiated.

In various instances, Q3 and Q4 can be regarded as current sources. Various operating modes can use Q3 and Q4 in the linear operating region to make them function as current sources. For example, the switch mode controller 120 may perform a control operation to control the bypass circuit in the TQB converter. Various methods are disclosed here to adjust the phase current detection and reduce the end of the voltage transient after the transient event. Each example can be configured to provide the optimal current level to the load (for example: the current is not too high, but not too small).

In some instances, the controller may not receive I _B , I _L and/or I _T. For example, since I _T =I _B +I _L , if the integrated current detection method is adopted, I _T can be detected by the power stage and I _B can be detected by the bypass. In the discrete DC resistance current detection, I _L and I _B can be detected; thus, in some instances, I _L and I _B cannot be provided/input to the controller. In some instances, I _B and I _L / I _T can be input to the controller, depending on the current detection method.

In some examples, a low-side switch such as the low-side switch Q2 in Figure 1 can be used as, for example, a freewheeling rectifier. In some examples, by way of example and not limitation, the freewheeling rectifier may include synchronous rectifiers, Schottky diodes, high-speed rectifiers, ordinary rectifiers and/or bulk diodes inherent in various types of transistors (For example: FET).

Figure 2 shows a typical switch-mode power supply controller with integrated control of a three-quadrant bridge. The typical switch mode controller 120 includes a step-down adjustment control circuit 205. The step-down adjustment control circuit 205 receives the voltage detection signal VOUT from the output of the switch mode power supply 100 being controlled by the switch mode controller 120 (FIG. 1 ). The step-down adjustment control circuit 205 receives the voltage detection signal VIN from the large-capacity power supply (Figure 1). The step-down adjustment control circuit 205 receives the current detection signal I _T (Figure 1). The step-down adjustment control circuit 205 processes the voltage detection signals VOUT, VIN and the current detection signal I _T to generate a driving signal D. In the depicted example, the step-down adjustment control circuit 205 generates an internal reference voltage signal VREF. In some instances, the step-down adjustment control circuit 205 receives the reference voltage signal VREF from the outside, so that the user can determine the value of the output voltage supply VOUT. In the drawing examples of FIGS. 1 and 2, the value of the reference voltage signal VREF is predetermined and generated internally to the step-down adjustment control circuit 205.

The logic circuit 210 receives the driving signal D. The logic circuit 210 also receives the forward feed drive signal D-FF and the bypass switch compensation drive signal D-bypass. The logic circuit 210 combines the forward feed drive signal D-FF, the drive signal D and the bypass switch compensation drive signal D-BYPASS together to generate a PWM signal and provide it to the switch mode power supply circuit (for example: the switch mode in Figure 1 Power supply circuit 100) High-side and low-side FET switches (for example: FET switches Q1 and Q2 in Figure 1).

In some instances, the logic circuit 210 can combine all the signals (D, D-FF, and D-BYPASS) to generate the final duty cycle signal D_final to determine the PWM signal. In some typical examples, the final duty cycle signal D_final (with all adjustments) can enter the PWM generator of the driver 125, and the driver 125 in turn generates HS (Q1) and LS (Q2) gate control signals. In some instances, the complete set of drivers 125 and switches Q1 and Q2 can be collectively referred to as SMPS blocks. As an example and not a limitation, some examples can combine the duty cycle signal D_final in the logic 210, and the output of the logic 210 can be a PWM signal.

The forward feeding circuit 215 generates a forward feeding drive signal D-FF. The forward feed circuit 215 receives the voltage detection signal VIN from the large-capacity power supply. The forward feeding circuit 215 receives the reference voltage signal VREF generated by the step-down adjustment control circuit 205.

The bypass switch compensation controller 220 generates the bypass switch compensation driving signal D-BYPASS. The bypass switch compensation controller 220 receives the output voltage supply detection signal VOUT from the output of the switch mode power supply 100 being controlled by the switch mode controller 120. The bypass switch compensation controller 220 receives the PWM signal generated by the logic 210. In some examples, the bypass switch compensation controller 220 may receive the driving signal D instead of the PWM signal generated by the logic 210. The bypass switch compensation controller 220 receives the bypass current detection signal IB; this signal may indicate (for example) the bypass current I _B , as shown in FIG. 1. The bypass switch compensation controller 220 receives the current detection signal _IT (Figure 1); this signal can indicate the load demand of the fed load. The bypass switch compensation controller 220 receives the reference voltage signal VREF. The bypass switch compensation controller 220 processes the input signals (for example, the output voltage supply VOUT and bypass current I _B in the depicted example), and generates the bypass switch compensation drive signal D-BYPASS and a set of bypass signals BP1 and BP2. The bypass driver 115 generates the bypass drive signals DRV-BP1 and DRV-BP2. The bypass drive signals DRV-BP1 and DRV-BP2 can be the gate-to-source voltage drive signals (VGS) leading to the bypass switch, for example: the bypass switch 105 and the like on the gate of the FET Q3 and Q4 of the bypass switch VGS.

In various transient loading instances, a bypass switch such as the bypass switch 105 may be outside the control loop controlled by the step-down adjustment control circuit 205. The bypass switch compensation controller 220 can compensate the function of the bypass switch. For example, the bypass switch compensation controller 220 may include an endogenous determination of the gain factor Kg. In various instances, Kg as a function of bypass current I _B and pulse width modulation (PWM) can be determined. In various instances, the gain factor Kg can be a function of the gate-to-source voltage drive signal (VGS) and PWM; the VGS is applied to (for example) the gate-to-source FETs Q3 and Q4 of various bypass switches pole.

The PWM signal as a function of the bypass switch compensation drive signal D-BYPASS will shrink (for example: reduce the duty cycle) or expand (for example: increase the duty cycle). The amount of contraction or expansion may depend on the amount of additional charge applied to the load through the bypass switch 105. For example, if the bypass current I _{B is applied} to charge the output (for example: I _B > 0), it may be necessary to add the total duty cycle and extend the pulse after the bypass switch is opened. In another example, when the TQB is in the settling mode, it may be necessary to contract the periodic pulse after the bypass switch is opened. The gain factor (Kg>1 when contracting, Kg>1 when expanding) can be applied to duty cycle correction, where:

Kg = f (VGS, PWM)

In some instances, the bypass switch compensation controller 220 may generate the bypass switch compensation driving signal D-BYPASS based on a reference table or formula. Refer to the data table or formula/function to use the PWM signal to determine the mode (for example: refer to the support mode or transfer mode in Figure 3A and 3B). The value of bypass current I _B and/or the value of VGS can be used to determine the intensity of bypass current by referring to the data table or formula/function. Refer to the data table or formula/function to apply the output voltage supply VOUT to control the time interval of the bypass current I _B. In various instances, the gain factor Kg can be applied to correct the bypass switch to compensate the driving signal D-bypass.

Figure 3A shows the support mode switching waveforms of a switch-mode power supply circuit with a typical integrated three-quadrant bridge. In the support mode, referring to Figure 1 and Figure 3A, during the I _LOAD step transient load event, when the FET switch Q1 is turned on (for example: "boost mode"), the TQB control line 110 can be used Turn on the bypass switch 105, and when connected in parallel with the output inductor L1, the additional current I _B (in this case IB>0) is drawn from VIN through the bypass switch 105. The additional current I _B can advantageously support the output voltage supply VOUT, thereby greatly reducing the undershoot (negative) voltage transient thereon. The amount of current I _B through bypass switch 105 may depend on the gate-to-source voltage VGS applied to FETs Q3 and Q4. As depicted in Figure 3A, the current I _B combined with the inductor current I _L produces a total current I _T to the output load.

Figure 3B shows the transition mode switching waveform of a switch-mode power supply circuit with a typical integrated three-quadrant bridge. In the transfer mode, referring to Figure 1 and Figure 3B, during the step transient unloading event on I _LOAD , when the FET switch Q1 is off (for example: "sinking mode"), conduction can be initiated via the TQB control line 110 The bypass switch 105 redirects a part of the output inductor current I _L through the bypass switch 105 instead of the load I _LOAD . The bypass current I _B (at this time I _B > 0) can be advantageously transferred out of the load and the output voltage supply VOUT, thereby greatly reducing the positive voltage transient (overshoot) on the output voltage supply VOUT. The amount of current I _B through bypass switch 105 may depend on the gate-to-source voltage VGS applied to FETs Q3 and Q4. As depicted in Figure 3B, the current I _B is subtracted from the inductor current I _L to produce the total current I _T to the output load. In this case, the low-side Q2 may be on.

Figure 3C shows a typical transfer mode. In the typical scenario depicted in Figure 3C, Q1 and Q2 are in the off state (for example, in high impedance mode), and the inductor current I _L circulates inside the loop formed by Q3, Q4, and L1. In this case, the switch resistance will dissipate some energy or power, so the current level will drop. In this example, I _T may be substantially zero (for example, because I _L and I _B may be equal in reverse).

As shown in Figures 3A and 3B, the switch mode controller 120 can add/subtract the bypass current I _B detected in the bypass switch 105 from/to the current passing through the high-side switch FET Q1 and/or the low-side switch FET Q2 I _T. In various examples, the controller can estimate the bypass current I _B based on the VGS that the controller applies to FETs Q3 and Q4. The estimated amount of bypass current IB can be a function of the resistance of FETs Q3 and Q4 and the supply voltage VIN. For example, the bypass current I _B can be determined by looking up the data table or equation (alone or in combination) (for example: I _B =f (VGS)). In some examples, the FET resistance can be determined as a function of the applied VGS, or it can be determined by consulting a data sheet or equation (alone or in combination). In various instances, the bypass current I _B in the bypass switch 105 can be measured from the current mirror on one or both of the FETs Q3 and Q4.

Figure 4 is a set of typical waveforms illustrating the control applied through the three-quadrant bridge (TQB) current during a step transient loading event. A set of waveforms 400 includes (refer to Figure 1) the total power supply current I _T (t), capacitor current I _C (t) and output voltage supply VOUT (t) in the switch mode power supply circuit; this circuit can be a switch with integrated TQB The mode power supply circuit 100 (Figure 1) may also be the bypass switch 105 (Figure 1).

A step transient loading event can be a sudden large step increase in load current. Figure 4 shows the response of the switch-mode power supply to the step transient load, when the load step occurs at t ₀ .

As depicted by a set of typical waveforms 400, the controlled bypass switch 105 turns on the bypass current I _B (t) 405. The bypass current 405 is added to the inductor current I _L (t) to produce a total current I _T (t). The controlled bypass switch 105 turns on the bypass current 405, generating a controlled amount of bypass on-time T _B. The capacitor current I _C (t) waveform depicted, the capacitor C 1 (FIG. 1) receives at least the current bypass portion 415 405. As depicted in the output voltage supply VOUT(t) waveform, the output voltage responds to the negative capacitor current supplied to the step transient load and drops. Without the bypass switch 105, the output voltage supply VOUT drops (for example) △V1 _min . With the bypass switch 105, the output voltage supply VOUT drops (for example) ΔV2 _min . Correspondingly, adding the bypass current I _B (t) 405 to the total current I _T (t) can advantageously reduce the magnitude of the transient response 420.

ON the bypass can be adjusted controlled amount of time T _B, 420 to minimize the transient response. In some examples, the I _B size of the bypass current 405 can be controlled to minimize the transient response 420. The I _{B of the} bypass current 405 can be controlled by controlling the gate-to-source voltage VGS of the FET in TQB; for example, the FETs Q3 and Q4 in the bypass switch 105 as shown in Figure 1. The control of the bypass on-time T _B can be implemented separately, or can be combined with the control of the I _B size of the bypass current 405 to control the transient response 420. Two controlled parameters-the bypass turn-on time T _B and the size of I _B , can be a function of the size of the step transient load current, for example: I _LOAD (Figure 1). The two controlled parameters can be determined (for example, by the switch mode controller 120) through a function or by looking up a data table. In various instances, controlled parameters, such as fixed values, can be determined in advance.

Figure 5 is a set of typical waveforms illustrating the control applied through the three-quadrant bridge (TQB) current during a step-down transient unloading event. A set of waveforms 500 includes (refer to Figure 1) the total power supply current I _T (t), capacitor current I _C (t) and output voltage supply VOUT (t) in the switch mode power supply circuit; the circuit can be a switch with integrated TQB The mode power supply circuit 100 (Figure 1) may also be the bypass switch 105 (Figure 1).

A step-down transient unloading event can be a sudden large step drop in load current. Figure 5 shows the response of the switch-mode power supply to the step-down transient unloading, when the load step occurs at t ₀ .

As depicted by a set of typical waveforms 500, the controlled bypass switch 105 turns on the bypass current I _B (t) 505. The bypass current 505 is subtracted from the inductor current I _L (t) 510 to produce the total current I _T (t). The controlled bypass switch 105 turns on the bypass current 505, generating a controlled amount of bypass on-time T _B. The capacitor current I _C (t) waveform depicted, the capacitor C 1 (FIG. 1) receives at least the current bypass portion 505 515. As depicted in the output voltage supply VOUT(t) waveform, the output voltage rises in response to the excess capacitor current supplying step transient loads. Without the bypass switch 105, the output voltage supply VOUT increases (for example) ΔV1 _max . With the bypass switch 105, the output voltage supply VOUT rises (for example) ΔV2 _max . Correspondingly, adding the bypass current I _B (t) 505 to the total current I _T (t) can advantageously reduce the magnitude of the transient response 520.

Figure 6 shows a typical bypass switch VGS voltage control circuit. The VGS voltage control circuit 600 includes an error amplifier U 1. The error amplifier U 1 generates an error voltage V _ERR . The error voltage V _{ERR is derived} from the difference between the output voltage VOUT and the reference voltage signal VREF, both of which are coupled to the input of the error amplifier U 1. As a function of the error voltage V _ERR , VGS can be determined by a formula or a reference table. In some instances, the VGS as a power function can be determined by a formula or a look-up table, for example: f (V _ERR , I _T ).

In some instances, R1 and R2 can be removed from the circuit, and U1 can be understood by looking at the value of VOUT-VREF. In various instances, the circuit shown in FIG. 6 may be inside the controller 120, so there may be communication between the bypass switch controller and the driver. In some examples, the controller can determine the level of VGS by command, and the driver can create this level and apply it to the switch Q3/Q4.

Figure 7 shows a typical bypass switch on-time control circuit. The on-time control circuit of the bypass switch contains an error amplifier U 1. The error amplifier U 1 generates an error voltage V _ERR . The error voltage V _{ERR is derived} from the difference between the output voltage VOUT and the reference voltage signal VREF, both of which are coupled to the input of the error amplifier U 1. The error voltage V _{ERR is} coupled to the window comparator formed by the comparators U2 and U3 and the pull-up resistor R3.

When the error voltage V _{ERR is} lower than the predetermined V _ERR HI threshold and higher than the predetermined V _ERR LO threshold, the fixed VGS can be turned off via the switch/gate SW1. When the error voltage V _{ERR is} higher than the predetermined V _ERR HI threshold or lower than the predetermined V _ERR LO threshold, the fixed VGS can be turned on via the switch/gate SW1.

Various examples can control the on-time of the bypass switch by controlling the slope of the output voltage VOUT. For example, when the output voltage VOUT reaches a predetermined slope, the fixed VGS will turn on. In some instances, when the output voltage VOUT reaches the inflection point, the VGS signal can be turned off. In some instances, the on time may be a constant predetermined time.

Figure 8 shows a typical total bypass switch VGS voltage and on-time control circuit. The total bypass switch VGS voltage and on-time control circuit 800 includes an error amplifier U 1. The error amplifier U 1 generates an error voltage V _ERR . The error voltage V _{ERR is derived} from the difference between the output voltage VOUT and the reference voltage signal VREF, both of which are coupled to the input of the error amplifier U 1.

The error voltage V _ERR and the power supply current I _{T are} coupled to the input of the f() function block 805. The f() function block 805 generates output based on the function f (V _ERR , I _T ). The output of f() function block 805 is fed to the input of switch SW1. The output control switch SW1 of g() function block 810. The g() function block 810 generates output (for example) based on the function g (V _ERR , V _ERR HI, V _ERR LO). g() function block 810 receives inputs V _ERR , V _ERR HI and V _ERR LO. Correspondingly, the typical total bypass switch VGS voltage and on-time control circuit 800 can control the magnitude and on-time of the VGS voltage signal VGS(t) to each bypass switch.

Figure 9 shows a typical TQB support mode control method. For example, the TQB support mode method 900 can be used in the bypass switch compensation controller 220 (Figure 2). TQB support mode method 900 starts at process block 905. At process block 905, method 900 controls the output voltage VOUT. The output voltage VOUT can be the output of a switch-mode power supply, such as the switch-mode power supply circuit 100 (Figure 1). Continue to execute the decision block. At decision block 910, method 900 determines the initial negative transient on the output voltage supply VOUT. If there is no initial negative transient on the output voltage supply VOUT, the execution jumps back to block 905. If there is an initial negative transient on it, then decision block 915 continues. At decision block 915, the process determines the state of the high-side switch, such as the high-side switch Q 1 (Figure 1). If the high-side switch is not turned on, then execution jumps back to process block 905. If the high-side switch has been turned on, the process block 920 is continued, and the TQB support mode control method 900 starts to provide additional current through the bypass switch.

At process block 920, method 900 determines the amount of control of the bypass current through the bypass switch to alleviate negative transients on the output voltage supply VOUT. The determinant of the bypass current is related to the control voltage VGS that can be applied to the control gate of the FET in the bypass switch, for example: FETs Q 3 and Q 4 (Figure 1). Referring to Figures 6-8, as an example and not a limitation, various look-up tables, formulas, and/or formulas that are suitable for determining the number of bypass currents IB and related VGS applied to the control gate of the FET in the bypass switch Or function. Once the process block 920 is completed, the process block 925 continues to be executed.

At process block 925, method 900 applies a predetermined VGS from process block 920 to the control gate of the FET in the bypass switch to control the bypass current IB. Proceed to process block 930. At process block 930, method 900 controls the output voltage supply VOUT. The execution of decision block 935 continues.

At decision block 935, if the output voltage VOUT has reached the inflection point (for example), it will no longer fall, but will start to level out, ready to produce an initial positive voltage offset, and then proceed to process block 940. At process block 940, method 900 turns off the control voltage VGS to the bypass switch. This removal of the control voltage VGS at the bypass switch will terminate the supporting bypass current IB through the bypass switch. Then exit method 900.

If the output voltage VOUT at decision block 935 has not reached the inflection point, then decision block 945 will continue. At decision block 945, the process determines the state of the high-side switch. If the high-side switch is not turned on, execution jumps to process block 940 to turn off the bypass switch and exit method 900. If the high-side switch is turned on, then execution jumps back to process block 930. Correspondingly, the execution of blocks 930, 935, and 945 provide the method 900 with a wait function to wait for the identification to reach the upper inflection point of the output voltage VOUT or the high-side switch to turn off, so as to terminate the support mode by disconnecting the bypass current.

One point will be recognized, that is: at decision blocks 910 and 935, various other detection methods can be used. For example, referring to the description of FIGS. 6-8, when the output voltage VOUT falls below a predetermined threshold or a predetermined error voltage V _ERR threshold, the decision blocks 910 and 935 will produce a positive result.

In some instances, step 920 reflects VGS control. In some operating modes, steps 920 and 925 are optional or removed, which means that the bypass is turned on and VGS is fixed. Therefore, the method steps in one of the options may include turning on the bypass with a fixed VGS and directly entering step 930 (for example, skipping or removing steps 920 and 925).

Figure 10 shows a typical TQB transfer mode control method. The TQB transfer mode method 1000 can be used, for example: in the bypass switch compensation controller 220 (Figure 2). TQB transfer mode method 1000 starts at process block 1005. At process block 1005, method 1000 controls the output voltage supply VOUT. The output voltage supply VOUT can be the output of a switch-mode power supply, such as the switch-mode power supply 100 (Figure 1). The execution of decision block 1010 continues. At decision block 1010, method 1000 determines the initial positive transient on the output voltage VOUT. If there is no initial positive transient on the output voltage VOUT, the execution jumps back to process block 1005. If there is an initial positive transient on the output voltage VOUT, the decision block 1015 continues. At decision block 1015, the process determines the state of the high-side switch, for example: high-side switch Q 1 (Figure 1). If the high-side switch is not open, then execution jumps back to process block 1005. If the high-side switch has been disconnected, proceed to process block 1020, at this time the TQB transfer mode control method 1000 begins to transfer the current through the bypass switch to leave the power output.

At process block 1020, method 1000 determines the amount of bypass current control through the bypass switch to alleviate the positive transient on the output voltage VOUT. The determined amount of bypass current can be related to the control voltage VGS applied to the control gate of the FET in the bypass switch, for example: FET Q 3 and Q 4 (Figure 1). Referring to Figures 6-8, as an example and not a limitation, various reference tables, formulas and formulas that are suitable for determining the bypass current I _B applied to the control gate of the FET in the bypass switch and the related VGS quantity /Or function. Once the process block 1020 is completed, the process block 1025 continues to be executed.

At process block 1025, method 1000 applies a predetermined VGS from process block 1020 to the control gate of the FET in the bypass switch to control the bypass current I _B. Proceed to process block 1030. At process block 1030, method 1000 controls the output voltage VOUT. The execution of decision block 1035 continues.

At decision block 1035, if the output voltage VOUT has reached the inflection point (for example), it will no longer rise, but will start to level out, ready to generate an initial negative voltage offset, and then continue to execute process block 1040. At process block 1040, method 1000 turns off the control voltage VGS to the bypass switch. This removal of the control voltage VGS at the bypass switch will terminate the bypass current I _B flowing through the bypass switch. Then exit method 1000.

If the output voltage VOUT at decision block 1035 has not reached the inflection point, decision block 1045 will continue. At decision block 1045, the process determines the state of the high-side switch. If the high-side switch is not opened, execution jumps to process block 1040 to turn off the bypass switch and exit method 1000. If the high-side switch has been opened, then execution jumps back to process block 1030. Correspondingly, the execution of blocks 1030, 1035, and 1045 provide the method 1000 with a wait function to wait for the identification to reach the inflection point of the output voltage VOUT or the high-side switch to turn on, so as to terminate the transfer mode by disconnecting the bypass current.

One thing will be recognized, that is: at decision blocks 1010 and 1035, various other detection methods can be used. For example, referring to the description of FIGS. 6-8, when the output voltage VOUT rises above a predetermined threshold or a predetermined error voltage V _ERR threshold, the decision blocks 1010 and 1035 will produce positive results.

In some instances, step 1020 reflects VGS control. In some operating modes, steps 1020 and 1025 are optional or removed, which means that the bypass is turned on and VGS is fixed. Therefore, the method step in one of the options may include turning on the bypass with a fixed VGS and directly entering step 1030 (for example, skipping or removing steps 1020 and 1025).

Figure 11 is a block diagram of the bypass switch control system. The bypass switch control system 1100 can be used in various types of bypass switch compensation controllers, such as the bypass switch compensation controller 220 in Figure 2. The bypass switch control system 1100 includes a controller 1105. The controller 1105 is coupled to a random access memory (RAM) 1110 through a data/control bus during operation. RAM 1110 can facilitate the basic functions of controller 1105. The controller 1105 is coupled to a non-volatile random access memory (NVRAM) 1115 in operation. NVRAM 1115 contains program memory 1120. Program memory can provide controller 1105 pre-program design execution instructions.

The controller 1105 receives the PWM signal. Logic circuits can generate PWM signals, such as logic circuit 210 (Figure 2). The controller 1105 can use the PWM signal to identify the control signal to the bypass switch. For example, during a step transient loading event, the controller 1105 may only turn on the bypass switch when the PWM signal has been activated. Similarly, during a transient step-down unloading event, the controller 1105 can only turn on the bypass switch when the PWM signal cancels the start.

The controller 1105 receives the reference voltage signal VREF. The controller can use the reference voltage signal VREF to determine (for example) when the output voltage and/or error voltage are lower than a predetermined threshold. In some instances, the analog-to-digital converter ADC 1125 can read the reference voltage signal VREF. In the depicted example, the ADC 1125 samples the analog input signal and converts it into digital bits. The analog input signal sampled and converted by the ADC includes an output voltage VOUT that can indicate an output load current, a bypass current I _B, and a total current I _T.

The controller 1105 generates the bypass switch compensation driving signal D-BYPASS, which may be a duty cycle correction signal. The duty cycle correction signal can be combined with the forward feed correction signal and the step-down adjustment PWM output signal to alleviate the output voltage transient offset. The controller 1105 generates the TQB bypass signals BP1 and BP2 through the digital-to-analog converter DAC 1130. In some examples, the DAC 1130 may be implemented and/or integrated with the controller 1105. Correspondingly, the controller 1105 determines the TQB correction value according to the input VOUT, I _B , I _T and/or VREF, and writes a digital value into the DAC 1130 to control the TQB support or TQB transfer current. The controller 1105 generates the enable signal EN. The enable signal EN can turn on and off the bypass switch.

Although various examples have been explained with reference to the diagrams, other examples can be used. For example, an analog-to-digital converter ADC and/or a digital-to-analog converter DAC can be used to determine the bypass current I _B in the analog or digital domain. The various control methods of the step-down adjustment circuit with various TQBs can advantageously adopt forward feed control and adjustment, and can adopt current detection methods and overcurrent protection (OCP) or/and realize fast transient response.

Various examples can include the operation method of Buck-Derived Power Supplies (BDPS) with a three-quadrant bridge (TQB) configuration. The method of operation may include providing BDPS. The BDPS may include an input terminal configured to provide an input voltage source, an output terminal configured to drive a load, an inductor electrically coupled between the input terminal and the output terminal, electrically coupled between the input terminal and the output terminal and operating The input terminal can be selectively connected to the main switch of the intermediate switch node, the rectifier electrically coupled to the intermediate switch node, and the bypass switch electrically connected between the intermediate switch node and the output terminal and the inductor in parallel (for example).

The method may include providing a controller that controls the main switch and the bypass switch during operation, and is configured to provide a pulse width modulation (PWM) signal to control the main switch. The method may include causing the BDPS to enter a boost mode during a step transient loading event, which mode includes simultaneously activating the main switch and the bypass switch. The method may include: in response to exiting the boost mode when the load current is reduced, performing a duty cycle correction, which includes adjusting the duty cycle of the PWM signal applied to the main switch in the next cycle of the PWM signal after the load current is reduced . In some instances, the PWM signal duty cycle adjustment in response to exiting the boost mode includes: in the next cycle, increasing the duty cycle of the PWM signal applied to the main switch by a predetermined amount. In some instances, the PWM signal duty cycle adjustment in response to exiting the boost mode includes: in the next cycle, reducing the duty cycle of the PWM signal applied to the main switch by a predetermined amount. In various examples, the method includes combining the bypass current IB through the bypass switch with the inductor current IL through the inductor in the boost mode to support the output voltage VOUT at the output terminal.

In some examples, the bypass switch includes a first semiconductor switch (Q3) with a first control gate and a second semiconductor switch (Q4) with a second control gate, where the first and second semiconductor switches are reversed Connect in series. In some instances, the execution of the duty cycle correction includes applying a gain factor (Kg) to perform at least one of contraction and expansion of the PWM signal. In some instances, the method includes: according to a predetermined current characteristic of the bypass switch, by applying a gate-to-source voltage (VGS) to the bypass switch, adjusting the bypass current I through the bypass switch in a boost mode _B. The method may include: adjusting the bypass current I _B through the bypass switch in the boost mode by changing the on-time (T _B ) of the bypass switch. The method may include estimating the bypass current IB through the bypass switch as a function of the bypass switch gate-to-source voltage (VGS). The method may include: performing integrated current detection by applying a current mirror of the bypass switch, thereby detecting the bypass current I _B passing through the bypass switch.

In some examples, the method may include: during a step-down transient unloading event, causing the BDPS to enter a settling mode, which includes both activating the bypass switch and deactivating the main switch. The method may include exiting the settlement mode. The method may include: responding to the exit of the sinking mode when the load current increases, and adjusting the duty ratio of the PWM signal applied to the main switch in the next cycle of the PWM signal after the load current increases. In some instances, the duty cycle adjustment of the PWM signal in response to exiting the settling mode includes increasing the duty cycle of the PWM signal applied to the main switch by a predetermined amount in the next cycle. In some examples, the duty cycle adjustment of the PWM signal in response to exiting the sinking mode includes reducing the duty cycle of the PWM signal applied to the main switch by a predetermined amount in the next cycle. In various examples, the method includes: in the sinking mode, at least a portion of the inductor current _IL flows through the bypass switch.

Although a number of examples have been described, it can be realized that various modifications can be made. For example, beneficial results can be obtained in the following various situations: the steps of publishing the art are performed in a different order; the components of the publishing system are combined in different ways; the components are supplemented by other components. Therefore, consider other corresponding examples within the scope of the following requirements.

In summary, the three-quadrant bridge used in the step-down derivative switch mode power supply of the present invention does have an unprecedented innovative structure. It has not been seen in any publications, and there is no similar product on the market. , Its novelty should be considered. In addition, the unique features and functions of the present invention are far from comparable with conventional ones, so it is indeed more progressive than conventional ones, and it meets the requirements of the Chinese Patent Law concerning the requirements for application of invention patents, and a patent application is filed in accordance with the law.

However, the above-mentioned illustrations and descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. Those who are familiar with the art will do other things based on the characteristic scope of the present invention. Equivalent changes or modifications should be regarded as not departing from the design scope of the present invention.

100‧‧‧Switch mode power supply circuit 105‧‧‧Bypass switch 110‧‧‧TQB drive line 115‧‧‧Bypass drive circuit 120‧‧‧Switch Mode Controller 125‧‧‧Switch mode drive circuit 205‧‧‧Voltage adjustment control circuit 210‧‧‧Logic Circuit 215‧‧‧Forward feed circuit 220‧‧‧Bypass switch compensation controller 400‧‧‧A set of typical waveforms 405‧‧‧Bypass current Part of 415‧‧‧bypass current 405‧‧‧ 420‧‧‧Transient response 500‧‧‧A set of typical waveforms 505‧‧‧Bypass current 510‧‧‧Inductor current 515‧‧‧Part of bypass current 505‧‧‧ 600‧‧‧VGS voltage control circuit 800‧‧‧On-time control circuit 805‧‧‧f() function block 810‧‧‧g() function block 900‧‧‧TQB support mode method 905‧‧‧Process block 910‧‧‧Decision block 915‧‧‧Decision block 920‧‧‧Process block 925‧‧‧Process block 930‧‧‧Process block 935‧‧‧Decision block 940‧‧‧Process block 945‧‧‧Decision block 1000‧‧‧TQB transfer mode method 1005‧‧‧Process block 1010‧‧‧Decision block 1015‧‧‧Decision block 1020‧‧‧Process block 1025‧‧‧Process block 1030‧‧‧Process block 1035‧‧‧Decision block 1040‧‧‧Process block 1100‧‧‧Bypass switch control system 1105‧‧‧Controller 1110‧‧‧Random Access Memory (RAM) 1115‧‧‧Non-volatile random access memory (NVRAM) 1120‧‧‧Program memory 1125‧‧‧Digital Converter ADC 1130‧‧‧Converter DAC analog/digital converter 53

Figure 1 shows a typical switch-mode power supply circuit with a typical integrated three-quadrant bridge. Figure 2 shows a typical switch-mode power supply controller that provides integrated control of a three-quadrant bridge. Figure 3A shows the support mode switching waveforms of a switch-mode power supply circuit with a typical integrated three-quadrant bridge. Figure 3B shows the transition mode switching waveform of a switch-mode power supply circuit with a typical integrated three-quadrant bridge. Figure 3C shows a typical transfer mode. Figure 4 depicts a set of typical waveforms illustrating the control applied through the three-quadrant bridge (TQB) current during a step transient loading event. Figure 5 is a set of typical waveforms illustrating the control applied through the three-quadrant bridge (TQB) current during a step-down transient unloading event. Figure 6 shows a typical bypass switch VGS voltage control circuit. Figure 7 shows a typical bypass switch on the on-time control circuit. Figure 8 shows a typical total bypass switch VGS voltage and on-time control circuit. Figure 9 shows a typical TQB support mode control method. Figure 10 shows a typical TQB transfer mode control method. Figure 11 is a block diagram of the TQB control system.

100‧‧‧Switch mode power supply circuit

105‧‧‧Bypass switch

110‧‧‧TQB drive line

115‧‧‧Bypass drive circuit

120‧‧‧Switch Mode Controller

125‧‧‧Switch mode drive circuit

Claims (20)

A method for operating a Buck-Derived Power Supplies (BDPS) with a Three Quarter Bridge (TQB) configuration. The method includes: providing the BDPS, including: an input terminal for configuration To provide an input voltage source; an output terminal, configured to drive the load; an inductor, electrically coupled between an intermediate switch node and the output terminal; a main switch, electrically coupled between the input terminal and the intermediate switch node, operating When selectively connecting the input terminal to the intermediate switch node; a freewheeling rectifier electrically coupled to the intermediate switch node; and a bypass switch, electrically connected between the intermediate switch node and the output terminal, and in parallel with the inductor; providing a The controller, which controls the main switch and the bypass switch during operation, is configured to provide pulse width modulation (PWM) signals to control the main switch; during the boost transient load access period, the BDPS enters the boost mode, which includes Turn on the main switch and bypass switch at the same time; exit the boost mode; and exit the boost mode when the load current is reduced. The exit system performs duty cycle correction, including adjustment in the next cycle of the PWM signal after the load current is reduced The duty cycle of the PWM signal applied to the main switch. The method described in item 1 of the scope of patent application includes combining the bypass current (I _B ) through the bypass switch and the inductor current (I _L ) through the inductor in the boost mode to support The output voltage (VOUT) at the output terminal. According to the method described in item 1 of the scope of the patent application, the duty cycle correction system includes applying a gain factor (Kg) to perform at least one of contraction and expansion of the PWM signal. The method described in item 1 of the scope of patent application includes adjusting the voltage through the bypass switch in boost mode by applying a gate-to-source voltage (VGS) to the bypass switch in accordance with the predetermined current characteristics of the bypass switch. Bypass current (I _B ). The method described in item 1 of the scope of patent application includes adjusting the bypass current (I _B ) through the bypass switch in boost mode by changing the on-time (T _B ) of the bypass switch. The method described in item 1 of the scope of the patent application involves estimating the bypass current (I _B ) through the bypass switch as a function of the gate-to-source voltage (VGS) of the bypass switch. The method described in item 1 of the scope of the patent application includes performing integrated current detection by applying a current mirror of the bypass switch to detect the bypass current (I _B ) passing through the bypass switch. The method described in item 1 of the scope of patent application includes: during the step-down transient load disconnection period, the BDPS enters the sinking mode, which includes simultaneously starting the bypass switch and canceling the start of the main switch; exiting the sinking mode ; And in response to the exit of the sinking mode when the load current increases, the duty cycle of the PWM signal applied to the main switch is adjusted in the next cycle of the PWM signal after the load current increases. The method described in item 8 of the scope of patent application includes at least a part of the inductor current ( _IL ) flowing through the bypass switch in the sinking mode. For the method described in item 1 of the scope of the patent application, the controller includes a step-down adjustment control circuit configured to generate a driving signal (D), which is based on the input voltage source and the output voltage at the output terminal , And at least one of the total current ( _IT ) equal to the sum of the inductor current (I _L ) through the inductor and the bypass current (I _B ) through the bypass switch (I _T ) is generated. For the method described in item 10 of the scope of patent application, the controller includes a logic circuit, a forward feed circuit and a bypass switch compensation controller; the operation coupling generates a PWM signal to drive the main switch and the freewheeling rectifier, At least one of the bypass signals (BP1, BP2) is generated to drive the bypass switch. As the method described in item 11 of the scope of the patent application, the logic circuit in it: operates coupled to the forward feed circuit to receive the forward feed drive signal (D-FF), and the forward feed drive signal (D-FF) As a function of the input voltage source (VIN) and reference voltage (VREF); run coupled to the step-down adjustment control circuit to receive the drive signal (D); run coupled to the bypass switch compensation controller to receive the bypass switch compensation drive signal ( D-BYPASS); and configured to generate a PWM signal that is a function of at least one of the following signals: forward feed drive signal (D-FF), drive signal (D), and bypass switch compensation drive signal (D -BYPASS). The method described in item 12 of the scope of patent application, wherein: the bypass switch compensation controller operates to couple and receive the output voltage, the total current ( _IT ) and the bypass current ( _IB ) at the output terminal, and feed forward The circuit is coupled to receive the input voltage source. In the method described in item 13 of the scope of the patent application, the bypass switch compensation controller is operatively coupled to the logic circuit to receive the PWM signal from the logic circuit. For example, in the method described in item 14 of the scope of the patent application, the bypass switch compensation controller is configured to generate at least one of the bypass signals (BP1, BP2) in response to the PWM signal received from the logic circuit. As the method described in item 15 of the scope of patent application, the bypass switch includes a first semiconductor switch (Q3) with a first control gate and a second semiconductor switch (Q4) with a second control gate, And the first semiconductor switch and the second semiconductor switch are connected in anti-series; wherein, a bypass driver receives at least one of the bypass signals (BP1, BP2) to generate the first bypass drive signal (DRV-BP1) to drive the A control gate, a second bypass driving signal (DRV-BP2) to drive the second control gate. A control circuit for a three-quadrant bridge of a step-down derivative switch mode power supply. The step-down derivative switch mode power supply system includes: a high-end switch connected between an input terminal and an intermediate switch node, and an intermediate switch node connected to ground. An inductor and a bypass switch connected in parallel between the low-side switch and the intermediate switch node and the output terminal, wherein the control circuit includes: a logic circuit configured to generate a PWM signal to control the switch mode drive circuit, drive the high-side switch and Low-side switch; a bypass switch compensation controller, configured to generate a set of bypass drive signals to control the bypass drive circuit to drive the bypass switch, and the bypass switch compensation controller runs coupled to the logic circuit to receive from the logic circuit PWM signal; and a step-down adjustment control circuit configured to generate a drive signal (D) input to the logic circuit. The control circuit described in item 17 of the scope of patent application includes a forward feeding circuit configured to provide a forward feeding drive signal (D-FF) for the logic circuit. For the control circuit described in item 18 of the scope of patent application, the logic circuit is also configured to receive the bypass switch compensation drive signal (D-BYPASS) generated by the bypass switch compensation controller. For the control circuit described in item 17 of the scope of patent application, the bypass switch compensation controller is configured to receive: (1) an output voltage detection signal indicating the output voltage supply (VOUT) at the output terminal, and (2) the logic circuit generates The output signal of (3) indicates the bypass current detection signal (I _B ) flowing through the bypass switch, (4) the total current detection signal (IT) indicating the load demand of the fed load, and (5) the reference voltage signal (VREF).

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