TWI398935B - Wafer carrier board and package structure and method thereof - Google Patents

Description

Wafer carrier board and package structure and method thereof

The present invention relates to a wafer carrier and its package structure, and more particularly to a wafer carrier having a contact plug that prevents contamination of the package glue and a package structure thereof.

Referring to FIG. 1, a conventional wafer package structure 100 includes a wafer carrier 110, a wafer 120, and a package insulator 130. The wafer carrier 110 has lateral contact slots 112 and connection pads 114. The method of forming the package structure 100 includes bonding the wafer 120 over the wafer carrier 110; the wafer 120 is connected to the connection pad 114 by wire bonding to be electrically connected to the lateral contact slot 112; and then the wafer carrier 110 is placed. In the pre-prepared mold, an appropriate amount of resin glue is injected to cover the wafer 120; finally, the resin glue is solidified and demolded to form the package insulator 130. After the package structure 100 is completed, it can be cut along the broken line as shown in FIG. 1 to obtain individual package crystal grains. Each package die has a lateral contact slot 112 for easy insertion on a circuit board of an electronic product.

The conventional chip package structure 100 has the disadvantage of being easily contaminated by the resin glue used for packaging the insulator in the process. In detail, as in the forming step of the package structure 100 described above, when an appropriate amount of resin glue is applied to cover the wafer 120, the resin glue penetrates into the lateral contact slot 112, so that the final packaged die is completed. A problem of poor contact. The conventional method for solving this problem is to apply a protective film to cover the exposed surface of the contact slot 112 before the resin glue is injected. However, this solution will increase the complexity of the packaging process, so it is expected to be innovative and innovative, especially to facilitate the packaging process to solve the conventional problems.

In view of the above problems, the present invention provides a structure which can prevent a resin glue from contaminating a contact line which has been formed, and a method of manufacturing the same.

In one aspect, the present invention provides a wafer carrier comprising: a wafer carrying portion vertically disposed with a first contact structure and a second contact structure; and a bracket portion laterally surrounding the wafer carrying portion; Opening the wafer carrying portion and the bracket portion; and a shielding layer extending laterally across the space to connect the wafer carrying portion and the bracket portion. A method of forming the wafer carrier is also provided.

In another aspect, the invention provides a package structure comprising a wafer carrier as described above; a wafer disposed on the first contact structure; and a package insulator covering the wafer. A method of forming this package structure is also provided.

The present invention is intended to cover other aspects and the various aspects described above are disclosed in detail in the following embodiments.

Preferred embodiments of the present invention will be exemplified below with reference to the accompanying drawings. Like components in the drawings have the same component symbols. It should be noted that the various elements of the present invention are not drawn to the true aspect of the present invention, and in order to avoid obscuring the present invention, the following description also omits the known components, related materials, and related processing techniques.

2A to 2D and 3 to 5 are schematic cross-sectional views and a top view showing a process of fabricating a wafer carrier according to an embodiment of the invention.

First, referring to FIG. 2A, a wafer carrier 700 (see FIG. 5) is first provided with a multilayer wiring board 200, an upper bonding film 300, a lower bonding film 400, an upper shielding substrate 500, and a lower protective substrate 600. 2B shows a top view of the multilayer wiring board 200 of FIG. 2A. Figure 2C shows a top view of the top bonded film 300 of Figure 2A. Figure 2D shows a top view of the underlying bonded film 400 of Figure 2A.

The multilayer circuit board referred to herein includes at least two layers of wire lines. As shown in FIG. 2A, viewed from the Y direction, the multilayer wiring board 200 includes four wiring lines 201 to 204 with insulating layers 205 to 207 interposed therebetween. The uppermost wire line 201 and the lowermost wire line 204 are selectively covered with wire covering layers 208 and 209. A solder mask layer 210 may be selectively covered under the wire cover layer 209. Viewed from the X direction, the multilayer wiring board 200 may include a bracket portion 220, a wafer carrying portion 240, and an outer edge portion 230. The bracket portion 220 surrounds the wafer carrying portion 240 laterally inwardly; the outer edge portion 230 is connected to the outside. The outer edge portion 230 is typically a waste side. A hollow space 250 is provided between the bracket portion 220 and the wafer carrier portion 240. The wafer carrier 240 includes a sidewall contact receptacle 241 exposed to the spacer 250; and a conductive via 242 disposed therein. The side wall contact socket 241 surrounds the periphery of the wafer carrying portion 240 like a castle. The side wall contact socket 241 is for interposing on a circuit board of an electronic product. The production of the multilayer circuit board 200 can be conventionally known as printed circuit board technology, and the conductive and insulating materials used can be referred to various suitable materials. For example, the conductive material may be copper aluminum nickel or the like, the insulating material may be an epoxy resin glass fiber (FR4) substrate, etc.; the solder resist layer may be a commonly used polymer base solder resist green paint. The wire lines 201 to 204, the patterned solder resist layer and the like can be developed by photoresist etching; the fabrication interval 250, the sidewall contact socket 241 and the conductive through hole 242 can be generally drilled or laser drilled and perforated copper plating technology. Etching techniques can also be used. 2B is a top view of the multilayer wiring board 200 shown in FIG. 2A. The multilayer wiring board 200 shown in Fig. 2A is a cross-sectional view taken along the broken line B-B' of Fig. 2B. As is clear from FIG. 2B, the bracket portion 220 surrounds the wafer carrier 240 in a mesh structure, and the space 250 is interposed between the bracket portion 220 and the wafer carrier portion 240. The outer edge portion 230 is located at the outermost periphery of the multilayer wiring board 200. In particular, it should be noted that the multilayer circuit board 200 has a plurality of wafer carriers 240 that can be used to receive a plurality of wafers. In another embodiment, the multilayer wiring board 200 may also have only one wafer carrier 240. The diagonal position of the wafer carrying portion 240 is provided with a connecting portion 260 for connecting to the bracket portion 220. 2B shows that the surface of the multilayer wiring board 200 is covered with a wire covering layer 208. In another embodiment, the wire cap layer 208 may also have a patterned structure on the wafer carrier 240 to expose the underlying insulating layer 205.

In the present embodiment, the upper bonding film 300 may be a general thermosetting resin sheet for connecting the surface of the multilayer wiring board 200 close to the uppermost wiring line 201 to the upper shielding substrate 500. In another embodiment, if the multilayer wiring board 200 is already viscous, the upper bonding film 300 may be omitted. As shown in FIG. 2A, the structure of the upper bonded film 300 in the X direction is substantially similar to that of the multilayer wiring board 200. In detail, the upper bonding film 300 also has a holder portion 320, a wafer carrying portion 340, and an outer edge portion 330. The upper bonding film 300 has a hollowed space 301 corresponding to the spacing 250 of the multilayer wiring board 200. Preferably, the spacing 301 is greater than the spacing 250 so that the upper bonding film 300 does not contaminate the sidewall contact receptacle 241 due to spillage during subsequent hot pressing stages. 2C is a top view of the overlying adhesive film 300 of FIG. 2A. The upper bonded film 300 of Fig. 2A is a cross-sectional view taken along the line C-C' of Fig. 2C. The layered bonded film 300 having a hollow space 301 can be formed by stamping.

In the present embodiment, the material of the lower bonding film 400 is like the upper bonding film 300, which is a general thermosetting resin sheet. The lower bonding film 400 is used to connect the surface of the multilayer wiring board 200 close to the lowermost wiring line 204 to the lower protective substrate 600. The lower protective substrate 600 is a sacrificial layer, which is removed at the end of the process of the embodiment. Therefore, the lower bonding film 400 only needs to achieve the effect of temporarily bonding the lower protective substrate 600 to the multilayer wiring board 200. As shown in FIG. 2A, the lower bonded film 400 has a hollowed space 401. In other words, the lower bonding film 400 has only the structure corresponding to the outer edge portion 230 of the multilayer wiring board 200, and the rest are hollow spaces 401. Figure 2D is a top plan view of the underlying bonded film 400 of Figure 2A. The lower layer bonded film 400 of Fig. 2A is a cross-sectional view taken along the dotted line D-D' of Fig. 2D. The adhesive film 400 having a void interval 401 can be formed by stamping.

In the present embodiment, the upper shielding substrate 500 has at least two uses, one for forming an outer layer to form a wafer contact structure, and the other for forming a mask for preventing the subsequent sealing of the resin glue into the sidewall contact socket 241. Or other various lines that have been completed on the multilayer circuit board 200. As shown in FIG. 2A, the upper shielding substrate 500 may include an insulating shielding layer 501 and an outer conductor layer 502. In this embodiment, a copper foil epoxy fiberglass (FR4) substrate is used as the upper shielding substrate 500. However, the present invention is not limited thereto, and those skilled in the art can see that any material that can achieve the above-mentioned use of the invention can be used. .

In the present embodiment, the underlying protective substrate 600 has at least one use in that during the fabrication of the subsequent outer layer, the process syrup or other various impurities are prevented from contaminating the sidewalls from contacting the socket 241 or other various lines that have been completed on the multilayer wiring board 200. In this embodiment, a copper foil epoxy fiberglass (FR4) substrate is used as the lower layer protection substrate 600. However, the present invention is not limited thereto, and those skilled in the art can see that any material that can achieve the above-mentioned use of the invention is applicable. .

Referring next to Figure 3, a press-fit step is shown. The above layers, that is, the multilayer wiring board 200, the upper bonding film 300, the lower bonding film 400, the upper shielding substrate 500, and the lower protective substrate 600 are arranged in the order shown in the figure, and then pressed. Pressing can be carried out by a general hot press, and the temperature and pressure can be adjusted according to actual needs. In addition to the above layers, a thin layer such as other functions may be added as needed.

Referring next to Figure 4, for the outer conductor layer 502, the outer layer is fabricated using conventional printed circuit board technology to form a wafer contact structure. As shown in FIG. 4, it can be known that the hole copper plating technique forms a conductive via 505 through the insulating mask layer 501 to communicate with the underlying conductive via 242; a portion of the outer conductor layer 502 can be removed by etching to form a hollow The spacer 503; the wafer conductive contact 507 may be further formed on the outer conductor layer 502 and the outer solder resist layer 509 is coated. As with the spacing 250 described above, the spacing 503 can separate the portion of the outer conductor layer 502 that serves as a support from the wafer carrier. By spacing 503, the position of each of the outer layers of the wafer will be clearly revealed. When etching the outer conductor layer 502, care should be taken to control the process conditions so that the etching stops at the underlying insulating mask layer 501. In other words, the spacer 503 does not penetrate the insulating mask layer 501. As described above, since the underlying protective substrate 600 is provided, it is possible to prevent the process syrup or other various impurities from contaminating the sidewall contact socket 241 or other various lines previously completed on the multilayer wiring board 200 during the fabrication of the outer layer wiring.

After the outer layer is completed, the lower bonded film 400 and the lower protective substrate 600 can be removed by molding or stamping or other suitable means. FIG. 5 shows the wafer carrier 700 formed after the underlying protective substrate 600 is removed. As shown in FIG. 5, the wafer carrier 700 includes a wafer carrier 702; the carrier portion 701 laterally surrounds the wafer carrier 702; a spacer 710 for spacing the wafer carrier 702 from the carrier portion 701; and an outer edge portion 712 The bracket portion 701 surrounds the periphery of the wafer carrier 700 laterally. Wafer carrier 700 includes an upper wafer contact structure 704 and a lower circuit board contact structure 705. The insulating shielding layer 501 laterally connects the wafer carrying portion 702 and the bracket portion 701 across the interval 710. The insulating masking layer 501 extends laterally between the wafer contact structure 704 and the board contact structure 705 and laterally extends into the bracket portion 701 from another angle.

6 shows a package structure in which a wafer 801 is adhered to the wafer carrier 700 shown in FIG. 5 and an appropriate amount of resin glue is injected to cover the wafer 801 package insulator 802. It should be noted that the package insulator 801 may cover a portion of the insulating mask layer 501 that spans the gap 710. Individual packaged dies can be obtained by cutting along the dashed line as shown in FIG. It can be understood from FIG. 6 that the insulating mask layer 501 can be used to prevent the resin glue for encapsulation from penetrating into the underlying circuit board contact structure 705.

Figure 7 is a photograph (top view) of a wafer carrier 700' according to another embodiment of the present invention. As can be seen from Fig. 7, the wafer carrier 700' includes a plurality of holder portions 701', a plurality of wafer carrier portions 702', and a connecting portion 703' that connects the two. An insulating shielding layer 501' is interposed between the holder portion 701' and the wafer carrier portion 702' to prevent the resin glue liquid for subsequent encapsulation from penetrating into the underlying circuit board contact structure.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following. Within the scope of the patent application.

100. . . Chip package structure

110. . . Wafer carrier

112. . . Lateral contact slot

114. . . Connection pad

120. . . Wafer

130. . . Package insulator

200. . . Multi-layer circuit board

201,202,203,204. . . Wire line

205,206,207. . . Insulation

208,209. . . Wire cover

210. . . Solder mask

220. . . Bracket

230. . . Outer edge

240. . . Wafer carrier

241. . . Side wall contact socket

242. . . Conductive through hole

250. . . interval

260. . . Connection

300. . . Upper bonding film

320. . . Bracket

340. . . Wafer carrier

330. . . Outer edge

301. . . interval

400. . . Underlying bonding film

401. . . interval

500. . . Upper shielding substrate

501,501’. . . Insulating shielding layer

502. . . Outer conductor layer

505. . . Conductive through hole

503. . . interval

507. . . Wafer conductive contact

509. . . Outer solder mask

600. . . Lower protective substrate

700,700’. . . Wafer carrier

701,701’. . . Bracket

702,702’. . . Wafer carrier

703’. . . Connection

704. . . Wafer contact structure

705. . . Board contact structure

710. . . interval

712. . . Outer edge

801. . . Wafer

802. . . Package insulator

1 is a schematic cross-sectional view of a conventional package structure;

2A to 2D and 3 to 5 are schematic cross-sectional views and a top view showing a process of fabricating a wafer carrier according to an embodiment of the invention;

6 is a cross-sectional view showing a package structure fabricated in accordance with an embodiment of the present invention;

Figure 7 is a top plan view of a wafer carrier made in accordance with an embodiment of the present invention.

200‧‧‧Multilayer circuit board

250‧‧‧ interval

300‧‧‧Upper bonding film

501‧‧‧Insulation shielding layer

502‧‧‧ outer conductor layer

503‧‧‧ interval

700‧‧‧ wafer carrier

701‧‧‧ bracket

702‧‧‧ wafer carrier

704‧‧‧ wafer contact structure

705‧‧‧Board contact structure

710‧‧‧ interval

712‧‧‧The outer edge

Claims (14)

A wafer carrier comprising: a wafer carrying portion vertically provided with a first contact structure and a second contact structure; a bracket portion laterally surrounding the wafer carrying portion; a space separating the wafer carrying portion and the bracket And a shielding layer extending laterally across the spacing to join the wafer carrier and the bracket portion. The wafer carrier of claim 1, wherein the first contact structure is for electrically contacting a wafer, and the second contact structure is for electrically contacting a circuit board. The wafer carrier of claim 1 wherein the second contact structure further comprises a sidewall contact receptacle exposed to the spacer. The wafer carrier of claim 1, wherein the shielding layer extends laterally between the first contact structure and the second contact structure. The wafer carrier of claim 1 wherein the masking layer extends laterally into the bracket portion. A package structure comprising: the wafer carrier as claimed in claim 1; a wafer disposed on the first contact structure; and a package insulator covering the wafer. The package structure of claim 6, wherein the package insulation system covers a portion of the shielding layer that spans the space. A method for forming a wafer carrier, comprising: providing a multilayer circuit board, an upper shielding substrate and a lower protection substrate, the multilayer circuit board comprising a wafer carrying portion, a bracket portion surrounding the wafer carrying portion and a spacing between Between the wafer carrying portion and the bracket portion; performing a pressing step to join the multilayer circuit board, the upper layer shielding substrate and the lower layer protection substrate, the multilayer circuit board being interposed between the upper shielding substrate and the lower protective substrate The upper shielding substrate spans the space; and a second contact structure is formed over the wafer carrier. The method of forming a wafer carrier according to claim 8, further comprising removing the underlying protective substrate after the second contact structure is formed. The method for forming a wafer carrier according to claim 8, further comprising placing an upper bonding film between the multilayer wiring board and the upper shielding substrate before the pressing step. The method for forming a wafer carrier according to claim 8, further comprising placing a layer of adhesive film between the multilayer wiring board and the lower protective substrate before the pressing step. The method of forming a wafer carrier according to claim 8, wherein the upper shielding substrate comprises a shielding layer and an outer conductor layer, and the outer conductor layer is used to form the second contact structure. A method of forming a package structure, comprising: providing a wafer carrier as claimed in claim 1; and disposing a wafer on the first contact structure; and forming a package insulator to cover the wafer. The package structure of claim 13, wherein the package insulation system covers a portion of the shielding layer that spans the space.