TWI396063B - A low dropout regulator without esr compensation - Google Patents

Description

Low-dropout linear regulator without ESR resistor compensation

The present invention relates to a linear regulator, and more particularly to a low dropout linear regulator without ESR resistance compensation characteristics.

A conventional linear regulator 40, as disclosed in U.S. Patent No. 7,038,431, which is incorporated herein by reference to FIG. 8, which includes a reference voltage source 41, an amplifier network 42, a load 43, a bypass circuit 44, and a zero point. The compensation circuit 45, wherein the amplifier network 42 is electrically connected to the reference voltage source 41, the load 43, the bypass circuit 44 and the zero compensation circuit 45 are electrically connected to the amplifier network 42, the linear regulator The 40 series can generate a transfer function that converts the reference voltage of the reference voltage source 41 into a stable voltage and supplies it to the load 43, which is used to provide a zero point to compensate for the transfer function. Due to the change of the load current, the conventional linear regulator 40 can only perform frequency compensation for a fixed load. If the load is different, the main pole will be changed. Therefore, the zero compensation circuit 45 and the bypass circuit 44 The equivalent series resistance (ESR) 441 cannot perform frequency compensation actions in response to different loads.

The main purpose of the present invention is to provide a low-dropout linear regulator without ESR resistance compensation, which comprises a signal input terminal, a high precision reference voltage source, an error amplifier, a source follower, and a zero tracking compensation. a signal, a power transmission component, a compensation/divider circuit, and a signal output terminal, wherein the signal input terminal is configured to provide a voltage input signal, and the high precision reference voltage source is electrically connected to the signal input end, the error The amplifier is electrically connected to the high-precision reference voltage source, and the source follower and the zero tracking compensation circuit are electrically connected to the error amplifier, and the power transmission component is electrically connected to the source follower, the compensation/ The voltage dividing circuit and the signal output end are electrically connected to the power transmission component, and the signal output terminal can output a stable voltage output signal. The invention is based on the compensation effect of the zero-point tracking compensation circuit. When the signal output end of the low-dropout linear regulator is electrically connected to a load, the main pole of the circuit will vary due to the load, and the zero-point tracking compensation circuit is The corresponding zero point position can be generated according to different main poles, so the effect of phase margin compensation can be effectively achieved. In addition, the circuit design of the present invention eliminates the need for external equivalent series resistance (ESR) to make the system different. A stable voltage output signal can still be provided under load.

Referring to FIG. 2, which is a preferred embodiment of the present invention, a low-dropout linear regulator 10 without ESR resistance compensation includes a signal input terminal 11, a high-precision reference voltage source 12, and an error amplifier 13. a source follower 14 , a zero tracking compensation circuit 15 , a power transmission component 16 , a compensation / voltage divider circuit 17 and a signal output terminal 18 , the signal input terminal 11 is used to provide a voltage input The high-precision reference voltage source 12 is electrically connected to the signal input terminal 11. The error amplifier 13 is electrically connected to the high-precision reference voltage source 12, and the source follower 14 and the zero tracking compensation circuit 15 are connected. Electrically connected to the error amplifier 13 , the power transmission component 16 is electrically connected to the source follower 14 , and the compensation/divider circuit 17 and the signal output 18 are electrically connected to the power transmission component 16 . The signal output terminal 18 can output a stable voltage output signal.

Please refer to FIG. 1 , which is a circuit block diagram of an electronic device, which is composed of a power source 20 , the low-dropout linear regulator 10 and a load 30. In this embodiment, the power source 20 can be a A battery or rechargeable battery with a voltage range of 3.45 to 5.0V. The voltage signal provided by the power supply is an unstable voltage signal. After the unstable signal is passed through the low voltage drop linear regulator 10, Effective conversion to a stable voltage signal to account for different load variations is the primary function of the low dropout linear regulator 10.

Referring to FIG. 1 and FIG. 2 again, the signal receiving end 11 receives the voltage input signal provided by the power source 20 and sends the voltage input signal to the high precision reference voltage source 12, see FIG. 3, the high precision reference voltage. The source 12 is composed of a reference voltage unit 121, an error amplifier 122, and a first PMOS transistor 123. The error amplifier 122 and the first PMOS transistor 123 are electrically connected to the reference voltage unit 121. The unit 121 adjusts the reference voltage of a reference signal terminal 1211 by changing the ratio between the resistors, and the reference voltage is not affected by temperature and process drift. The first PMOS transistor 123 can be used as a startup circuit (Start). -UP) to prevent the voltage of the reference cell transistor 121 in the case where no current flows, the addition, the error amplifier 122 based correction using negative feedback mechanism such that it is electrically connected to both ends of the cell 121 to the reference voltage V _x of the point , V _y voltage values are equal, so that the reference voltage source 12 may provide a more accurate the reference voltage, Referring again to FIG. 2, the reference voltage and the compensation / dividing circuit 17 generates the feedback voltage delivered to the system In the present embodiment, the error amplifier 13 has a positive terminal 131, a negative terminal 132 and an output terminal 133. The negative terminal 132 is electrically connected to the reference signal of the high precision reference voltage source 12. The terminal 1211 is electrically connected to the compensation/divider circuit 17, and the output terminal 133 is electrically connected to the source follower 14 and the zero tracking compensation circuit 15. Referring to FIG. 4, The error amplifier 13 further has a bias generating circuit 134, a PMOS differential pair 135 electrically connected to the bias generating circuit 134, and an operational amplifier 136 electrically connected to the PMOS differential pair 135. The positive terminal 131 and The negative terminal 132 is electrically connected to the PMOS differential pair 135. The output terminal 133 is electrically connected to the operational amplifier 136. In this embodiment, the operational amplifier 136 is composed of a plurality of NMOS transistors and a plurality of PMOS electrodes. a crystal composition, the reference voltage and the feedback voltage are subtracted and amplified by the error amplifier 13 to generate a voltage amplification signal, please refer to FIG. 2, the voltage amplification signal is sent to the source follower 14 to provide a voltage To the power transmission component 16, as shown in FIG. 5, the source follower 14 has a second PMOS transistor 141 and a third PMOS transistor 142 electrically connected to the second PMOS transistor 141. The source terminal 1411 of the second PMOS transistor 141 is electrically connected to the signal input terminal 11. The gate terminal 1421 of the third PMOS transistor is electrically connected to the error amplifier 13. The second terminal of the second PMOS transistor 141 is electrically connected. 1412 and the source terminal 1422 of the third PMOS transistor 142 are electrically connected to the power transmission component 16. In the embodiment, the power transmission component 16 is a large-sized (80000/0.35um) PMOS transistor. The source follower 14 is configured to control the turn-on voltage of the source and drain terminals of the power transfer component 16 such that the power transfer component 16 can generate a stable voltage output signal, and the voltage output signal can be sent to the The voltage output 18 is provided for use by the load 30.

Referring to FIG. 2, the compensation/divider circuit 17 is composed of a second capacitor 171, a first resistor 172 electrically connected to the second capacitor 171, and an electrical connection between the second capacitor 171 and the first a second resistor 173 of the resistor 172, the second capacitor 171, the first resistor 172 and the second resistor 173 are electrically connected to the positive terminal 131 of the error amplifier 13, the first resistor 172 and the first resistor The other end of the second capacitor 171 is electrically connected to the signal output terminal 18, wherein the first resistor 172 and the second capacitor 171 can generate a zero point and a pole point, and the pole position is located at the zero point (1+R1) In addition, the second capacitor 171 has a function of rapidly coupling the voltage output signal of the signal output terminal 18, so that the circuit noise of the system can be effectively suppressed. Please refer to FIG. 2 again, in this embodiment. In order to stabilize the system, it is necessary to maintain a sufficient phase margin. Therefore, the present invention uses two methods to compensate the phase boundary, one of which is to use the zero tracking compensation circuit 15, which is used to track the compensation circuit 15 Has a variable zero position The zero-point tracking compensation circuit 15 has a fourth PMOS transistor 151 and a first capacitor 152 electrically connected to the fourth PMOS transistor 151. The fourth PMOS transistor and the first capacitor 152 are electrically connected. The fourth PMOS transistor 151 is connected to the linear region. In the embodiment, the fourth PMOS transistor 151 is used as a variable resistor, and the resistance is associated with the fourth PMOS. The voltage of the transistor 151 is changed by the change of the voltage amplification signal received by the gate of the transistor 151. Since the load 30 is connected to the positive terminal 131 of the error amplifier 13 by the compensation/divider circuit 17, the zero tracking compensation is performed. The circuit 15 can generate a zero corresponding to the current change of the load 30, which can effectively avoid the situation that the phase boundary is insufficient due to the sudden change of the load current of the load 30. Please refer to FIG. 2, the low pressure drop is linearly stable. The voltage device 10 further has a frequency compensation circuit 19, and another method of phase boundary compensation is to use the frequency compensation circuit 19, and the terminal end of the frequency compensation circuit 19 is electrically connected to the output end 133 of the error amplifier 13. frequency The other end of line 19 of the compensation circuit is electrically connected to the signal output terminal 18, in the present embodiment, the frequency compensation circuit 19 may be by a capacitor which produces a low frequency zero line to compensate for the phase boundary.

Please refer to FIG. 6 and FIG. 7 , which are the actual measurement results of the present invention. As can be seen from FIG. 6 , when the voltage input signal of the signal input terminal 11 has a voltage value of 3.45 to 5 volts, the signal output terminal 18 The voltage output signal is still stable at 3.3 volts, and its linear regulation can reach 0.012% through measurement. It can be seen from Fig. 7 that when the load current changes (clock in the figure), the signal output The voltage output signal of 18 has almost no change, and its load regulation rate can reach 0.005% through measurement, which has extremely high system stability.

According to the present invention, the zero tracking correction circuit 15 can generate a zero corresponding to the current change of the load 30, thereby effectively avoiding a situation in which the phase boundary is insufficient due to a sudden change of the load current of the load 30. The circuit design of the invention does not require equivalent series resistance (ESR) to enable the system to provide a stable voltage output signal under different loads.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

10‧‧‧Low-Dropout Linear Regulator

11‧‧‧Voltage input

12‧‧‧High precision reference voltage source

121‧‧‧reference voltage unit

1211‧‧‧Reference signal end

122‧‧‧Error amplifier

123‧‧‧First PMOS transistor

13‧‧‧Error amplifier

131‧‧‧ positive end

132‧‧‧Negative end

133‧‧‧output

134‧‧‧ bias generation circuit

135‧‧‧ PMOS differential pair

136‧‧‧Operational Amplifier

14‧‧‧Source follower

141‧‧‧Second PMOS transistor

1411‧‧‧ source extreme

1412‧‧‧汲 Extreme

142‧‧‧ Third PMOS transistor

1421‧‧ ‧ extreme

1422‧‧‧ source extreme

15‧‧‧Zero tracking compensation circuit

151‧‧‧ Fourth PMOS transistor

152‧‧‧first capacitor

16‧‧‧Power transmission components

17‧‧‧ Frequency compensation and voltage divider circuit

171‧‧‧second capacitor

172‧‧‧First resistance

173‧‧‧second resistance

18‧‧‧Signal output

19‧‧‧ Frequency compensation circuit

20‧‧‧Power supply

30‧‧‧load

40‧‧‧Linear regulator

41‧‧‧reference voltage source

12‧‧‧Amplifier Network

43‧‧‧ load

44‧‧‧Bypass circuit

441‧‧‧ equivalent series resistance

45‧‧‧zero compensation circuit

Figure 1 is a block diagram of a circuit of a low dropout linear regulator without ESR resistor compensation in accordance with a first preferred embodiment of the present invention.
Figure 2 is a circuit diagram of the low dropout linear regulator without ESR resistance compensation in accordance with a first preferred embodiment of the present invention.
Figure 3 is a circuit diagram of a high precision reference voltage source for a drop-down linear regulator without ESR resistance compensation in accordance with a first preferred embodiment of the present invention.
Figure 4 is a circuit diagram of an error amplifier of the ESR-free resistor-compensated falling linear regulator in accordance with a first preferred embodiment of the present invention.
Figure 5 is a circuit diagram of a source follower of the ESR-free resistor-compensated falling linear regulator in accordance with a first preferred embodiment of the present invention.
Figure 6 is a diagram showing an input voltage signal/output voltage signal waveform of the reduced-linear regulator without ESR resistance compensation according to the first preferred embodiment of the present invention.
Figure 7 is a diagram showing the load current/output voltage signal waveform of the reduced-linear regulator without ESR resistance compensation according to the first preferred embodiment of the present invention.
Figure 8: Circuit diagram of a conventional low-dropout linear regulator.

10‧‧‧Low-Dropout Linear Regulator

11‧‧‧Signal input

12‧‧‧High precision reference voltage source

13‧‧‧Error amplifier

131‧‧‧ positive end

132‧‧‧Negative end

133‧‧‧output

14‧‧‧Source follower

15‧‧‧Zero tracking compensation circuit

151‧‧‧ Fourth PMOS transistor

152‧‧‧first capacitor

16‧‧‧Power transmission components

17‧‧‧Compensation/divider circuit

171‧‧‧second capacitor

172‧‧‧First resistance

173‧‧‧second resistance

18‧‧‧Signal output

19‧‧‧ Frequency compensation circuit

30‧‧‧load

Claims (10)

A low dropout linear regulator without ESR resistor compensation, comprising:
a signal input terminal for providing an input voltage signal;
a high-precision reference voltage source electrically connected to the signal input end;
An error amplifier electrically connected to the high precision reference voltage source;
a source follower, which is electrically connected to the error amplifier;
a zero point tracking compensation circuit electrically connected to the error amplifier;
a power transmission component electrically connected to the source follower;
a compensation/divider circuit electrically connected to the power transmission component; and a signal output terminal electrically connected to the power transmission component and capable of outputting a stable output voltage signal. The low-dropout linear regulator without ESR resistance compensation according to the first aspect of the patent, wherein the high-precision reference voltage source is composed of a reference voltage unit, an error amplifier and a first PMOS transistor. The error amplifier and the first PMOS transistor system are electrically connected to the reference voltage unit. The low-dropout linear regulator without ESR resistance compensation according to the first aspect of the patent, wherein the error amplifier has a positive terminal, a negative terminal and an output terminal, and the negative terminal is electrically connected to the high precision reference. The voltage source is electrically connected to the compensation/divider circuit, and the output is electrically connected to the source follower and the zero tracking compensation circuit. The low-dropout linear regulator without ESR resistance compensation according to the third aspect of the patent, wherein the error amplifier further has a bias generating circuit, a PMOS differential pair electrically connected to the bias generating circuit, and An operational amplifier is electrically connected to the PMOS differential pair, and the positive terminal and the negative terminal are electrically connected to the PMOS differential pair, and the output terminal is electrically connected to the operational amplifier. The low-dropout linear regulator without ESR resistance compensation according to the first aspect of the patent, wherein the power transmission component can be a PMOS transistor. The low-dropout linear regulator without ESR resistance compensation according to the first aspect of the invention, wherein the source follower has a second PMOS transistor and a second electrically connected to the second PMOS transistor a PMOS transistor, wherein a source terminal of the second PMOS transistor is electrically connected to the signal input end, and a gate terminal of the third PMOS transistor is electrically connected to the error amplifier, and a second PMOS transistor is connected to the terminal And a source terminal of the third PMOS transistor is electrically connected to the power transmission element. The low-dropout linear regulator without ESR resistance compensation according to the first aspect of the invention, wherein the zero tracking compensation circuit has a fourth PMOS transistor and a first electrically connected to the fourth PMOS transistor The capacitor, the fourth PMOS transistor and the first capacitor are electrically connected to the error amplifier. The low-dropout linear regulator without ESR resistance compensation according to the third aspect of the patent, wherein the compensation/divider circuit has a second capacitor, a first resistor electrically connected to the second capacitor, and Electrically connecting the second capacitor and the second resistor of the first resistor, the second capacitor, the first resistor and the second resistor are electrically connected to the positive terminal of the error amplifier, the first The other end of the resistor and the second capacitor are electrically connected to the signal output end. The low-dropout linear regulator without ESR resistance compensation according to claim 3, further comprising a frequency compensation circuit, wherein the frequency end of the frequency compensation circuit is electrically connected to the output end of the error amplifier, the frequency The other end of the compensation circuit is electrically connected to the signal output end. The low-dropout linear regulator without ESR resistance compensation according to the ninth aspect of the patent, wherein the frequency compensation circuit can be a capacitor.