201205226 六、發明說明： 【發明所屬之技術領城】 [0001 ] 本發明係有關於一種線性穩壓器，特別係有關於— 種無ESR電阻補償特性之低壓降線性穩壓器° 【先前控:術】 [0002] 習知線性穩壓器40，如美國專利第7038431號所揭 示，請參閱第8圖，其係包含一參考電壓源41、一放大器 網路42、一負載43、一旁通電路44及一零點補償電路45 ’其中該放大器網路42係電性連操該參考電壓源41，該 負載43、該旁通零路44及該零點補償電路45係電性連接 該放大器網路42，該線性穩壓器40係可產生一轉移函數 ，此轉移函數可將該參考電壓源41之參考電壓轉換為— =疋電壓並輸送至該負載43 ’該零點補償電路45係用以 提供-零點’以補償轉移函數因負栽電流變動所產生之 變化，惟習知線性穩壓㈣僅料_定負載進行頻率 =严若負載不同時將導致主極點產生變動，因此該零 =員電路45及該旁通電路44之等⑼聯電阻（esr)⑷ 無法因應不同之負載進行鮮補償動作。 【發明内容】 [0003] 壓降線性籍嚴、馒無ESR電阻補償之伯 穩壓盗，其包含一訊號輪 一 電壓源、—入、、一两精度參考 償電路、—功康播& 耦态、一令點追蹤補 力革傳輸元件、一補償/八蔽φ 出端，該4電路及-訊號輪 精度參考電壓^ 電壓輸入汛號，該高 原係電性連接該錢輪人端，該誤差放大 099125279 表單編號ΑΟίοι 第4頁/共21頁 0992044429-0 201205226 Ο [0004] ❹ 盗係電性連接該高精度參考電壓源，㈣㈣耗器及該 零點追縱補償電料、電.&連接該誤差放大器，該功率傳 輪兀件係電性連接該源極隨耦器，該補似分壓電路及該 訊號輸出端係電性連接該功率傳輸元件，該訊號輪出端〆 係可輸出-穩定之電壓輪出訊號。本發明係藉由該零點 追縱補償電路之補償效果，當該低壓降線性穩壓器之訊 號輸出端電性連接·_負載，㈣路主極點將因負載之不 同而變動’該零點&縱補償電路係可因應不同之主極點 產生相對應之零點位置，因此可有效達成相位邊界 (Phase margin)補償之功效，此外，本發明之電路設計 係無需外掛等效串聯電阻（ESR)而使得系统在不同之負載 下仍能夠提供一穩定之電壓輸出訊號。 【實施方式】 請參閱第2圖，其係本發明之一較佳實施例，—種無 ESR電阻補償之低壓降線性穩壓器1〇係包含一訊號輸入端 11、一尚精度參考電壓源12、一誤差放大器13、一源極 隨耦器14、一零點追蹤補償電路15、一功率傳輸元件“ 、-補償/分壓電路17及一訊號輸出端18，該訊號輸入端 11係用以提供一電壓輸入訊號，該高精度參考電壓源u 係電性連接該訊號輸入端u，該誤差放大器13係電性連 接該高精度參考電壓源12，該源極隨耦器14及該零點追 蹤補償電路15係電性連接該誤差放大器13，該功率傳輸 元件16係電性連接該源極隨耦器14，該補償/分壓電路u 及該訊號輸出端18係電性連接該功率傳輸元件16，該訊 號輸出端18係可輸出一穩定之電壓輸出訊號。 099125279 表單編號A0101 第5頁/共21頁 0992044429-0 201205226 [0005] 請參閱第1圖，其係為一電子設備之電路方塊圖，由 一電源20、該低壓降線性穩壓器10及一負載30所組成， 在本實施例中，該電源20係可為一電壓範圍介於3.45至 5. 0V之一般電池或可充電電池，該電源所提供之電壓訊 號係為一不穩定之電壓訊號，此一不穩定訊號經由該低 壓降線性穩壓器10後，可有效轉換為一穩定之電壓訊號 ，以因應不同的負載變化，其係為該低壓降線性穩壓器 10之主要功能。 [0006] 請再參閱第1圖及第2圖，該訊號接收端Π係接收該 電源20所提供之該電壓輸入訊號並輸送至該高精度參考 電壓源12，請參閱第3圖，該高精度參考電壓源12係由一 參考電壓單元121、一誤差放大器122及一第一PMOS電晶 體123所構成，該誤差放大器122及該第一PMOS電晶體 123係電性連接該參考電壓單元121，該參考電壓單元 121係藉由電阻間之比值改變以調整一參考訊號端1211之 參考電壓，並使該參考電壓不受溫度及製程飄移之影響 ，該第一 PMOS電晶體123係可作為一啟動電路 (Start-up)以防止該參考電壓單元121中之電晶體完全 沒有電流流動之情形，另外，該誤差放大器122係利用負 回授修正機制使得其電性連接該參考電壓單元121之兩端 點V ,V電壓值相等，因此該參考電壓源12可提供更精準 X y 之參考電壓，請再參閱第2圖，該參考電壓與該補償/分 壓電路17所產生之回授電壓係輸送至該誤差放大器13， 在本實施例中，該誤差放大器13係具有一正極端131、一 負極端132及一輸出端133，該負極端132係電性連接該 099125279 表單編號A0101 第6頁/共21頁 0992044429-0 201205226 高精度參考電壓源12之該參考訊號端1211，該正極端 131係電性連接該補償/分壓電路17，該輸出端133係電 性連接該源極隨耦器14及該零點追蹤補償電路丨5，請參 閱第4圖’該誤差放大器13係另具有一偏壓產生電路丨34 、一電性連接該偏壓產生電路134之PM〇s差動對135及一 電性連接該PM0S差動對135之運算放大器136，該正極端 131及該負極端132係電性連接該pM〇s差動對135，該輸 出端133係電性連接該運算放大器136，在本實施例中， 該運算放大器136係由複數個NMOSt晷體及複數個PM0S 電晶體組成，該參考電壓及該回授電蘿傜經由該誤差放 大器13進行相減及放大動作雨產生一電壓放大訊號，請 再參閱第2圖，該電壓放大訊號係輸送至該源極隨耦器14 以提供一電壓訊號至該功率會輸元件1 6，請參閲第5圖， 5玄源極隨搞器14係具有一第二PM0S電晶:::競141及一電性 連接該第二PM0S電晶體141之第三PM0S電晶體142，其中 該第二PM0S電晶體141.之源極端1411係電性連接該訊號 輸入端11，該第三PM0S電晶體之閘極端1421係電性連接 該誤差放大器13，該第二PM0S電晶體141之汲極端1412 及該第三PM0S電晶體142之源極端1422係電性連接該功 率傳輸元件16，在本實施例中，該功率傳輸元件16係為 一大尺寸（80000/0. 35um)之PM0S電晶體，該源極隨耗 器14係用以控制該功率傳輸元件16之源極端及汲極端之 導通電壓大小，使得該功率傳輸元件16能夠產生穩定< 該電壓輸出訊號，該電壓輸出訊號可輸送至該電壓輪出 端18並提供給該負載30使用。 099125279 表單編號A0101 第7頁/共21頁 0992044429-0 201205226 [0007] 凊參閱第2圖，該補償/分壓電路17係由一第二電容 171 電性連接該第二電容171之第一電阻172及一電 ! 生連接该第二電容171及該第一電阻172之第二電阻173 °亥第—電容171、該第一電阻172及該第二電阻173之 端係電性連接該誤差放大器13之該正極端131，該第一 電阻172及該第二電容171之另一端係電性連接該訊號輸 出端18，其中該第—電阻172及該第二電容171係可產生 零點與一極點，該極點位置係位於該零點之 U+IU/R2)倍處，另外，該第二電容171係具有快速耦合 A訊號輸出端18之電摩雜出訊鍊的功維，因此可有效抑 制系統之電路雜訊，請再參間第2圖，在本實施例中為 了使系統穩定，需維持足夠之相位邊界（Phase margin) ，因此本發明係使用兩種方式對相位邊界作補償動作， 八為使用忒零點追蹤補償電路15，該零點追蹤補償電 路15係具有產生一可變零點位置之功能，該零點追蹤補 償電路15係具有一第四PMO S電晶播1 51及一電性連接該 第四PM〇S電晶體151之第一電溶152，該第四PMOS電晶體 及該第一電容152係鼋性連接該备差放大器13，該第四 PMOS電晶體151被操作於線性區，在本實施例中，該第四 PMOS電晶體151係作為一可變電阻使用，其阻值係隨著該 第四PMOS電晶體1 51閘極所接收之該電壓放大訊號之變化 而改變，由於該負載30係藉由該補償/分壓電路17而連接 至該誤差放大器13之該正極端131，因此該零點追蹤補償 電路15可產生一隨著該負載3〇之電流變化而對應之零點 ，可有效避免因該負载3〇之負載電流突然變化而導致相 099125279 位邊界不足之情形，請再參閱第2圖，該低壓降線性穩壓 表單編號A0101 第8頁/共21頁 0992044429-0 201205226 [0008] Ο [0009] Ο [0010] 器10係另具有一頻率補償電路19，相位邊界補償之另一 方式即為使用該頻率補償電路19，該頻率補償電路19之 一端係電性連接該誤差放大器13之輸出端133，該頻率補 償電路19之另一端係電性連接該訊號輸出端18，在本實 施例中，該頻率補償電路19係可為一電容，該電容係可 產生一低頻零點以補償相位邊界。 請參閱第6及第7圖，其係本發明之實測結果，由第6 圖可知，當該訊號輸入端11之該電壓輸入訊號之電壓值 介於3. 45至5伏特時，該訊號輸出端18之電壓輸出訊號仍 穩定維持在3. 3伏特，其線性調節率（Linear regulation)經由量測可達 0. 012% ， 由第7圖可知 ，當負 載電流 產生變化時（圖中之clock)，該訊號輸出端18之電壓輸 出訊號幾乎沒有任何變動，其負載調節率（Load regulation)經由量 測可達0. 005% ， 具有極高 之系統穩定性 〇 本發明係藉由該零點追蹤補償電路15，可產生一隨 著該負載30之電流變化而對應之零點，有效避免因該負 載30之負載電流突然變化而導致相位邊界不足之情形， 此外，本發明之電路設計係不需_等效串聯電阻（ESR)而使 得系統在不同之負載下仍能夠提供穩定之該電壓輸出訊 號。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神 和範圍内所作之任何變化與修改，均屬於本發明之保護 範圍。 099125279 表單編號A0101 第9頁/共21頁 0992044429-0 201205226 :圖式簡單說明】 [0011] 種無ESR電阻 第1圖：依據本發明之第―較佳實施例，— 補償之低壓降線性穩職之電路方塊圖。 該無ESR電阻補 第2圖··依據本發明之第—較佳實施例 償之低壓降線性穩壓器之電路圖。 該無ESR電阻補 第3圖：依據本發明之第一較佳實_ — 償之降線性穩壓器之高精度參考電壓源之電路圖 第4圖：依據本發明之第_較佳實施例該無電阻補 償之降線性穩壓器之誤差放大器之電路圖。 第5圖：依據本發明之第一較佳實施例，該無_阻補 償之降線性穩壓器之源極隨轉器之電路圖。 第6圖：依據本發明之第—較佳實施例，該無ESR電阻補 h之降線性穩壓器之輸入電堡訊號/輪出電壓訊號波形圖 第7圖：依據本發明之第—較佳實施例 償之降線性穩壓器之負載電流/輸出電壓鑛號波形 第8圖：習知低壓降線性穩壓器之電路圖。 【主要元件符號說明】 [0012] 1 〇低壓降線性穩壓器 12高精度參考電壓源 1211參考訊號端 123第一PMOS電晶體 131正極端 133輸出端 135 PMOS差動對 14源極隨耦器 ，該無ESR電阻補 圖。 11電壓輸入端 121參考電壓單元 122誤差放大器 13誤差放大器 13 2負極端 134偏壓產生電路 136運算放大器 141第二PMOS電晶體 099125279 表單編號A0101 第10頁/共21頁 0992044429-0 201205226 1411源極端 1412沒極端 142第三PM0S電晶體 1421閘極端 1422源極端 15零點追蹤補償電路 151第四PM0S電晶體 152第一電容 17頻率補償及分壓電路 172第一電阻 18訊號輸出端 20電源 40線性穩壓器 4 2放大器網路 ,44.旁通電路 45零點輝償電路 a » ' * __201205226 VI. Description of the Invention: [Technology Leading the Invention] [0001] The present invention relates to a linear regulator, in particular to a low-dropout linear regulator without ESR resistance compensation characteristics. [0002] A conventional linear regulator 40, as disclosed in U.S. Patent No. 7,038,431, which is incorporated herein by reference to FIG. The circuit 44 and the zero-point compensation circuit 45' are electrically connected to the reference voltage source 41. The load 43, the bypass zero path 44 and the zero compensation circuit 45 are electrically connected to the amplifier network. The circuit 42, the linear regulator 40 can generate a transfer function, the transfer function can convert the reference voltage of the reference voltage source 41 to -=疋 voltage and deliver to the load 43 'the zero compensation circuit 45 is used Provide -zero' to compensate for the change of the transfer function due to the variation of the load current. However, the conventional linear voltage regulator (4) only feeds the fixed load frequency = if the load is different, the main pole will change, so the zero = member Circuit 45 and ⑼ other associated resistor of the bypass circuit 44 (esr) ⑷ not keep fresh different load compensating action. SUMMARY OF THE INVENTION [0003] Pressure drop linearity strict, ES no ESR resistance compensation of the primary voltage thief, which includes a signal wheel, a voltage source, - in, one or two precision reference compensation circuit, - Gong Kang broadcast & Coupling state, one-point tracking compensatory leather transmission component, one compensation/eight-mask φ output, the 4-circuit and the signal wheel precision reference voltage ^ voltage input nickname, the plateau is electrically connected to the money wheel human end, The error is amplified by 099125279 Form No. ΑΟίοι Page 4 of 21 page 0992044429-0 201205226 Ο [0004] ❹ The thief is electrically connected to the high-precision reference voltage source, (4) (4) consuming device and the zero point tracking compensation electric material, electricity. Connecting the error amplifier, the power transmission device is electrically connected to the source follower, and the complementary voltage dividing circuit and the signal output end are electrically connected to the power transmission component, and the signal wheel output terminal It can output a stable voltage turn-off signal. According to the invention, the compensation effect of the zero-point tracking compensation circuit is that when the signal output end of the low-dropout linear regulator is electrically connected to the load, the main pole of the (four) way will vary due to the load. The zero point & The vertical compensation circuit can generate the corresponding zero point position according to different main poles, so the effect of phase margin compensation can be effectively achieved. Moreover, the circuit design of the present invention does not require external equivalent series resistance (ESR). The system can still provide a stable voltage output signal under different loads. [Embodiment] Please refer to FIG. 2, which is a preferred embodiment of the present invention. A low-dropout linear regulator without ESR resistance compensation includes a signal input terminal 11 and a precision reference voltage source. 12. An error amplifier 13, a source follower 14, a zero tracking compensation circuit 15, a power transmission component ", a compensation/divider circuit 17 and a signal output terminal 18, the signal input terminal 11 The high-precision reference voltage source u is electrically connected to the signal input terminal u, and the error amplifier 13 is electrically connected to the high-precision reference voltage source 12, the source follower 14 and the The zero-tracking compensation circuit 15 is electrically connected to the error amplifier 13. The power transmission component 16 is electrically connected to the source follower 14, and the compensation/divider circuit u and the signal output terminal 18 are electrically connected. The power transmission component 16 and the signal output terminal 18 can output a stable voltage output signal. 099125279 Form No. A0101 Page 5 of 21 0992044429-0 201205226 [0005] Please refer to FIG. 1 , which is an electronic device. Circuit block diagram, by The power supply 20, the low-voltage drop linear regulator 10, and a load 30, in the embodiment, the power supply 20 can be a general battery or a rechargeable battery having a voltage range of 3.45 to 5.0V. The voltage signal provided is an unstable voltage signal. After the low voltage drop linear regulator 10 is passed, the unstable signal can be effectively converted into a stable voltage signal to respond to different load changes. The main function of the low-dropout linear regulator 10. [0006] Please refer to FIG. 1 and FIG. 2 again, the signal receiving end receives the voltage input signal provided by the power source 20 and sends the voltage input signal to the high-precision reference. For the voltage source 12, please refer to FIG. 3, the high-precision reference voltage source 12 is composed of a reference voltage unit 121, an error amplifier 122 and a first PMOS transistor 123. The error amplifier 122 and the first PMOS battery The crystal 123 is electrically connected to the reference voltage unit 121. The reference voltage unit 121 adjusts the reference voltage of a reference signal terminal 1211 by changing the ratio between the resistors, and the reference voltage is not affected by temperature and process drift. The first PMOS transistor 123 can be used as a start-up to prevent the transistor in the reference voltage unit 121 from flowing completely without current. In addition, the error amplifier 122 is modified by negative feedback. The mechanism is electrically connected to the two ends of the reference voltage unit 121. The V voltages are equal. Therefore, the reference voltage source 12 can provide a more accurate reference voltage of X y . Please refer to FIG. 2 , the reference voltage and the reference voltage The feedback voltage generated by the compensation/divider circuit 17 is sent to the error amplifier 13. In the embodiment, the error amplifier 13 has a positive terminal 131, a negative terminal 132 and an output terminal 133. The extreme 132 series is electrically connected to the compensation/divider circuit. The positive terminal 131 is electrically connected to the compensation/divider circuit. The reference terminal 1211 of the high-precision reference voltage source 12 is electrically connected to the 099125279 form number A0101, page 6 of 21, 0992044429-0, 201205226. 17. The output terminal 133 is electrically connected to the source follower 14 and the zero tracking compensation circuit 丨5. Please refer to FIG. 4, the error amplifier 13 has a bias generating circuit 丨34, an electrical connection The PM〇s differential pair 135 of the bias generating circuit 134 and an operational amplifier 136 electrically connected to the PM0S differential pair 135, the positive terminal 131 and the negative terminal 132 are electrically connected to the pM〇s differential pair 135 The output terminal 133 is electrically connected to the operational amplifier 136. In the embodiment, the operational amplifier 136 is composed of a plurality of NMOS turns and a plurality of PMOS transistors. The reference voltage and the feedback power are via The error amplifier 13 performs a subtraction and amplification operation to generate a voltage amplification signal. Please refer to FIG. 2, the voltage amplification signal is sent to the source follower 14 to provide a voltage signal to the power transmission component 1 6, please refer to FIG. 5, the fifth source device 14 has a second PMOS transistor::: 141 and a third PMOS transistor 142 electrically connected to the second PMOS transistor 141, The source terminal 1411 of the second PMOS transistor 141 is electrically connected to the signal input terminal 11. The gate terminal 1421 of the third PMOS transistor is electrically connected to the error amplifier 13. The second PMOS transistor 141 is electrically connected. The anode terminal 1412 and the source terminal 1422 of the third PMOS transistor 142 are electrically connected. The power transmission component 16 is connected. In the embodiment, the power transmission component 16 is a large-sized (80000/0.35 um) PMOS transistor, and the source stalker 14 is used to control the power transmission component. The source and the extreme on-voltage of the source of the source 16 enable the power transfer component 16 to produce a stable < the voltage output signal that can be delivered to the voltage wheel terminal 18 for use by the load 30. 099125279 Form No. A0101 Page 7 of 21 0992044429-0 201205226 [0007] Referring to FIG. 2, the compensation/divider circuit 17 is electrically connected to the second capacitor 171 by a second capacitor 171. The resistor 172 and an electrical connection are connected to the second capacitor 171 and the second resistor 173 of the first resistor 172. The capacitor 171, the first resistor 172 and the second resistor 173 are electrically connected to the error. The first terminal 172 and the other end of the second capacitor 171 are electrically connected to the signal output terminal 18, wherein the first resistor 172 and the second capacitor 171 can generate a zero point and a The pole position is located at U+IU/R2 times of the zero point. In addition, the second capacitor 171 has the power dimension of the electric hybrid signal chain of the fast coupling A signal output terminal 18, thereby effectively suppressing For the circuit noise of the system, please refer to FIG. 2 again. In this embodiment, in order to stabilize the system, it is necessary to maintain a sufficient phase margin. Therefore, the present invention uses two methods to compensate the phase boundary. Eight is to use the zero point tracking compensation circuit 15, which The point tracking compensation circuit 15 has a function of generating a variable zero point position, and the zero point tracking compensation circuit 15 has a fourth PMO S electric crystal 1 51 and a fourth electrically connected to the fourth PM S crystal 151. An electrolysis 152, the fourth PMOS transistor and the first capacitor 152 are electrically connected to the standby amplifier 13 , and the fourth PMOS transistor 151 is operated in a linear region. In this embodiment, the fourth PMOS The transistor 151 is used as a variable resistor, and its resistance changes according to the change of the voltage amplification signal received by the gate of the fourth PMOS transistor 153, since the load 30 is compensated by the compensation/minute. The voltage circuit 17 is connected to the positive terminal 131 of the error amplifier 13, so that the zero tracking compensation circuit 15 can generate a zero corresponding to the current change of the load 3,, which can effectively avoid the load If the load current suddenly changes and the 099125279 bit boundary is insufficient, please refer to Figure 2, the low dropout linear regulator form number A0101 Page 8 of 21 0992044429-0 201205226 [0008] Ο [0009] Ο [ 0010] 10 has another frequency The compensation circuit 19, another method of phase boundary compensation is to use the frequency compensation circuit 19, one end of the frequency compensation circuit 19 is electrically connected to the output end 133 of the error amplifier 13, and the other end of the frequency compensation circuit 19 is electrically connected. The signal output terminal 18 is connected to the signal. In this embodiment, the frequency compensation circuit 19 can be a capacitor that generates a low frequency zero point to compensate for the phase boundary. Please refer to the sixth and seventh figures, which are the actual measurement results of the present invention. It can be seen from FIG. 6 that when the voltage input signal of the signal input terminal 11 has a voltage value of 3.45 to 5 volts, the signal output is The voltage output signal of the terminal 18 is still stable at 3.3 volts, and the linear regulation rate is up to 0. 012%. It can be seen from the figure 7 that when the load current changes (the clock in the figure) The voltage output signal of the signal output terminal 18 has almost no change, and the load regulation rate is up to 0.005%, which has extremely high system stability. The present invention tracks the zero point. The compensation circuit 15 can generate a zero point corresponding to the current change of the load 30, thereby effectively avoiding a situation in which the phase boundary is insufficient due to a sudden change of the load current of the load 30. Furthermore, the circuit design of the present invention does not require _ The equivalent series resistance (ESR) allows the system to provide a stable voltage output signal under different loads. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. . 099125279 Form No. A0101 Page 9/Total 21 Page 0992044429-0 201205226: Simple Description of the Drawings [0011] Non-ESR Resistor FIG. 1 : According to the first preferred embodiment of the present invention, the compensated low-dropout linear stability Circuit block diagram of the job. The ESR-free resistor is complemented by a circuit diagram of a low-dropout linear regulator in accordance with a first preferred embodiment of the present invention. FIG. 4 is a circuit diagram of a high precision reference voltage source according to a first preferred embodiment of the present invention. FIG. 4 is a view of the first embodiment of the present invention. Circuit diagram of the error amplifier of a linear regulator without resistance compensation. Figure 5 is a circuit diagram of the source follower of the non-resistive compensated falling linear regulator in accordance with a first preferred embodiment of the present invention. Figure 6: According to the first preferred embodiment of the present invention, the input electric buck signal/round voltage signal waveform diagram of the linear regulator without ESR resistors is reduced. Figure 7: According to the present invention The load current/output voltage of the linear regulator of the preferred embodiment is reduced. Figure 8: Circuit diagram of a conventional low-dropout linear regulator. [Main component symbol description] [0012] 1 〇 low-dropout linear regulator 12 high-precision reference voltage source 1211 reference signal terminal 123 first PMOS transistor 131 positive terminal 133 output terminal 135 PMOS differential pair 14 source follower , the no ESR resistor complement map. 11 voltage input terminal 121 reference voltage unit 122 error amplifier 13 error amplifier 13 2 negative terminal 134 bias generation circuit 136 operational amplifier 141 second PMOS transistor 099125279 Form No. A0101 Page 10 / 21 pages 0992044429-0 201205226 1411 source extreme 1412 no extreme 142 third PM0S transistor 1421 gate terminal 1422 source terminal 15 zero point tracking compensation circuit 151 fourth PM0S transistor 152 first capacitor 17 frequency compensation and voltage dividing circuit 172 first resistor 18 signal output terminal 20 power supply 40 linear Voltage regulator 4 2 amplifier network, 44. Bypass circuit 45 zero-point compensator circuit a » ' * __
16功率傳輸元件 171第二電容 17 3第二電阻 19頻率補償電路 30負載 〇 41參考電壓源 43負載 441等效串聯電阻 〇 099125279 表單編號 A0101 11頁/共21頁 0992044429-016 power transmission component 171 second capacitor 17 3 second resistor 19 frequency compensation circuit 30 load 〇 41 reference voltage source 43 load 441 equivalent series resistance 〇 099125279 Form number A0101 11 pages / total 21 pages 0992044429-0