TWI394251B - Stacked package structure and package substrate thereof - Google Patents

Description

Stacked package structure and package substrate thereof

The invention relates to a package structure, in particular to a stacked package structure with a high solder ball yield and a package substrate thereof.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the requirements of high integration and miniaturization of semiconductor packages for more active and passive components and lines, semiconductor package substrates have gradually evolved from two-layer boards to multilayer boards. (multi-layer board), which utilizes an interlayer connection in a limited space to expand the layout area available on the semiconductor package substrate and to meet the needs of a high circuit density integrated circuit. It can achieve the purpose of light and thin package and improved electrical function.

However, since the circuit is usually disposed around the electrical contact pads exposed on the outermost layer of the package substrate, it is necessary to simultaneously cover the surface of the circuit and the electrical contact pads with a solder resist layer such as green paint, and The solder resist layer is formed with a solder resist layer opening of the exposed portion of the electrical contact pad, and the solder resist layer is used to protect the surface of the circuit layer and the electrical contact pad portion from oxidation by the influence of air and moisture of the external environment. However, as the lines in the package substrate become finer and finer, the distance between the electrical contact pads is smaller and smaller, thereby meeting the requirements for fine line and fine pitch, but limited by the use of fine lines and fine pitch. Nowadays, the bottleneck of exposure development technology, if you want to form a small solder mask opening to expose part of the surface of the electrical contact pad, often the alignment is not accurate and the exposure resolution is not good, even causing the solder mask opening offset Or revealing problems such as incomplete opening; for this reason, the solder mask opening is too small to provide sufficient contact area to connect the bump or the solder ball, so the industry has developed a layer in the layer. A technique of directly forming an external electrical contact pad on a dielectric layer (insulating protective layer) to overcome the above problem. Referring to FIG. 1, a cross-sectional view of a stacked package structure made by using a conventional package substrate of the foregoing technology. schematic diagram.

As shown in FIG. 1 , the conventional stacked package structure includes a package substrate 1 , a semiconductor wafer 3 , a package 4 , and an electronic device 5 .

The package substrate 1 includes a substrate body 10, an insulating protective layer 11, and an electrical contact pad 13. The substrate body 10 has opposite first and second surfaces 10a, 10b. The first surface 10a has a first electrical connection pad 104 and a plurality of second portions around the first electrical connection pad 104. The electrical connection pad 102 has a plurality of ball pads 103 on the second surface 10b. The substrate body 10 has a plurality of inner layer lines 100 and conductive blind holes 101, and the conductive blind holes 101 are electrically connected to the inner layer lines 100 and the second electrical connection pads 102. The insulating protective layer 11 is disposed on the first and second surfaces 10a, 10b of the substrate body 10, and has a plurality of openings 110 and first openings 112a in the insulating protective layer 11 on the first surface 10a. Therefore, each of the openings 110 corresponds to each of the second electrical connection pads 102, and each of the first openings 112a corresponds to each of the first electrical connection pads 104. Further, a plurality of second openings 112b are formed in the insulating protective layer 11 on the second surface 10b, so that the ball pads 103 respectively expose the second openings 112b for receiving the solder balls 14. The electrical contact pads 13 are disposed in the openings 110 to electrically connect the electrical contact pads 13 to the second electrical connection pads 102. Further, the upper surface 13a of the electrical contact pad 13 is flat.

The semiconductor wafer 3 is disposed on the insulating protective layer 11 and electrically connected to the first electrical connection pad 104.

The package 4 is formed between the insulating protective layer 11 and the semiconductor wafer 3.

The electronic device 5 is coupled to the insulating protective layer 11 of the first surface 10a of the substrate body 10. The electronic device 5 has a solder ball 50 corresponding to the electrical contact pad 13 to bond the solder ball 50. To the electrical contact pad 13, the electronic device 5 is electrically connected to the substrate body 10.

However, the conventional technique is to form an external electrical contact pad 13 on the surface of the insulating protective layer 11 on the original second electrical connection pad 102. Since the outermost surface of the package substrate is not provided with a circuit layer, the most The outer surface is not additionally applied with a solder resist layer, and the surface of the electrical contact pad 13 can be completely exposed, so as to avoid misalignment and exposure analysis when the surface of the solder contact layer is originally opened to expose the surface of the electrical contact pad portion. Poor degree, even causing the opening of the solder resist layer or revealing the incomplete opening; however, since the soldering layer is not provided by the prior art, the solder ball 50 is bonded to the electrical contact pad. When the surface of the surface 13 is used, the solder ball 50 may be in a liquid state during the reflow process, causing the solder to overflow due to the limitation of the area of the opening of the solder resist layer; and due to the upper surface 13a of the electrical contact pad 13 The flatness and the absence of the solder mask opening limit a space, the solder ball 50 is easy to cause the ball to fall off, and the process of bonding the solder ball 50 is difficult to perform, thereby causing the solder ball to fall off or the solder overflow to cause bridging. And other issues.

Therefore, how to avoid the problem that the external electrical contact pads in the prior art are likely to cause the subsequent solder balls to fall off or the solder overflow to cause bridging has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, it is an object of the present invention to provide a stacked package structure and a package substrate thereof which can enhance the bonding force between a line and a dielectric layer and satisfy the fine pitch requirements of the line.

Another object of the present invention is to provide a stacked package structure and a package substrate thereof which can reduce manufacturing costs.

To achieve the above and other objects, the present invention discloses a package substrate for use in a package on package (POP), comprising: a substrate body having opposite first and second surfaces on the first surface a plurality of first electrical connection pads, and a plurality of second electrical connection pads around the crystallized region, and a plurality of ball pads on the second surface; and insulation protection The layer is disposed on the first and second surfaces of the substrate body, and the plurality of arcuate grooves and the first opening are disposed in the insulating protection layer on the first surface to make each of the arcuate grooves Corresponding to each of the second electrical connection pads, wherein each of the first openings corresponds to each of the first electrical connection pads, and a plurality of micro holes are disposed in each of the arcuate grooves to enable the second electrical connection a portion of the surface of the pad is exposed in the micropores; and an electrical contact pad is disposed in each of the arcuate grooves and the micro holes to electrically connect the electrical contact pad to the second electrical connection pad .

In the above package substrate, the substrate body has a plurality of inner layer lines and conductive blind holes, and the conductive blind holes are electrically connected to the inner layer lines and the second electrical connection pads.

In the above package substrate, the outer surface of the electrical contact pad is arcuate, and the material forming the electrical contact pad is copper.

In the above package substrate, a plurality of second openings are formed in the insulating protective layer on the second surface, so that each of the ball pads corresponding to the second openings is exposed.

The present invention discloses a package on package (POP) structure, comprising: a substrate body having opposite first and second surfaces, having a crystallizing region on the first surface, and the crystallizing region Having a plurality of first electrical connection pads, and having a plurality of second electrical connection pads around the crystallographic region, and having a plurality of ball-forming pads on the second surface; and an insulating protective layer disposed on the substrate body And a plurality of arcuate grooves and a first opening in the insulating protective layer on the first surface, so that the arcuate grooves correspond to the second electrical connecting pads, And each of the first openings corresponds to each of the first electrical connection pads, and a plurality of micro holes are disposed in each of the arcuate grooves, so that a part of the surface of the second electrical connection pad is exposed to the micro An electrical contact pad is disposed in each of the arcuate recesses and the micro holes to electrically connect the electrical contact pad to the second electrical connection pad; the semiconductor wafer is disposed on the crystallographic region An insulating protective layer; and an electronic device, an insulating protective layer bonded to the first surface of the substrate body , Having electrical contact pads to be solder balls, the solder balls to make electrically bonded to the contact pads to enabling the electronic device is electrically connected to the substrate body on the electronic device.

In the above-mentioned stacked package structure, the substrate body has a plurality of inner layer lines and conductive blind holes, and the conductive blind holes are electrically connected to the inner layer lines and the second electrical connection pads.

In the above stacked package structure, the outer surface of the electrical contact pad is arcuate, and the material forming the electrical contact pad is copper. Further, a plurality of second openings are formed in the insulating protective layer on the second surface, so that each of the ball pads corresponding to the second openings is exposed.

In the above stacked package structure, the semiconductor wafer is electrically connected to the first electrical connection pad in a flip chip manner. The package structure further includes a conductive bump disposed in each of the first openings, so that the conductive bumps are electrically connected to the first electrical connection pads and the semiconductor wafer, and the package material is formed. Between the insulating protective layer and the semiconductor wafer.

In addition, in another embodiment, the semiconductor wafer is electrically connected to the first electrical connection pad by wires, and the package material is formed between the insulation protection layer and the semiconductor wafer.

In the foregoing stacked package structure, the electronic device is a circuit board or another package structure.

It can be seen that the package substrate in the stacked package structure of the present invention is formed on the second electrical connection pad covering the inside of the insulation protection layer to form an external electrical contact pad, and the inner layer circuit is provided by The conductive blind hole in the substrate body is electrically connected to the second electrical connection pad and the external electrical contact pad, and the surface of the external electrical contact pad has a curved recess, so that subsequent electrical contact with the external After soldering on the pad, the solder ball of the electronic device is combined, and the contact area between the solder ball and the external electrical contact pad is large, so that the bonding force between the solder ball and the external electrical contact pad is strong, and it is not easy to have The situation in which the solder balls fall off. Furthermore, the arcuate recesses also limit the range of movement of the solder balls, so that the solder balls are less likely to drop balls or cause bridging due to contact with each other. Therefore, compared with the prior art, the stacked package structure of the present invention has the advantages of improving the yield of the processing process of the solder ball and facilitating the product design of the fine pitch.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

Referring to Figures 2A through 2G, a method of fabricating a package on package (POP) structure of the present invention is disclosed.

As shown in FIG. 2A, a substrate body 20 having opposite first and second surfaces 20a, 20b is provided, having a crystallographic region A on the first surface 20a, and having a plurality of first regions in the crystal region A The electrical connection pad 204 has a plurality of second electrical connection pads 202 around the crystal area A, and a plurality of ball pads 203 on the second surface 20b. The substrate body 20 has a plurality of inner layer lines 200 and conductive blind holes 201, and the conductive blind holes 201 are electrically connected to the inner layer lines 200 and the second electrical connection pads 202.

As shown in FIG. 2B, an insulating protective layer 21 is formed on the first and second surfaces 20a, 20b of the substrate body 20.

As shown in FIG. 2C, a plurality of arcuate grooves 210 and first openings 212a are formed in the insulating protective layer 21 on the first surface 20a, so that the arcuate grooves 210 correspond to the second electrical properties. The pads 202 are connected to each other, and the first openings 212a are corresponding to the first electrical connection pads 204. The plurality of micro holes 211 are formed in each of the arcuate grooves 210 to make the second electrical connection pads 202 The surface is exposed in the micropores 211. In addition, a plurality of second openings 212b are formed in the insulating protective layer 21 on the second surface 20b, so that each of the ball pads 203 correspondingly exposes the second openings 212b.

As shown in FIG. 2D, a resist layer 22 is formed on the insulating protective layer 21, and a plurality of open regions 220 are formed in the resist layer 22, so that the arcuate recesses 210 are correspondingly exposed to the respective open regions 220. Optionally, the first opening 212a is exposed to the opening region 220.

As shown in FIG. 2E, an electrical contact pad 23 is formed in each of the open area 220, the arcuate recess 210 in the open area 220, and the micro holes 211 in the arcuate recess 210. The electrical contact pads 23 are electrically connected to the second electrical connection pads 202. The outer surface 23a of the electrical contact pad 23 is arcuate, and the material forming the electrical contact pad 23 is copper.

The conductive bumps 24 are formed in the first opening 212a of the opening region 220 to electrically connect the conductive bumps 24 to the first electrical connection pads 204.

As shown in FIG. 2F, the resist layer 22 is removed to complete the package substrate 2 used for stacking the package structure. The package substrate 2 includes a substrate body 20, an insulating protective layer 21, and an electrical contact pad 23.

The substrate body 20 has opposite first and second surfaces 20a, 20b, and has a crystallized area A on the first surface 20a, and the plurality of first electrical connection pads 204 are disposed in the crystallized area A. And a plurality of second electrical connection pads 202 around the crystallized area A, and a plurality of ball pads 203 on the second surface 20b. The substrate body 20 has a plurality of inner layer lines 200 and conductive blind holes 201, and the conductive blind holes 201 are electrically connected to the inner layer lines 200 and the second electrical connection pads 202.

The insulating protective layer 21 is disposed on the first and second surfaces 20a, 20b of the substrate body 20, and has a plurality of arcuate grooves 210 and first in the insulating protective layer 21 on the first surface 20a. Opening the holes 212a such that the arcuate grooves 210 correspond to the second electrical connection pads 202, so that the first openings 212a correspond to the first electrical connection pads 204, and each of the arcs A plurality of micro holes 211 are defined in the recess 210 to expose a portion of the surface of the second electrical connection pad 202 to the micro holes 211. Further, a plurality of second openings 212b are formed in the insulating protective layer 21 on the second surface 20b, so that each of the ball pads 203 correspondingly exposes the second openings 212b.

The electrical contact pads 23 are disposed in the arcuate recesses 210 and the micro holes 211 to electrically connect the electrical contact pads 23 to the second electrical connection pads 202. Moreover, the outer surface 23a of the electrical contact pad 23 is arcuate, and the material forming the electrical contact pad 23 is copper.

As shown in FIG. 2G, following the process of FIG. 2F, a semiconductor wafer 3 is disposed on the insulating protective layer 21 on the crystallographic region A, and the insulating protective layer 21 of the first surface 20a of the substrate body 20 is further disposed. A package material 4 is formed between the semiconductor wafers 3, and a package structure is fabricated.

Next, an electronic device 5 is mounted on the semiconductor device 3 and the substrate body 20, and the solder ball 50 corresponding to the electrical contact pad 23 is disposed on the electronic device 5 to electrically connect the solder ball 50 to the electrical contact. Pad 23, 俾 completes the fabrication of the stacked package structure described above. The stacked package structure includes the package substrate 2, the semiconductor wafer 3, the package material 4, and the electronic device 5.

The semiconductor wafer 3 is disposed on the insulating protective layer 21 on the crystallographic region A, and the semiconductor wafer 3 is electrically connected to the first electrical connection pad 204 in a flip chip manner, that is, by being disposed in each of the semiconductor wafers The conductive bumps 24 in the first opening 212a are soldered to form solder balls 24' to electrically connect the first electrical connection pads 204 and the semiconductor wafer 3.

The encapsulating material 4 is formed between the insulating protective layer 21 and the semiconductor wafer 3 in a corresponding crystal region A.

The electronic device 5 is, for example, a circuit board or another package structure, and is coupled to the insulating protective layer 21 of the first surface 20a of the substrate body 20. The electronic device 5 has an electrical contact pad 23 corresponding thereto. The solder ball 50 is soldered to the electrical contact pad 23 to electrically connect the electronic device 5 to the substrate body 20.

As shown in FIG. 2G', it is another stacked package structure of the present invention; the difference between this embodiment and the above embodiment is that the semiconductor chip 3 is electrically connected to the first electrical connection pad 204 by the wire 30. The package 4' is formed on the insulating protective layer 21 to cover the semiconductor wafer 3 and the wires 30. Therefore, in the process of the second and second embodiments, no conductive is formed in the first opening 212a. Bump.

In summary, the package substrate of the stacked package structure of the present invention is formed on the second electrical connection pad covering the inside of the insulation protection layer to form an external electrical contact pad, and the inner layer circuit is disposed on the substrate The conductive blind hole in the body is electrically connected to the second electrical connection pad and the external electrical contact pad, and the surface of the external electrical contact pad has a curved recess, and thus is subsequently connected to the external electrical contact pad After reflowing, in combination with the solder ball of the electronic device, the contact area of the solder ball with the external electrical contact pad is large, so that the bonding force between the solder ball and the external electrical contact pad is strong, and it is not easy to be soldered. The situation in which the ball falls off.

Furthermore, the arcuate recesses also limit the range of movement of the solder balls, so that the solder balls are less likely to drop balls or cause bridging due to contact with each other. Therefore, compared with the prior art, the stacked package structure of the present invention has the advantages of improving the yield of the processing process of the solder ball and facilitating the product design of the fine pitch.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1, 2. . . Package substrate

10, 20. . . Substrate body

10a, 20a. . . First surface

10b, 20b. . . Second surface

100, 200. . . Inner line

101, 201. . . Conductive blind hole

102, 202. . . Second electrical connection pad

103, 203. . . Ball pad

104, 204. . . First electrical connection pad

11, 21. . . Insulating protective layer

110. . . Opening

112a, 212a. . . First opening

112b, 212b. . . Second opening

13,23. . . Electrical contact pad

13a. . . Upper surface

14, 24', 50. . . Solder ball

210. . . Arc groove

211. . . Microporous

twenty two. . . Resistance layer

220. . . Open area

23a. . . The outer surface

twenty four. . . Conductive bump

3. . . Semiconductor wafer

30. . . wire

4, 4’. . . Packaging material

5. . . Electronic device

A. . . Crystal zone

Figure 1 is a schematic cross-sectional view of a conventional stacked package structure;

2A to 2G are schematic views showing a method of manufacturing the stacked package structure of the present invention; wherein the 2G' diagram is a schematic view of another embodiment of the 2Gth diagram.

2. . . Package substrate

20. . . Substrate body

20a. . . First surface

20b. . . Second surface

200. . . Inner line

201. . . Conductive blind hole

202. . . Second electrical connection pad

203. . . Ball pad

204. . . First electrical connection pad

twenty one. . . Insulating protective layer

210. . . Arc groove

211. . . Microporous

212a. . . First opening

212b. . . Second opening

twenty three. . . Electrical contact pad

23a. . . The outer surface

twenty four. . . Conductive bump

A. . . Crystal zone

Claims (16)

A package substrate is used for a package on package (POP), comprising: a substrate body having opposite first and second surfaces, having a crystallizing region on the first surface, and the crystallizing region Having a plurality of first electrical connection pads, and having a plurality of second electrical connection pads around the crystallographic region, and having a plurality of ball-forming pads on the second surface; and an insulating protective layer disposed on the substrate body And a plurality of arcuate grooves and a first opening in the insulating protective layer on the first surface, so that the arcuate grooves correspond to the second electrical connecting pads, And each of the first openings corresponds to each of the first electrical connection pads, and a plurality of micro holes are disposed in each of the arcuate grooves, so that a part of the surface of the second electrical connection pad is exposed to the micro And the electrical contact pad is disposed in each of the arcuate grooves and the micro holes to electrically connect the electrical contact pads to the second electrical connection pads. The package substrate of claim 1, wherein the substrate body has a plurality of inner layer lines and conductive blind holes, and the conductive blind holes are electrically connected to the inner layer lines and the second electrical connection pads. The package substrate of claim 1, wherein the outer surface of the electrical contact pad is curved. The package substrate of claim 1, wherein the material forming the electrical contact pad is copper. The package substrate of claim 1, wherein a plurality of second openings are formed in the insulating protective layer on the second surface, so that each of the ball pads correspondingly exposes the second openings. A package on package (POP) structure includes: a substrate body having opposite first and second surfaces, having a crystallized region on the first surface, and having a plurality of first regions in the crystallographic region Electrically connecting the pad and having a plurality of second electrical connection pads around the crystallized area, and having a plurality of ball-forming pads on the second surface; and an insulating protective layer disposed on the first and second sides of the substrate body a plurality of arcuate grooves and a first opening are formed in the insulating protective layer on the first surface, so that each of the arcuate grooves corresponds to each of the second electrical connecting pads, so that each The first opening corresponds to each of the first electrical connection pads, and a plurality of micro holes are disposed in each of the arcuate grooves, so that a part of the surface of the second electrical connection pad is exposed in the micro holes; The contact pads are disposed in the arcuate recesses and the micropores to electrically connect the electrical contact pads to the second electrical connection pads; the semiconductor wafer, the insulating protective layer disposed on the crystallographic region And an electronic device coupled to the insulating protective layer of the first surface of the substrate body, the electronic device Should solder balls having electrical contact pads, the solder balls to make electrically bonded to the contact pads to enabling the electronic device electrically connected to the substrate body. The stacked package structure of claim 6, wherein the substrate body has a plurality of inner layer lines and conductive blind holes, and the conductive blind holes are electrically connected to the inner layer lines and the second electrical connection pads. . The stacked package structure of claim 6, wherein the outer surface of the electrical contact pad is curved. The stacked package structure of claim 6, wherein the material forming the electrical contact pad is copper. The stacked package structure of claim 6, wherein a plurality of second openings are formed in the insulating protective layer on the second surface, so that each of the ball pads corresponding to the second openings is exposed. The stacked package structure of claim 6, wherein the semiconductor wafer is electrically connected to the first electrical connection pad in a flip chip manner. The stacked package structure of claim 11 further includes a conductive bump disposed in each of the first openings to electrically connect the conductive bumps to the first electrical connection pads and the semiconductor wafer. The package structure according to claim 11 of the patent application, comprising a package material, is formed between the insulation protection layer and the semiconductor wafer. The stacked package structure of claim 6, wherein the semiconductor chip is electrically connected to the first electrical connection pad by wires. The package structure of claim 14 is further comprising a package material formed on the insulation protection layer to encapsulate the semiconductor wafer and the wire. The stacked package structure of claim 6, wherein the electronic device is a circuit board or another package structure.