TWI389619B - Method for manufacturing multi-layer printed circuit board - Google Patents

Description

Multilayer circuit board manufacturing method

The present invention relates to the field of circuit board fabrication, and more particularly to a method of fabricating a multilayer circuit board having a conductive structure.

With the advancement of science and technology, printed circuit boards have been widely used due to their high assembly density. For application of the circuit board, please refer to the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans On Components, Packaging, and Manufacturing Technology, 1992, 15(4): 418-425.

The fabrication of a multi-layer circuit board is usually made by laminating, that is, each inner circuit layer is sequentially formed, and then film is placed between the inner circuit layers and pressed into a whole, and then integrated into a whole. The inner circuit board is drilled to form a through hole penetrating the plurality of inner layer lines, and then the through hole is plated to form a via hole, and finally the outer copper layer is etched to obtain the outermost layer, thereby obtaining a plurality of layers. Circuit board. In the above manufacturing method, each of the inner layer circuit layers is separately fabricated, so that when the layers are made, the inner and outer circuit layers are inconsistent due to the difference in the manufacturing conditions, and it is not easy to accurately perform the pressing. Bit. During the through-hole plating process, a plating layer is also formed on the outer copper foil layer, so that the thickness of the outer copper foil layer is increased and the thickness of the plating layer is not uniform, and etching is incomplete or over-etched during the etching process, which affects The quality of the outer circuit. In addition, the through hole is usually formed by mechanical drilling or laser hole forming, and it is easy to leave a slag generated by the film or the insulating layer due to high temperature in the hole. In the through-hole plating process, the slag is likely to cause poor reliability of the formed via holes. When the number of layers of the circuit board is large, the depth of the through holes formed is large, and when plating is performed, it is difficult for the plating solution to flow into the through holes, resulting in poor conductivity of the via holes.

In view of the above, it is necessary to provide a multilayer circuit board manufacturing method capable of ensuring good reliability of the formed interlayer structure.

A method of fabricating a multilayer circuit board will be described below by way of example.

A method for fabricating a multi-layer circuit board, comprising the steps of: providing a metal substrate, wherein the metal substrate comprises a plurality of regions arranged in sequence, each region comprising a product region and a peripheral region surrounding the product region, the metal substrate having a first surface and a second surface; a first insulating layer is formed on the first surface, and a first through hole is formed in the first insulating layer corresponding to each product region; and the metal substrate is etched to form a plurality of product regions correspondingly a plurality of conductive lines, wherein a region of the plurality of conductive lines that needs to be turned on is exposed from the first through hole; a second insulating layer is formed on the second surface of the metal substrate, and each of the product regions is formed with a corresponding second insulating layer a second via hole, each of the first via holes corresponding to the first second via hole, wherein a region of the plurality of conductive lines that needs to be turned on is exposed from the second via hole; forming a first via pillar in the first via hole a first conductive pillar protrudes from the first insulating layer, a second conductive pillar is formed in the second through hole, and the second conductive pillar protrudes from the second insulating layer, so that each region corresponds to Forming a circuit board area; and folding and pressing a plurality of the circuit board areas such that the plurality of circuit board areas overlap each other and become a whole, and the first conductive pillars or the second conductive pillars located in the adjacent circuit board area are in contact with each other The first conductive pillars and the second conductive pillars that are in contact with each other are electrically connected to each other by adjacent conductive lines.

Compared with the prior art, the multi-layer circuit board manufacturing method provided by the technical solution has the following advantages: First, in the process of manufacturing the circuit board, the layers of the circuit board are simultaneously fabricated, which can effectively prevent the layers of the obtained circuit board from being shrunk. Inconsistent issues. Secondly, the interlayer conduction of the multi-layer circuit board is not conducted by drilling and electroplating, so that the problem of poor inter-layer communication communication due to conduction by drilling and electroplating can be effectively avoided.

The method for fabricating the circuit board provided by the technical solution will be further described below with reference to the accompanying drawings and embodiments.

The embodiment of the technical solution provides a method for fabricating a multi-layer circuit board. The following describes a method for fabricating the circuit board by taking a four-layer circuit board as an example. The method for manufacturing a multilayer circuit board includes the following steps:

Referring to FIG. 1, in a first step, a metal substrate 110 is provided. The metal substrate 110 includes a first region 111, a second region 112, a third region 113, and a fourth region 114 which are sequentially arranged.

The metal substrate 110 has a first surface 115 and a second surface 116 opposite to each other. The metal substrate 110 may be a copper foil generally used for fabricating a flexible circuit board, which may be an electrolytic copper foil or a rolled copper foil. The metal substrate 110 may also be made of a metal having good electrical conductivity such as silver or aluminum. In this embodiment, the metal substrate 110 has an elongated shape, and includes a first region 111, a second region 112, a third region 113, and a fourth region 114 which are sequentially arranged along the longitudinal direction thereof. The first region 111, the second region 112, the third region 113, and the fourth region 114 respectively correspond to four conductive layers of the four-layer circuit board to be fabricated.

The first region 111 includes a first product region 1111 and a first peripheral region 1112 surrounding the first product region 1111. In this embodiment, the first product region 1111 is rectangular, and the first peripheral region 1112 is substantially a "mouth" shape that surrounds the first product region 1111. The second region 112 includes a second product region 1121 and a second peripheral region 1122 surrounding the second product region 1121. The third region 113 includes a third product region 1131 and a third peripheral region 1132 surrounding the third product region 1131. The fourth region 114 includes a fourth product region 1141 and a fourth peripheral region 1142 surrounding the fourth product region 1141. The shape and size of the second product region 1121, the third product region 1131, and the fourth product region 1141 are the same as the shape and size of the first product region 1111. The shape and size of the second peripheral region 1122, the third peripheral region 1132, and the fourth peripheral region 1142 are the same as the shape and size of the first peripheral region 1112.

Referring to FIG. 1 and FIG. 2 together, in the second step, a first insulating layer covering the first region 111, the second region 112, the third region 113, and the fourth region 114 is formed on the first surface 115 of the metal substrate 110. 120. The first insulating layer 120 has a plurality of first via holes 121 and a plurality of first alignment holes 122.

The positions of the plurality of first through holes 121 are respectively corresponding to the first product area 1111, the second product area 1121, the third product area 1131, and the fourth product area 1141, and the positions of the plurality of first alignment holes 122 are respectively opened and A peripheral region 1112, a second peripheral region 1122, a third peripheral region 1132, and a fourth peripheral region 1142 correspond to each other. The shape and the number of the first through holes 121 can be set according to actual needs of the circuit board. The first through hole 121 may be circular or rectangular, and may have other shapes. In this embodiment, the first alignment hole 122 is a circular hole.

In this embodiment, the first insulating layer 120 is formed on the first surface 115 by using a blanket. Before the pressing, a plurality of first through holes 121 and a plurality of first alignment holes 122 are formed in the first insulating layer 120. After the first insulating layer 120 is pressed against the metal substrate 110, the first insulating layer 120 corresponding to the first product region 1111, the second product region 1121, the third product region 1131, and the fourth product region 1141 has two The first through holes 121 are one of a square through hole and one of which is a circular through hole. Moreover, the two first through holes 121 corresponding to the first product region 1111 and the two first through holes 121 corresponding to the second product region 1121 are symmetrically arranged with respect to the boundary between the first region 111 and the second region 112. The two first through holes 121 corresponding to the second product region 1121 and the two first through holes 121 corresponding to the third product region 1131 are symmetrically disposed with respect to the boundary between the second region 112 and the third region 113, and The two first through holes 121 corresponding to the three product regions 1131 and the two first through holes 121 corresponding to the fourth product region 1141 are symmetrically disposed with respect to the boundary between the third region 113 and the fourth region 114. The first insulating layer 120 corresponding to the first peripheral region 1112, the second peripheral region 1122, the third peripheral region 1132, and the fourth peripheral region 1142 each has a first alignment hole 122. The first alignment hole 122 corresponding to the first peripheral region 1112 and the first alignment hole 122 corresponding to the second peripheral region 1122 are symmetrically disposed with respect to the boundary between the first region 111 and the second region 112, and the second The first alignment hole 122 corresponding to the peripheral region 1122 and the first alignment hole 122 corresponding to the third peripheral region 1132 are symmetrically disposed with respect to the boundary line between the second region 112 and the third region 113, and the third peripheral region 1132 The corresponding first alignment hole 122 and the first alignment hole 122 corresponding to the fourth peripheral region 1142 are symmetrically disposed with respect to the boundary between the third region 113 and the fourth region 114.

The first insulating layer 120 can also be formed by printing a liquid insulating material. That is, a liquid insulating material is printed on the first surface 115 of the metal substrate 110 by providing a screen corresponding to the pattern of the first through hole 121 and the first alignment hole 122. The liquid insulating material used should have low hygroscopicity, good dimensional stability, electrical insulation and chemical resistance. The liquid insulating material can be liquid polyimide or liquid crystal polymer material (Liquid). Crystal polymer).

Referring to FIG. 1 , FIG. 3 and FIG. 4 , in the third step, the metal substrate 110 is etched to form a first conductive line 130 in the first product region 1111 and a second conductive region in the second product region 1121 . The line 140 forms a third conductive line 150 in the third product region 1131 and a fourth conductive line 160 in the fourth product region 1141.

In this embodiment, the first conductive line 130, the second conductive line 140, the third conductive line 150, and the fourth conductive line 160 are formed in the metal substrate 110 by an image transfer process and an etching process, and the first conductive line 130 is made. The region that needs to be turned on is exposed from the first via hole 121 corresponding to the first product region 1111, and the region of the second conductive trace 140 that needs to be turned on is exposed from the first via hole 121 corresponding to the second product region 1121. The region of the three conductive lines 150 that needs to be turned on is exposed from the first via hole 121 corresponding to the third product region 1131, and the region of the fourth conductive trace 160 that needs to be turned on is from the first via hole corresponding to the fourth product region 1141. 121 exposed. The first through hole 121 has a smaller aperture than the conductive line exposed therefrom.

After forming the first conductive line 130, the second conductive line 140, the third conductive line 150, and the fourth conductive line 160, the first peripheral area 1112, the second peripheral area 1122, the third peripheral area 1132, and the fourth The peripheral region 1142 forms a second alignment hole 170, respectively. Each of the second alignment holes 170 is in direct communication with a first alignment hole 122.

In order to facilitate subsequent folding, the metal substrate 110 located at the boundary line of adjacent adjacent regions may be etched away along the boundary line while etching to form the plurality of conductive lines.

Referring to FIG. 5 and FIG. 6 , the fourth step is to form a second insulating layer 180 on the second surface 116 of the metal substrate 110. The second insulating layer 180 has a plurality of second via holes 181 and a plurality of third alignment holes. 182. The plurality of second through holes 181 are in one-to-one correspondence with the plurality of first through holes 121. The plurality of third alignment holes 182 are in one-to-one correspondence with the plurality of second alignment holes 170.

In this embodiment, the second insulating layer 180 is formed in the same manner as the first insulating layer 120, so that the first conductive line 130, the second conductive line 140, the third conductive line 150, and the fourth conductive line 160 need to be turned on. It is also exposed from the second through hole 181.

Referring to FIG. 7 and the fifth step, a first conductive pillar 123 is formed in the first through hole 121, and a second conductive pillar 183 is formed in the second through hole 181. The first conductive pillar 123 is partially protruded from the first conductive pillar 183. The insulating layer 120 and the second via 183 are partially protruded from the second insulating layer 180.

In this embodiment, the first via post 123 and the second via post 183 are formed by printing solder paste. First, the first via post 123 and the second via post 183 are formed in the first via hole 121 by means of stencil printing. The first insulating layer 120 and the second insulating layer 180 are cover films, and the first insulating layer 120 and the second insulating layer 180 have a thickness of about 30 micrometers. The thickness of the steel plate of the printing solder paste used in this embodiment is about 100 micrometers, and the heights of the first conductive pillars 123 and the second conductive pillars 183 are greater than the depths of the first through holes 121 and the second through holes 181. One end of the first conductive pillar 123 is in contact with the first conductive line 130, the second conductive line 140, the third conductive line 150 or the fourth conductive line 160, the other end protrudes from the first through hole 121, and the second conductive column 183 One end is in contact with the first conductive line 130, the second conductive line 140, the third conductive line 150 or the fourth conductive line 160, and the other end protrudes from the second through hole 181. Then, the first via post 123 and the second via post 183 which are formed by printing are subjected to high-temperature re-melting, so that the first via post 123 fully fills the first via hole 121 and protrudes from the first via hole 121, and the second conductive via is performed. The post 183 sufficiently fills the second through hole 181 and protrudes from the second through hole 181.

The first region 111 of the metal substrate 110 and the first insulating layer 120 corresponding to the first region 111, the second insulating layer 180 corresponding to the first region 111, and the first via post 123 corresponding to the first region 111 and the first region 111 correspond to The second conductive posts 183 together form a first circuit board area 101. The first insulating layer 120 corresponding to the second region 112 and the second region 112 of the metal substrate 110, the second insulating layer 180 corresponding to the second region 112, and the first conductive pillar 123 corresponding to the second region 112 and the first region 111 correspond to The second conductive posts 183 together form a second circuit board region 102. The first insulating layer 120 corresponding to the second region 112 and the second region 112 of the metal substrate 110, the second insulating layer 180 corresponding to the second region 112, and the first conductive pillar 123 and the second region 112 corresponding to the second region 112 correspond to The second conductive posts 183 together form a second circuit board region 102. The first insulating layer 120 corresponding to the third region 113 and the third region 113 of the metal substrate 110, the second insulating layer 180 corresponding to the third region 113, and the first via post 123 and the third region 113 corresponding to the third region 113 correspond to The second conductive posts 183 together form a third circuit board region 103. The first insulating layer 120 corresponding to the fourth region 114 and the fourth region 114 of the metal substrate 110, the second insulating layer 180 corresponding to the fourth region 114, and the first conductive pillar 123 and the fourth region 114 corresponding to the fourth region 114 correspond to The second conductive posts 183 together form a fourth circuit board region 104.

Referring to FIG. 8, the sixth step is selectively performed on the first circuit according to the folding manner of the predetermined first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104. The surface of the first insulating layer 120 and the second insulating layer 180 corresponding to the board region 101, the second circuit board region 102, the third circuit board region 103, and the fourth circuit board region 104 is adhered to the adhesive layer 190 in the adhesive layer 190. A third through hole 191 is formed.

The third through hole 191 corresponds to the first through hole 121 and the second through hole 181 , and the first conductive post 123 and the second conductive post 183 are exposed from the corresponding third through hole 191 . The glue layer 190 may be made of epoxy resin or acrylic resin, which may be a low flow amount of semi-cured film. Before the adhesive layer 190 is attached to the surfaces of the first insulating layer 120 and the second insulating layer 180, the third through holes 191 are formed in the adhesive layer 190.

In this embodiment, the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104 need to be sequentially stacked, that is, the first circuit board area 101 corresponds to the second. The insulating layer 180 is opposite to the surface of the second insulating layer 180 corresponding to the second circuit board region 102. The surface of the first insulating layer 120 of the second circuit board region 102 and the first insulating layer 120 corresponding to the third circuit board region 103 The second insulating layer 180 corresponding to the third circuit board region 103 is opposite to the second insulating layer 180 of the fourth circuit board region 104. Therefore, the surface of the second insulating layer 180 corresponding to the first circuit board region 101 corresponding to the first product region 1111 and the first insulating layer 120 corresponding to the second circuit board region 102 correspond to the second product region 1121. The surface of the second insulating layer 180 corresponding to the third circuit board region 103 is bonded to the surface of the third product region 1131.

Of course, the position at which the adhesive layer 190 is disposed is not limited to the region set in the embodiment, as long as the adhesive layer 190 is disposed between the surface of the first insulating layer 120 or the surface of the second insulating layer 180 after being folded.

Referring to FIG. 9, the seventh step is folded and pressed along the boundary between the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104 as needed. The first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104 are integrated, and the first conductive line 130, the second conductive line 140, and the third conductive line 150 are The fourth conductive line 160 is electrically connected to each other by providing a first via post 123 and a second via post 183 which are integrated with each other, thereby obtaining a multilayer circuit board 100 having interlayer interconnection.

During the folding process, the folded first board area 101, the second board area 102, the third board area 103, and the fourth board area 104 need to be aligned. In this embodiment, the first alignment hole 122 and the second alignment hole 170 are disposed on the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104. The third alignment hole 182 is aligned. That is, after folding, the first alignment hole 122, the second alignment hole 170, and the third alignment hole 182 located in different circuit board regions are opposite to each other, so that the first circuit board region 101 and the second circuit board region are located. 102. The first conductive pillar 123 and the second conductive pillar 183 of the third circuit board area 103 and the fourth circuit board area 104 are mutually opposite each other. If the first circuit board area 101 and the second circuit board area 102 are folded such that the surface of the second insulating layer 180 of the first circuit board area 101 is opposite to the surface of the second insulating layer 180 of the second circuit board area 102, The first alignment hole 122, the second alignment hole 170 and the third alignment hole 182 in the first circuit board region 101 and the first alignment hole 122 and the second pair in the second circuit board region 102 The bit hole 170 and the third alignment hole 182 are opposite to each other. In this way, the alignment relationship between the first conductive line 130 in the first circuit board area 101 and the second conductive line 140 in the second circuit board area 102 can be ensured, and the first position in the first circuit board area 101 is ensured. The via post 123 and the second via post 183 and the first via post 123 and the second via post 183 located in the second board region 102 overlap each other. When folding the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104, different folding modes may be adopted according to actual production requirements, thereby changing the first The stacking relationship between the board area 101, the second board area 102, the third board area 103, and the fourth board area 104 obtains different boards.

In this embodiment, the folded first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104 are pressed by a quick press. During the pressing process, the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104 are heated such that the first circuit board area 101 and the second circuit board The first conductive pillar 123 and the second conductive pillar 183 of the region 102, the third circuit board region 103, and the fourth circuit board region 104 are melted, and under the action of pressure, the first conductive pillars 123 that are in direct contact with each other or The second conductive pillars 183 are all integrated, so that the first conductive line 130, the second conductive line 140, the third conductive line 150 and the fourth conductive line 160 are disposed with the first conductive pillar 123 integrated therebetween. And the second conductive pillars 183 are electrically connected to each other.

Referring to FIG. 10, the circuit board manufacturing method provided in this embodiment may further include forming a circuit board 100 after the circuit board 100 is obtained. That is, by pressing forming, the area corresponding to the peripheral area of the circuit board 100 is removed, and only the corresponding portion of the product area is left, thereby obtaining a circuit board that satisfies the shape of the customer's demand.

The multi-layer circuit board manufacturing method provided by the technical solution has the following advantages: First, in the process of manufacturing the circuit board, the layers of the circuit board are simultaneously fabricated, which can effectively avoid the problem of inconsistent expansion and contraction of the layers of the obtained circuit board. Secondly, the interlayer conduction of the multi-layer circuit board is not conducted by drilling and electroplating, so that the problem of poor inter-layer communication communication due to conduction by drilling and electroplating can be effectively avoided. Thirdly, since the circuit board is made of pure copper foil and the insulating layer is pressed, since the price of the copper foil and the insulating layer is lower than that of the backed copper foil, the production cost of the circuit board can be reduced.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧ boards

101‧‧‧First board area

102‧‧‧Second circuit board area

103‧‧‧ Third board area

104‧‧‧4th board area

110‧‧‧Metal substrate

111‧‧‧First area

1111‧‧‧First product area

1112‧‧‧First surrounding area

112‧‧‧Second area

1121‧‧‧Second product area

1122‧‧‧Second surrounding area

113‧‧‧ Third Area

1131‧‧‧ Third Product Area

1132‧‧‧The third surrounding area

114‧‧‧fourth area

1141‧‧‧ Fourth Product Area

1142‧‧‧4th surrounding area

115‧‧‧ first surface

116‧‧‧ second surface

120‧‧‧First insulation

121‧‧‧First through hole

122‧‧‧First registration hole

123‧‧‧First conducting column

130‧‧‧First conductive line

140‧‧‧Second conductive line

150‧‧‧third conductive line

160‧‧‧fourth conductive line

170‧‧‧Second registration hole

180‧‧‧Second insulation

181‧‧‧Second through hole

182‧‧‧ third alignment hole

183‧‧‧Second conductive column

190‧‧‧ glue layer

191‧‧‧ third through hole

FIG. 1 is a schematic diagram of a metal substrate provided by an embodiment of the present technical solution.

FIG. 2 is a schematic view of the embodiment of the present invention after the first insulating layer is formed on the surface of the metal substrate.

FIG. 3 is a schematic diagram of the first surface of the metal substrate provided by the embodiment of the present technical solution after forming a conductive line.

Figure 4 is a schematic cross-sectional view taken along line IV-IV of Figure 3.

FIG. 5 is a schematic view of the second embodiment of the present invention after the second insulating layer is formed on the second surface of the metal substrate.

Figure 6 is a cross-sectional view taken along line VI-VI of Figure 5.

FIG. 7 is a schematic view showing the first via post formed in the first via hole and the second via post formed in the second via hole provided by the embodiment of the present technical solution.

FIG. 8 is a schematic view showing the formation of a glue layer on the surfaces of the first insulating layer and the second insulating layer provided by the embodiment of the present technical solution.

FIG. 9 is a schematic diagram of a plurality of circuit board regions provided by embodiments of the present technical solution stacked and pressed.

FIG. 10 is a schematic diagram of a plurality of circuit board regions provided by an embodiment of the present technical solution stacked and pressed and formed.

100‧‧‧ boards

123‧‧‧First conducting column

130‧‧‧First conductive line

140‧‧‧Second conductive line

150‧‧‧third conductive line

160‧‧‧fourth conductive line

183‧‧‧Second conductive column

190‧‧‧ glue layer

Claims (10)

A method for manufacturing a multilayer circuit board, comprising the steps of:
Providing a metal substrate, the metal substrate comprising a plurality of regions arranged in sequence, each region comprising a product region and a peripheral region surrounding the product region, the metal substrate having opposite first and second surfaces;
Forming a first insulating layer on the first surface, and forming a first through hole in the first insulating layer corresponding to each product region;
Etching the metal substrate such that a plurality of conductive regions are formed corresponding to the plurality of product regions, and a region of the plurality of conductive traces that needs to be turned on is exposed from the first via holes;
Forming a second insulating layer on the second surface of the metal substrate, wherein each of the second insulating layers corresponding to each of the product regions is formed with a second through hole, and each of the first through holes corresponds to a second through hole. An area of the plurality of conductive lines that needs to be turned on is exposed from the second through hole;
Forming a first conductive pillar in the first through hole, the first conductive pillar protrudes from the first insulating layer, the second conductive pillar is formed in the second through hole, and the second conductive pillar protrudes from the second insulating layer, thereby Each of the regions corresponds to a circuit board region; and the plurality of circuit board regions are folded and pressed so that the plurality of circuit board regions overlap each other and become a whole, and the first conductive pillar or the second conductive region located in the adjacent circuit board region The pillars are in contact with each other such that adjacent conductive lines are electrically connected to each other by the first via post and the second via post that are in contact with each other. The method for fabricating a multi-layer circuit board according to claim 1, wherein the first conductive post is formed by printing a liquid solder paste corresponding to a region corresponding to the first via hole, and the second conductive via is formed by the second pass A liquid solder paste is formed in the area corresponding to the hole. The method for fabricating a multi-layer circuit board according to the second aspect of the invention, wherein after printing the liquid solder paste in the area corresponding to the first through hole and the second through hole, further comprising performing high temperature remelting on the printed solder paste. The steps. The method for fabricating a multilayer circuit board according to claim 2, wherein the material of the solder paste is a tin-silver-copper alloy. The method for fabricating a multi-layer circuit board according to the first aspect of the invention, wherein the first insulating layer and the region corresponding to each peripheral region are formed with a first pair of bit holes, and the plurality of conductive lines are correspondingly formed in the plurality of product regions. And forming a plurality of second alignment holes correspondingly in the plurality of peripheral regions, wherein the plurality of first alignment holes and the plurality of second alignment holes are in one-to-one correspondence, and the second insulating layer forms a region corresponding to each peripheral region. There is a third pair of bit holes, and the plurality of third bit holes and the plurality of second bit holes are in one-to-one correspondence, and when the plurality of circuit board regions are folded, the first pair of bit holes located in each circuit board area are obtained. The second alignment hole and the third alignment hole are respectively connected to each other to locate the plurality of circuit board regions. The method for fabricating a multi-layer circuit board according to claim 5, wherein between the folding of the plurality of circuit board regions, the surface of the two first insulating layers or the second insulating layer to be opposed after folding The step of forming a glue layer on one of the surfaces. The method of fabricating a multi-layer circuit board according to claim 6, wherein the adhesive layer has a plurality of third through holes, each of the third through holes being associated with a first conductive post or a second conductive via Correspondingly, the first conductive pillar or the second conductive pillar extends from the corresponding third through hole. The method of fabricating a multi-layer circuit board according to the first aspect of the invention, wherein the folding of the plurality of circuit board regions is performed so that the plurality of the circuit board regions become a unit, and further comprising the step of stamping. The method for fabricating a multi-layer circuit board according to claim 1, wherein, when the folded plurality of circuit board regions are pressed together, the folded plurality of circuit board regions are simultaneously heated to make the first conductive pillars in contact with each other. And the second conductive pillar is melted to form an integral structure. The method of fabricating a multi-layer circuit board according to claim 1, wherein the first insulating layer is formed by pressing a first surface of the metal substrate, and the second insulating layer is formed by the second surface of the metal substrate. Pressing the cover film is formed.