201143567 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及電路板製作領域，尤其涉及一種製作具有導 通結構之多層電路板之方法。 【先前技#亍】 [0002] 隨著科學技術之進步，印刷電路板因具有裝配密度高等 優點而得到廣泛應用。關於電路板之應用請參見文獻 Takahash i, A. Ook i, N. Naga i, A. Akahosh i, H. Mukoh, A. Waj ima, M. Res. Lab, High dens-ity multilayer pri.nted circuit board for HITAC M-880 * IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992， 15(4): 418-425 。 [0003] 多層電路板之製作通常藉由逐層壓合之方式製作，即先 依次製作各内層線路層，再將各内層線路層之間設置膠 片並壓合成為一整體，然後對成為一整體之内層線路板 進行鑽孔，形成一個貫穿多層内層線路之通孔，再對所 述通孔進行電鍍，形成導通孔，最後於外層之銅箔層進 行蝕刻得到最外層之線路，從而得到多層電路板。於上 述之製作方法中，每一内層線路層均單獨製作，從而於 製作各層線路時，由於製作條件之差異，導致各内層線 路層之漲縮不一致，於進行壓合時，不易準確對位。於 進行通孔電鍍過程中，亦會於外層之銅箔層上形成鍍層 ，從而使得外層銅箔層厚度增加並且鍍層厚度並不均勻 ，於蝕刻過程中容易產生蝕刻不完全或者過蝕現象，影 099116969 表單編號A0101 第4頁/共31頁 0992030146-0 201143567 響外層線路之品質。此外，所述通孔通常採用機械鑽孔 或者鐳射成孔方式形成，容易於孔内剩餘由膠片或絕緣 層由於高溫而產生之膠渣。於進行通孔電鍍過程中，膠 /查谷易13_成形成之導通孔之信賴性較差。當電路板之層 數較多和·，形成之通孔深度較大，於進行電鐘時，電鑛 溶液難以流入通孔内，導致導通孔之導電性較差。 【發明内容】 [0004] Ο [0005] [0006] ❹ 099116969 有鑑於此’提供一種能夠保證形成之層間結構具有良好 之信賴性之多層電路板製作方法實屬必要。 以下將以實施例說明一種多層電路板製作方法。 一種多層電路板製作方法，包括步驟：提供金屬基板， 所述金屬基板包括依次設置之複數區域，每個區域包括 產品區域及環繞產品區域之週邊區域*所述金屬基板具 有相對之第一表面及第二表面；於所述第一表面形成有 第一絕緣層，所述每個產品區域對應之第十絕緣層内均 形成有第一通孔；對金屬基板進筏蝕刻，使得複數產品 區域對應形成複數導電線路，複數導電線路中需要導通 之區域從所述第一通孔露出；於金屬基板之第二表面形 成第二絕緣層，所述每個產品區域對應之第二絕緣層内 均形成有第二通孔’每個第一通孔均與第一第二通孔相 對應，複數導電線路中需要導通之區域從所述第二通孔 露出；於第一通孔内形成第一導通枉，第一導通柱凸出 於第一絕緣層，於第二通孔内形成第二導通枉，第二導 通柱凸出於第二絕緣層，從而使得每個區域對應構成一 個電路板區域；及折疊並壓合複數所述電路板區域’使 表單編號Α0101 第5頁/共31頁 0992030146-0 201143567 [0007] [0008] [0009] [0010] [0011] 得複數電路板區域相互重疊並成為一個整體，位於相鄰 電路板區域之第一導通柱或第二導通柱相互接觸並使 付相鄰之導電線路之間藉由相互接觸之第一導通柱及第 二導通柱相互電導通。 相較於先前技術’本技術方案提供之？層電路板製作方 法，具有如下優點：首先，於進行電路板製作過程中， 電路板之各層同時製作’可有效之避免制得之電路板各 層/張縮不-致之問題。其次，多層電路板之層間導通不 知用鑽孔及電鍍之方式導通，從*可有效避免由於鑽孔 及電鍍之方式導通產生之層間導通信賴性差之問題。 【實施方式】 下面結合複數附圖及實施例對本技術方案提供之 製作方法作進一步說明。 略板 本技術方案實施例提供一種多層電路板製作方法’下麵 以製作四層電路板為例來說明該電路板製作方 _ 所述 夕層電路板製作方法包括如下步驟： 請參閱圖1，第一步，提供金屬基板110，金屬基板勺 括依次排列之第一區域U1、第二區域112、第三區域 113及第四區域114。 金屬基板110具有相對第—表面n 5及第二表面1ΐβ。公 屬基板110可為製作柔性電路板通常採用之銅箔，其可為 電解銅箔，亦可為壓延鋼箔。金屬基板11〇亦可由_^鋁 等具有良好導電性能之金屬製成。本實施例中，3 泛屬基 板110為長條形，沿其長度方向，包括依次排列之第—區 099116969 表單編號Α0101 第6頁/共31頁 0992030146-0 201143567 域111、第二區域112、第三區域113及第四區域114。該 第一區域111、第二區域112、第三區域113及第四區域 114分別與欲製作之四層電路板之四層導電層相對應。 [0012]第一區域111包括第一產品區域1111及環繞第一產品區域 1111之第一週邊區域丨112。本實施例中，第一產品區域 • 1111為長方形，第一週邊區域1112大致為‘‘口，’字形， 其環繞第一產品區域Π11。第二區域112包括第二產品區 域11 21及環繞第二產品區域1121之第二週邊區域1122。 0 第三區域11 3包括第三產品區域11 31及環繞第三產品區域 1131之第三週邊區域1132。第四區域114包括第四產品 區域1141及環繞第四產品區域1141之第四週邊區域1142 。其中，第二產品區域1121、第三產品區域η 31及第四 產品區域1141之形狀及大小與第一產品區域11丨丨之形狀 及大小相同。第二週邊區域1122、第三週邊區域1132及 第四週邊區域1142之形狀及大小與第一週邊區域1112之 形狀及大小相同。 〇 [0013] 請一併參閱圖1及爾2，第二步，於金屬基板11 〇之第一表 面115上形成覆蓋第一區域in、第二區域112、第三區 域113及第四區域114之第一絕緣層120。第一絕緣層120 具有複數第一通孔121及複數第一對位孔122。 [00M] 複數第一通孔121開設之位置分別與第一產品區域mi、 第二產品區域1121、第三產品區域1131及第四產品區域 1141相對應，複數第一對位孔12 2開設之位置分別與第一 週邊區域1112、第二週邊區域1122、第三週邊區域丨132 及第四週邊區域1142相對應。第一通孔121之形狀及個數 099116969 表單編號A0101 第7頁/共31頁 nQ09i 201143567 可根據實際製作電路板需要進行設定。第一通孔121可為 圓形亦可為長方形，其亦可為其他形狀。本實施例中， 第一對位孔122為圓形孔。 [0015] 本實施例中，採用壓合覆蓋膜（c〇verlay)於第—表面 115上形成第一絕緣層120。於進行壓合之前，先於第一 絕緣層120内形成複數第一通孔121及複數第—對位孔 122。於第一絕緣層12〇與金屬基板11〇壓合之後，使得 與第一產品區域11 Π、第二產品區域1121、第三產品區 域1131及第四產品區域1丨41相對應之第一絕緣層i 2〇均 具有兩第一通孔121，其中一為方形通孔，一為圓形通孔 。並且，與第一產品區域111丨相對應之兩個第一通孔12^ 及與第二產品區域11 21相對應之兩個第一通孔121關於第 一區域111及第二區域112之分界線對稱設置，與第二產 品區域1121相對應之兩第一通孔121及與第三產品區域 1131相對應之兩第一通孔12ι關於第二區域112及第三區 域113之分界線對稱設置’與第三產品區域1131相對應之 兩第一通孔121及與第四產品區埤u41相對應之兩第一通 孔121關於第三區域丨丨3及第四區域114之分界線對稱設 置。與第一週邊區域1Π2、第二週邊區域1122、第三週 邊區域11 32及第四週邊區域丨丨42相對應之第一絕緣層 120均具有一個第一對位孔122。其中，第一週邊區域 1112相對應之第一對位孔122與第二週邊區域11 22相對 應之第一對位孔122關於第一區域111及第二區域112之 分界線對稱設置，與第二週邊區域1122相對應之第一對 位孔122及與第三週邊區域丨丨32相對應之第一對位孔丨22 099116969 表單編號Α0101 第8頁/共31頁 0992030146-0 201143567201143567 VI. Description of the Invention: [Technical Field] The present invention relates to the field of circuit board fabrication, and more particularly to a method of fabricating a multilayer circuit board having a conductive structure. [Previous technology #亍] [0002] With the advancement of science and technology, printed circuit boards have been widely used due to their high assembly density. For application of the board, see the literature Takahash i, A. Ook i, N. Naga i, A. Akahosh i, H. Mukoh, A. Waj ima, M. Res. Lab, High dens-ity multilayer pri.nted circuit Board for HITAC M-880 * IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 418-425. [0003] The fabrication of a multi-layer circuit board is usually made by lamination, that is, each inner circuit layer is sequentially formed, and then film is placed between the inner circuit layers and pressed into a whole, and then becomes a whole. The inner circuit board is drilled to form a through hole penetrating the plurality of inner layer lines, and then the through hole is plated to form a via hole, and finally the outer copper layer is etched to obtain the outermost layer, thereby obtaining a multilayer circuit. board. In the above manufacturing method, each of the inner layer layers is separately produced, so that when the layers are formed, the inner layer wiring layers are inconsistently inconsistent due to the difference in the manufacturing conditions, and it is difficult to accurately align the stitches when performing the pressing. During the through-hole plating process, a plating layer is also formed on the outer copper foil layer, so that the thickness of the outer copper foil layer is increased and the thickness of the plating layer is not uniform, and etching is incomplete or over-etched during the etching process. 099116969 Form No. A0101 Page 4 of 31 0992030146-0 201143567 The quality of the outer circuit. In addition, the through holes are usually formed by mechanical drilling or laser hole forming, and it is easy to leave a slag which is generated by the film or the insulating layer due to high temperature in the holes. In the through-hole plating process, the reliability of the via hole formed by the glue/chaguyi 13_ is poor. When the number of layers of the circuit board is large and the depth of the through hole is large, it is difficult for the electric ore solution to flow into the through hole when the electric clock is performed, resulting in poor conductivity of the via hole. SUMMARY OF THE INVENTION [0004] [0005] ❹ 099116969 In view of the above, it is necessary to provide a multilayer circuit board manufacturing method capable of ensuring good reliability of the formed interlayer structure. A method of fabricating a multilayer circuit board will be described below by way of example. A method for fabricating a multilayer circuit board, comprising the steps of: providing a metal substrate, wherein the metal substrate comprises a plurality of regions arranged in sequence, each region comprising a product region and a peripheral region surrounding the product region; the metal substrate having a first surface and a second surface; a first insulating layer is formed on the first surface, and a first through hole is formed in the tenth insulating layer corresponding to each product region; and the metal substrate is etched to make the plurality of product regions correspond to Forming a plurality of conductive lines, wherein a region of the plurality of conductive lines that needs to be turned on is exposed from the first through hole; and forming a second insulating layer on the second surface of the metal substrate, wherein each of the product regions is formed in the second insulating layer Having a second through hole, each of the first through holes corresponding to the first second through hole, wherein a region of the plurality of conductive lines that needs to be turned on is exposed from the second through hole; forming a first conduction in the first through hole The first conductive pillar protrudes from the first insulating layer, and the second conductive via is formed in the second via hole, and the second conductive pillar protrudes from the second insulating layer, thereby causing each The domain corresponds to form a circuit board area; and the plurality of circuit board areas are folded and pressed to make the form number Α0101, page 5/total 31 page 0992030146-0 201143567 [0007] [0008] [0009] [0011] The plurality of circuit board regions overlap each other and become a whole, and the first conductive pillars or the second conductive pillars in the adjacent circuit board regions are in contact with each other and the first conductive pillars are contacted between the adjacent conductive conductive lines and The second conductive posts are electrically connected to each other. Compared to the prior art, is the technical solution provided? The layer circuit board manufacturing method has the following advantages: First, in the process of manufacturing the circuit board, the layers of the circuit board are simultaneously fabricated to effectively avoid the problems of the layers/stacking of the obtained circuit board. Secondly, the interlayer conduction of the multilayer circuit board is not known to be conducted by drilling and electroplating, and the problem of poor interlayer communication communication due to conduction by the drilling and electroplating can be effectively avoided. [Embodiment] Hereinafter, a manufacturing method provided by the present technical solution will be further described with reference to the accompanying drawings and embodiments. The present invention provides a method for fabricating a multi-layer circuit board. The following is a description of the method for fabricating a four-layer circuit board. The method for fabricating the circuit board includes the following steps: Please refer to FIG. In one step, a metal substrate 110 is provided. The metal substrate spoon includes a first region U1, a second region 112, a third region 113, and a fourth region 114 which are sequentially arranged. The metal substrate 110 has a first surface n 5 and a second surface 1 ΐβ. The common substrate 110 may be a copper foil generally used for fabricating a flexible circuit board, which may be an electrolytic copper foil or a rolled steel foil. The metal substrate 11 can also be made of a metal having good electrical conductivity such as aluminum. In this embodiment, the 3 universal substrate 110 is elongated, along its length direction, including the first-order region 099116969, the form number Α0101, the sixth page, the total 31 pages, the 0992030146-0201143567 field 111, the second region 112, The third area 113 and the fourth area 114. The first region 111, the second region 112, the third region 113, and the fourth region 114 respectively correspond to four conductive layers of the four-layer circuit board to be fabricated. The first region 111 includes a first product region 1111 and a first peripheral region 丨 112 surrounding the first product region 1111. In this embodiment, the first product area 1111 is rectangular, and the first peripheral area 1112 is substantially a 'mouth' shape surrounding the first product area Π11. The second region 112 includes a second product region 11 21 and a second peripheral region 1122 surrounding the second product region 1121. The third region 11 3 includes a third product region 11 31 and a third peripheral region 1132 surrounding the third product region 1131. The fourth region 114 includes a fourth product region 1141 and a fourth peripheral region 1142 surrounding the fourth product region 1141. The shape and size of the second product region 1121, the third product region η 31, and the fourth product region 1141 are the same as the shape and size of the first product region 11丨丨. The shape and size of the second peripheral region 1122, the third peripheral region 1132, and the fourth peripheral region 1142 are the same as those of the first peripheral region 1112. [0013] Please refer to FIG. 1 and FIG. 2 together. In the second step, the first region in, the second region 112, the third region 113, and the fourth region 114 are formed on the first surface 115 of the metal substrate 11 . The first insulating layer 120. The first insulating layer 120 has a plurality of first via holes 121 and a plurality of first alignment holes 122. [00M] The positions of the plurality of first through holes 121 are respectively corresponding to the first product area mi, the second product area 1121, the third product area 1131, and the fourth product area 1141, and the plurality of first alignment holes 12 2 are opened. The positions correspond to the first peripheral region 1112, the second peripheral region 1122, the third peripheral region 丨132, and the fourth peripheral region 1142, respectively. The shape and number of the first through holes 121 099116969 Form No. A0101 Page 7 of 31 nQ09i 201143567 It can be set according to the actual production of the circuit board. The first through hole 121 may be circular or rectangular, and may have other shapes. In this embodiment, the first alignment hole 122 is a circular hole. [0015] In this embodiment, the first insulating layer 120 is formed on the first surface 115 by using a press-fit cover film. Before the pressing, a plurality of first through holes 121 and a plurality of first-aligning holes 122 are formed in the first insulating layer 120. After the first insulating layer 12 is pressed against the metal substrate 11 第一, the first insulation corresponding to the first product region 11 Π, the second product region 1121, the third product region 1131, and the fourth product region 1 丨 41 is caused. The layers i 2 〇 each have two first through holes 121 , one of which is a square through hole and one of which is a circular through hole. And, the two first through holes 12^ corresponding to the first product region 111丨 and the two first through holes 121 corresponding to the second product region 11 21 are divided into the first region 111 and the second region 112. The boundary line is symmetrically disposed, and the two first through holes 121 corresponding to the second product region 1121 and the two first through holes 12ι corresponding to the third product region 1131 are symmetrically disposed with respect to the boundary between the second region 112 and the third region 113. 'The two first through holes 121 corresponding to the third product region 1131 and the two first through holes 121 corresponding to the fourth product region 埤u41 are symmetrically arranged with respect to the boundary between the third region 丨丨3 and the fourth region 114 . The first insulating layer 120 corresponding to the first peripheral region 1, 2, the second peripheral region 1122, the third peripheral region 11 32, and the fourth peripheral region 丨丨 42 each has a first alignment hole 122. The first alignment hole 122 corresponding to the first peripheral region 1112 and the first alignment hole 122 corresponding to the second peripheral region 11 22 are symmetrically disposed with respect to the boundary between the first region 111 and the second region 112, and The first alignment hole 122 corresponding to the two peripheral regions 1122 and the first alignment hole 22 corresponding to the third peripheral region 丨丨32 22 099116969 Form No. 1010101 Page 8/Total 31 Page 0992030146-0 201143567
[0017][0017]
[0018] 關於第二區域112及第三區域113之分界線對稱設置，與 第三週邊區域1132相對應之第一對位孔122及與第四週邊 區域11 42相對應之第一對位孔122關於第三區域113及第 四區域114之分界線對稱設置。 [0016] 第一絕緣層120亦可藉由印刷液態絕緣材料之方式形成。 即藉由設置與第一通孔1 21及第一對位孔1 2 2對應圖案之 網版’於金屬基板110之第一表面115上印刷液態絕緣材 料形成。所採用液態絕緣材料應具有低吸濕性、良好之 尺寸穩定性及電絕緣性以及财化學藥品性能，所述之液 態絕緣材料可為液態聚醯亞胺（P〇lyimide)或者液晶 高分子材料（Liquid crystal polymer)。 請一併參閱圖1、圖3及圖4 ’第三步，對金屬基板11 〇進 <亍蚀刻’使付於第一產品區域1111内形成第一導電線路 130，於第二產品區域1121内形成第二導電線路,於 第二產品區域1131内形成第耳導電線路15〇，於第四產品 區域1141内形成第四導電線路160。 本實施例中，藉由影像轉移工藝及蝕刻工藝於金屬基板 110内製作第一導電線路130、第二導電線路140、第三 導電線路150及第四導電線路16〇，並且使得第一導電線 路130中需要導通之區域從與第一產品區域丨丨丨丨相對應之 第一通孔121露出，第二導電線路140中需要導通之區域 從與第二產品區域1121相對應之第一通孔κι露出，第三 導電線路150中需要導通之區域從與第三產品區域丨131相 對應之第一通孔121露出，第四導電線路wo中需要導通 之區域從與第四產品區域1141相對應之第一通孔κι露出 099116969 表單編號Α0101 第9頁/共31頁 0992030146-0 201143567 [0019] [0020] [0021] [0022] [0023] 第通孔1 21孔徑小於從其露出之導電線路之寬度。 於形成第一導電線路130、第二導電線路140、第三導電 線路150及第四導電線路16〇之同時，再於第一週邊區域 1112、第二週邊區域1122、第三週邊區域1132及第四週 邊區域1142分別形成一個第二對位孔17〇。每一個第二對 位孔170均與一個第一對位孔122正對連通。 為方便後續進行折疊方便，於蝕刻形成上述複數導電線 路之同時，亦可將位於相鄰相鄰區域之分界線處之金屬 基板110沿著所述分界線餘刻去除。 请一併參閱圖5及圖6，第四步’於金屬基板11 〇之第二表 面116形成第二絕緣層180，第二絕緣層18〇内具有複數 第二通孔181及複數第三對位孔182。複數第二通孔181 與複數第一通孔121 — 一對應。複數第三對位孔182與複 數第一對位孔1 7 0--對應正對連通。 本實施例，與形成第一絕緣層12〇相同之方法形成第二絕 緣層180，從而使得第一導電線路13〇、第二導電線路 140、第二導電線路150及第四導電線路需要導通之 區域亦從第二通孔181露出。 請一併參閱圖7，第五步，於第一通孔121内形成第一導 通柱123，於第二通孔181内形成第二導通柱183，第一 導通柱123部分凸出於第一絕緣層12〇，第二導通柱183 部分凸出於第二絕緣層18〇。 [0024] 099116969 本實施例中，採用印刷錫膏之方式形成第一導通柱123及 第二導通柱183 表單編號A0101 首先’採用鋼版印刷之方式於第一通孔 第丨〇 頁/共 31 頁 0992030146-0 201143567 Ο 121内形成第一導通柱123及第二導通柱183。第一絕緣 層120及第二絕緣層180為覆蓋膜，第一絕緣層120及第 二絕緣層180之厚度約為30微米。本實施例中採用之印刷 錫膏之鋼版之厚度約為1〇〇微米，印刷形成第一導通柱 123及第二導通柱183之高度大於第一通孔121及第二通 孔181之深度，從而第一導通柱123之一端與第一導電線 路130、第二導電線路140、第三導電線路150或第四導 電線路160相接觸’另一端凸出於第一通孔121，第二導 通柱183之一端與第一導電線路130、第二導電線路14〇 、第三導電線路150或第四導電線路16〇相接觸，另一端 凸出於第二通孔181。然後，對印刷形成之第一導通柱 123及第二導通柱183進行高溫重溶定型，使得第一導通 柱123充分填滿第一通孔121並凸出於第^通孔121，第 二導通柱183充分填滿第二通孔181並凸出於第二通孔 m。 [0025] 金屬基板110之第一區域1丨1及第一區域ln對應之第一 Ο 絕緣層120、第一區域in辫應之第二絕緣層18〇、第一 區域111對應之第一導通柱丨23及第一區域ln對應之第 二導通柱183共同構成第一電路板區域1〇1。金屬基板 110之第二區域112及第二區域112對應之第一絕緣層12〇 、第二區域112對應之第二絕緣層18〇、第二區域112對 應之第一導通柱123及第一區域n !對應之第二導通柱 183共同構成第二電路板區域1〇2。金屬基板u〇之第二 區域112及第二區域112對應之第一絕緣層12〇、第二區 域112對應之第二絕緣層18〇、第二區域112對應之第一 099116969 表單編號Α0101 第Π頁/共31頁 、 0992030146-0 201143567 導通柱123及第二區域112對應之第二導通柱183共同構 成第二電路板區域102。金屬基板ιι〇之第三區域H3及 第三區域113對應之第一絕緣層12〇、第三區域113對應 之第二絕緣層180、第三區域113對應之第一導通柱123 及第三區域113對應之第二導通柱183共同構成第三電路 板區域103。金屬基板no之第四區域114及第四區域114 對應之第一絕緣層120、第四區域114對應之第二絕緣層 180、第四區域114對應之第一導通柱丨23及第四區域114 對應之第二導通柱183共同構成第四電路板區域1〇4。 [0026] [0027] [0028] 請參閱圖8，第六步，根據預定之第一電路板區域1〇1、 第二電路板區域1〇2、第三電路板區域1〇3及第四電路板 區域104之折疊方式，選擇性地於第一電路板區域1〇1、 第二電路板區域102、第三電路板區域1〇3及第四電路板 區域104對應之第一絕緣層丨2〇及第二絕緣層18〇之表面 貼合膠層190，於膠層190内形成有第三通孔191。 第三通孔1 91與第一通孔1 21及第二通孔1 81相對應，並 且第一導通柱12 3及第二導通柱1 8 3從對應之第三通孔 191露出。膠層190可為環氧樹脂或者丙烯酸樹脂製成， 其可為低流膠量之半固化膠片。於未將膠層19〇貼合於第 一絕緣層120及第二絕緣層18〇表面之前，先於膠層19〇 中形成第三通孔191。 本實施例中’需要將第一電路板區域1〇1、第二電路板區 域102、第三電路板區域1〇3及第四電路板區域1〇4依次 堆疊，即，使得第一電路板區域1〇1對應之第二絕緣層 180與第一電路板區域對應之第二絕緣層180之表面 099116969 表單編號A0101 第12頁/共31頁 0992030146-0 201143567 相對，第一電路板區域1〇2之第一絕緣層120之表面與第 三電路板區域103對應之第-絕緣層12G之表面相對，第 -電路板區域103對應之第二絕緣層18〇與第四電路板區 °、 4之第一絕緣層相對。從而，於第一電路板區域 1 對應之第二絕緣層〗8〇之與第一產品區域丨丨〗丨相對應 之表面、第—電路板區域102對應之第一絕緣層120與第 一產。。區域1121相對應之表面、第三電路板區域1〇3對應 之第二絕緣層180之與第三產品區域1131相對應表面貼合 結膠層190。 Ο [0029] [0030] ❸ [0031] 099116969 當然’膠層190設置之位置不限於本實施例中設置之區域 ，只要於需要析疊後相對之第一絕緣層12〇之表面或第二 絕緣層180之表面之間設置有膠層19〇即可。 明參閱圖9,第七步，根據需要沿第一電路板區域1〇1、 第一電路板區域1〇2、第三電路板區域1〇3及第四電路板 區域104之間之分界線進行拆疊並壓合，使得第一電路板 區域101、第二電路板區域1&2、第三電路板區域103及 第四電路板區域1〇4成為一個整體，第一導電線路丨3〇、 第一導電線路140、第三導電線路15〇及第四導電線路 160藉由設置與它們之間之成為一體之第一導通柱123及 第一導通柱183相互導通，從而得到具有層間互連之多層 電路板100。 於進行折疊之過程中，需要對折疊之第一電路板區域1〇1 、第二電路板區域1〇2、第三電路板區域1〇3及第 四電路 板區域104進行對位元。本實施例中，藉由設置於第—電 路板區域1G1、第二電路板區域1Q2、第三電路板區域 表單蝙號A0101 第13頁/共3 、d丨頁 0992030146-0 201143567 103及第四電路板區域1〇4之第一對位孔122、第二對位 孔170、第三對位孔182進行對位。即折疊後使得位於 不同電路板區域之第-對位孔122、第二對域17〇及第 三對位孔182相互正對，從而使得位於第1路板區域 101 '第二電路板區域1〇2、第三電路板區域1〇3及第四 電路板區域104之第-導通柱123及第二導通柱183均相 互正對重疊。如當折疊第一電路板區域101及第二電路板 區域102使得第一電路板區域101之第二絕緣層18〇表面 與第二電路板區域102之第二絕緣層180表面相對時，則 需要將位元於第一電路板區域1〇1内之第_對位孔122、 第二對位孔170及第三對位孔182與第二電路板區域1〇2 内之第一對位孔122、第二對位孔170及第三對位孔182 相互正對。這樣’可保證第一電路板區域1〇1内之第一導 電線路130與第二電路板區域1〇2内之第二導電線路14〇 之間之對位關係’並且位於第一電路板區域丨〇1内之第一 導通柱123及第二導通柱183與位於第二電路板區域1〇2 内之第一導通柱123及第二導通柱痛3珣相互正對重疊。 於進行第一電路板區域101、第二電路板區域1〇2、第三 電路板區域103及第四電路板區域104之折疊時，可根據 實際製作之需要，採用不同之折疊方式，從而改變第一 電路板區域101、第二電路板區域102、第三電路板區域 103及第四電路板區域104之間之堆疊關係，獲得不同之 電路板。 [0032] 本實施例中’採用快壓機對折疊後之第一電路板區域101 、第二電路板區域102、第三電路板區域103及第四電路 099116969 表單編號A0101 第14頁/共31頁 0992030146-0 201143567 Ο [0033] 板區域104進行壓合。於進㈣合之職巾，對第—電路 板區域101、第二電路板區域1()2、第三電路板區域⑽ 及第四電路板區域1〇4加熱，使得第—電路板區域⑻、 第二電路板區域102、第三電路板區域1〇3及第四電路板 區域104中之第—導通柱123及第二導通柱183溶化，並 於壓力之作用下，使得相互正對接觸之第-導通柱123或 第二導通柱183均成為-體結構，從而第一導電線路13〇 、第二導電線路140、第三導電線路15〇及第四導電線路 160藉由設置與它們之間之成為—體之第一導通柱123及 第二導通柱183相互導通。 請參閱H1G，本實施例提供之電路板製作方法，還可包 括於得到電路板100之後’對電路板1〇〇進行成型處理。 I7藉由衝壓成型之方式，將電路板1〇〇中週邊區域對廡之 區域去除，而只將產品區域對應部分留下，從而得到滿 足客戶需求形狀之電路板。 ! . . .:丨； [0034] Ο . ·;; : ; 本技術方案提供之多層電冷板製作方法，具有如下優點 :首先，於進行電路板製作過程中，電路板之各層同時 製作，可有效之避免制得之電路板各層漲縮不一致之問 題。其次，多層電路板之層間導通不採用鑽孔及電鍍之 方式導通，從而可有效避免由於鑽孔及電鍍之方式導通 產生之層間導通信賴性差之問題。再次，由於電路板製 作採用純銅箱壓合絕緣層之方式，由於銅箔及絕緣層之 價格較背膠鋼箔低，可降低電路板之生產成本。 [0035] 099116969 综上所述’本發明確已符合發明專利之要件，遂依法提 出專利申請。惟 表單編號Α0101 以上所述者僅為本發明之較佳實施方 第15頁/共31頁 0992030146-0 201143567 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或變化 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0036] 圖1係本技術方案實施例提供金屬基板之示意圖。 [0037] 圖2係本技術方案實施例提供之於金屬基板表面形成第一 絕緣層後之示意圖。 [0038] 圖3係本技術方案實施例提供之金屬基板之第一表面形成 導電線路後之示意圖。 [0039] 圖4係圖3沿IV-IV線之剖面示意圖。 [0040] 圖5係本技術方案實施例提供之於金屬基板之第二表面形 成第二絕緣層後之示意圖。 [0041] 圖6係圖5沿VI - VI線之剖面示意圖。 [0042] 圖7係本技術方案實施例提供之第一通孔内形成第一導通 柱、第二通孔内形成第二導通柱後之示意圖。 [0043] 圖8係本技術方案實施例提供之於第一絕緣層及第二絕緣 層表面形成膠層後之示意圖。 [0044] 圖9係本技術方案實施例提供之複數電路板區域堆疊並壓 合後之示意圖。 [0045] 圖1 0係本技術方案實施例提供之複數電路板區域堆疊並 壓合後進行成型後之示意圖。 【主要元件符號說明】 099116969 表單編號A0101 第16頁/共31頁 0992030146-0 201143567 [0046] 電路板：100 [0047] 第一電路板區域：101 [0048] 第二電路板區域：102 [0049] 第三電路板區域：103 [0050] 第四電路板區域：104 [0051] 金屬基板：110 [0052] Ο 第一區域：111 [0053] 第一產品區域：1111 [0054] 第一週邊區域：1112 ' [0055] 第二區域：112 [0056] 第二產品區域：1121 ' [0057] 第二週邊區域：1122 [0058] Ο 第三區域：113 [0059] 第三產品區域：1131 [0060] 第三週邊區域：1132 [0061] 第四區域：114 [0062] 第四產品區域：1141 [0063] 第四週邊區域：1142 [0064] 第一表面：11 5 099116969 表單編號Α0101 第17頁/共31頁 0992030146-0 201143567 [0065] 第二 表面：11 6 [0066] 第一 絕緣層：120 [0067] 第一 通孔：121 [0068] 第一 對位孔：122 [0069] 第一 導通柱：123 [0070] 第一 導電線路：130 [0071] 第二 導電線路：140 [0072] 第三 導電線路：150 [0073] 第四導電線路：1 60 [0074] 第二對位孔：170 [0075] 第二 .絕緣層：180 [0076] 第二 .通孔：181 [0077] 第三 .對位孔：182 [0078] 第二 .導通柱：183 [0079] 膠層 ：190 [0080] 第三 .通孔：191 099116969 表單編號A0101 第18頁/共31頁 0992030146-0[0018] The boundary between the second region 112 and the third region 113 is symmetrically disposed, the first alignment hole 122 corresponding to the third peripheral region 1132 and the first alignment hole corresponding to the fourth peripheral region 11 42 122 is symmetrically arranged with respect to the boundary between the third region 113 and the fourth region 114. [0016] The first insulating layer 120 can also be formed by printing a liquid insulating material. That is, it is formed by printing a liquid insulating material on the first surface 115 of the metal substrate 110 by providing a screen plate having a pattern corresponding to the first through hole 1 21 and the first alignment hole 1 2 2 . The liquid insulating material used should have low hygroscopicity, good dimensional stability and electrical insulation, and chemical and chemical properties. The liquid insulating material can be liquid polyimine (P〇lyimide) or liquid crystal polymer material. (Liquid crystal polymer). Referring to FIG. 1 , FIG. 3 and FIG. 4 'the third step, the metal substrate 11 is further etched into the first product region 1111 to form the first conductive line 130 in the second product region 1121. A second conductive line is formed therein, and a first ear conductive line 15 is formed in the second product region 1131, and a fourth conductive line 160 is formed in the fourth product region 1141. In this embodiment, the first conductive line 130, the second conductive line 140, the third conductive line 150, and the fourth conductive line 16 are fabricated in the metal substrate 110 by an image transfer process and an etching process, and the first conductive line is made. The region in 130 that needs to be turned on is exposed from the first via hole 121 corresponding to the first product region ,, and the region in the second conductive trace 140 that needs to be turned on is from the first via hole corresponding to the second product region 1121. Κι exposed, the region of the third conductive line 150 that needs to be turned on is exposed from the first via hole 121 corresponding to the third product region 丨131, and the region of the fourth conductive trace wo that needs to be turned on corresponds to the fourth product region 1141. The first through hole κι exposes 099116969 Form No. 1010101 Page 9/Total 31 Page 0992030146-0 201143567 [0020] [0022] [0023] The through hole 1 21 has a smaller aperture than the conductive line exposed therefrom The width. After forming the first conductive line 130, the second conductive line 140, the third conductive line 150, and the fourth conductive line 16〇, the first peripheral area 1112, the second peripheral area 1122, the third peripheral area 1132, and the first The four peripheral regions 1142 respectively form a second alignment hole 17〇. Each of the second alignment holes 170 is in direct communication with a first alignment hole 122. In order to facilitate the subsequent folding, the metal substrate 110 located at the boundary line between adjacent adjacent regions may be removed along the boundary line while etching to form the plurality of conductive lines. Referring to FIG. 5 and FIG. 6 together, the fourth step is to form a second insulating layer 180 on the second surface 116 of the metal substrate 11 . The second insulating layer 18 has a plurality of second through holes 181 and a plurality of third pairs. Bit hole 182. The plurality of second through holes 181 are in one-to-one correspondence with the plurality of first through holes 121. The plurality of third alignment holes 182 are in communication with the plurality of first alignment holes 170--. In this embodiment, the second insulating layer 180 is formed in the same manner as the first insulating layer 12, so that the first conductive line 13, the second conductive line 140, the second conductive line 150, and the fourth conductive line need to be turned on. The area is also exposed from the second through hole 181. Referring to FIG. 7 and the fifth step, a first conductive pillar 123 is formed in the first through hole 121, and a second conductive pillar 183 is formed in the second through hole 181. The first conductive pillar 123 is partially protruded from the first conductive pillar 183. The insulating layer 12 is, and the second via 183 is partially protruded from the second insulating layer 18A. [0024] 099116969 In this embodiment, the first conductive pillar 123 and the second conductive pillar 183 are formed by printing solder paste. Form No. A0101 First, 'printing by steel plate on the first through hole page/total 31 Page 0992030146-0 201143567 The first via post 123 and the second via post 183 are formed in the crucible 121. The first insulating layer 120 and the second insulating layer 180 are cover films, and the first insulating layer 120 and the second insulating layer 180 have a thickness of about 30 μm. The thickness of the steel plate of the printing solder paste used in this embodiment is about 1 μm, and the height of the first conductive pillar 123 and the second conductive pillar 183 is greater than the depth of the first through hole 121 and the second through hole 181. Therefore, one end of the first conductive pillar 123 is in contact with the first conductive line 130, the second conductive line 140, the third conductive line 150 or the fourth conductive line 160. The other end protrudes from the first through hole 121, and the second conduction is performed. One end of the post 183 is in contact with the first conductive line 130, the second conductive line 14A, the third conductive line 150 or the fourth conductive line 16A, and the other end protrudes from the second through hole 181. Then, the first via post 123 and the second via post 183 formed by printing are subjected to high temperature re-smelting, so that the first via post 123 fully fills the first via hole 121 and protrudes from the first via hole 121, and the second conductive via is performed. The post 183 sufficiently fills the second through hole 181 and protrudes from the second through hole m. [0025] The first region 1丨1 of the metal substrate 110 and the first germanium insulating layer 120 corresponding to the first region ln, the first insulating layer 18〇 of the first region in the first region, and the first conductive region corresponding to the first region 111 The post 23 and the second via 183 corresponding to the first region ln together constitute a first circuit board region 1〇1. The first insulating layer 12A corresponding to the second region 112 and the second region 112 of the metal substrate 110, the second insulating layer 18〇 corresponding to the second region 112, the first conductive pillar 123 corresponding to the second region 112, and the first region The corresponding second conductive posts 183 together form a second circuit board area 1〇2. The first insulating layer 12 对应 corresponding to the second region 112 and the second region 112 of the metal substrate 〇, the second insulating layer 18 对应 corresponding to the second region 112 , and the first 099116969 corresponding to the second region 112 are Α 0101 Π Pages / 31 pages, 0992030146-0 201143567 The conductive posts 123 and the second conductive posts 183 corresponding to the second region 112 together form a second circuit board region 102. The first insulating layer 12 对应 corresponding to the third region H3 and the third region 113 of the metal substrate, the second insulating layer 180 corresponding to the third region 113, and the first conductive pillar 123 and the third region corresponding to the third region 113 The second conductive pillars 183 corresponding to 113 collectively constitute a third circuit board region 103. The first insulating layer 120 corresponding to the fourth region 114 and the fourth region 114 of the metal substrate no, the second insulating layer 180 corresponding to the fourth region 114, and the first conductive pillar 23 and the fourth region 114 corresponding to the fourth region 114 The corresponding second conductive posts 183 together form a fourth circuit board area 1〇4. [0028] Referring to FIG. 8, the sixth step is based on the predetermined first circuit board area 1〇1, the second circuit board area 1〇2, the third circuit board area 1〇3, and the fourth The circuit board area 104 is folded in a manner corresponding to the first insulating layer corresponding to the first circuit board area 1〇1, the second circuit board area 102, the third circuit board area 1〇3, and the fourth circuit board area 104. The surface of the second insulating layer 18 is bonded to the surface of the second insulating layer 18, and a third through hole 191 is formed in the adhesive layer 190. The third through hole 1 91 corresponds to the first through hole 1 21 and the second through hole 1 81, and the first conductive post 12 3 and the second conductive post 1 8 3 are exposed from the corresponding third through hole 191. The glue layer 190 may be made of epoxy resin or acrylic resin, which may be a low flow amount of semi-cured film. The third via hole 191 is formed in the adhesive layer 19A before the adhesive layer 19 is pasted on the surface of the first insulating layer 120 and the second insulating layer 18. In this embodiment, it is necessary to sequentially stack the first circuit board area 1〇1, the second circuit board area 102, the third circuit board area 1〇3, and the fourth circuit board area 1〇4, that is, to make the first circuit board The surface of the second insulating layer 180 corresponding to the first insulating layer 180 corresponding to the region 1〇1 is 099116969. Form No. A0101 Page 12/Total 31 Page 0992030146-0 201143567 In contrast, the first board area is 1〇 The surface of the first insulating layer 120 is opposite to the surface of the first insulating layer 12G corresponding to the third circuit board region 103, and the second insulating layer 18 and the fourth circuit board region corresponding to the first circuit board region 103 are 4 The first insulating layer is opposite. Therefore, the surface of the second insulating layer corresponding to the first circuit board region 1 corresponds to the surface of the first product region, the first insulating layer 120 corresponding to the first circuit board region 102, and the first production layer . . The surface corresponding to the region 1121 and the surface of the second insulating layer 180 corresponding to the third circuit board region 1〇3 are bonded to the surface of the third product region 1131. [0030] [0030] [991] 099116969 Of course, the position of the glue layer 190 is not limited to the area set in the embodiment, as long as the surface of the first insulating layer 12 or the second insulation is opposite after the deposition is required. A glue layer 19 〇 may be disposed between the surfaces of the layer 180. Referring to FIG. 9, the seventh step, along the boundary between the first circuit board area 1〇1, the first circuit board area 1〇2, the third circuit board area 1〇3, and the fourth circuit board area 104, as needed. Disassembling and pressing, so that the first circuit board area 101, the second circuit board area 1& 2, the third circuit board area 103, and the fourth circuit board area 1〇4 become a whole, and the first conductive path 丨3〇 The first conductive line 140, the third conductive line 15〇, and the fourth conductive line 160 are electrically connected to each other by providing a first conductive pillar 123 and a first conductive pillar 183 which are integrated with each other, thereby obtaining interlayer interconnection. The multilayer circuit board 100. In the process of folding, it is necessary to perform alignment on the folded first board area 1〇1, the second board area 1〇2, the third board area 1〇3, and the fourth board area 104. In this embodiment, by setting in the first circuit board area 1G1, the second circuit board area 1Q2, the third circuit board area form bat number A0101, page 13 / total 3, d page 0992030146-0 201143567 103 and fourth The first alignment hole 122, the second alignment hole 170, and the third alignment hole 182 of the circuit board region 1〇4 are aligned. That is, after folding, the first-alignment hole 122, the second pair of domains 17〇, and the third alignment hole 182 located in different circuit board regions are opposite to each other, so that the first circuit board region 101' is located in the second circuit board region 1 〇2, the third circuit board area 1〇3, and the first-conducting post 123 and the second conductive post 183 of the fourth circuit board area 104 are all overlapped with each other. If the first circuit board area 101 and the second circuit board area 102 are folded such that the second insulating layer 18 〇 surface of the first circuit board area 101 is opposite to the second insulating layer 180 surface of the second circuit board area 102, then The first aligning hole 122, the second aligning hole 170 and the third aligning hole 182 in the first circuit board area 1〇1 and the first aligning hole in the second circuit board area 1〇2 122. The second alignment hole 170 and the third alignment hole 182 are opposite to each other. This can ensure the alignment relationship between the first conductive line 130 in the first circuit board area 1〇1 and the second conductive line 14〇 in the second circuit board area 1〇2 and is located in the first circuit board area. The first via post 123 and the second via post 183 in the crucible 1 overlap the first via post 123 and the second via post pain in the second board region 1〇2. When the folding of the first circuit board area 101, the second circuit board area 1〇2, the third circuit board area 103, and the fourth circuit board area 104 is performed, different folding manners may be adopted according to actual production requirements, thereby changing The stacking relationship between the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit board area 104 obtains different circuit boards. [0032] In the present embodiment, the first circuit board area 101, the second circuit board area 102, the third circuit board area 103, and the fourth circuit 099116969 are folded using a quick press pair. Form No. A0101 Page 14 of 31 Page 0992030146-0 201143567 Ο [0033] The plate area 104 is pressed. In the fourth (4) joint towel, the first circuit board area 101, the second circuit board area 1 () 2, the third circuit board area (10) and the fourth circuit board area 1 〇 4 are heated, so that the first circuit board area (8) The second circuit board area 102, the third circuit board area 1〇3, and the first conductive pillar 123 and the second conductive pillar 183 of the fourth circuit board area 104 are melted, and under the action of pressure, the mutual contact is made. The first conductive pillar 123 or the second conductive pillar 183 is a body structure, so that the first conductive line 13〇, the second conductive line 140, the third conductive line 15〇, and the fourth conductive line 160 are disposed by The first conductive pillar 123 and the second conductive pillar 183 are electrically connected to each other. Please refer to the H1G, the circuit board manufacturing method provided in this embodiment, and the method for forming the circuit board 100 after the circuit board 100 is obtained. By means of stamping, the I7 removes the area of the peripheral area of the board 1〇〇, leaving only the corresponding part of the product area, thereby obtaining a circuit board that satisfies the shape of the customer. [0034] Ο . . . ; ; ; The multi-layer electric cold plate manufacturing method provided by the technical solution has the following advantages: First, in the process of manufacturing the circuit board, the layers of the circuit board are simultaneously produced, It can effectively avoid the problem of inconsistent expansion and contraction of each layer of the obtained circuit board. Secondly, the interlayer conduction of the multi-layer circuit board is not conducted by means of drilling and electroplating, so that the problem of poor communication between layers due to conduction by electroplating and electroplating can be effectively avoided. Thirdly, since the circuit board is made of a pure copper box and the insulating layer is pressed, since the price of the copper foil and the insulating layer is lower than that of the backed steel foil, the production cost of the circuit board can be reduced. [0035] 099116969 In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the form number Α0101 or above is only the preferred embodiment of the present invention. Page 15 of 31 0992030146-0 201143567, which cannot limit the scope of patent application in this case. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0036] FIG. 1 is a schematic view showing a metal substrate according to an embodiment of the present technical solution. 2 is a schematic view of the embodiment of the present invention after the first insulating layer is formed on the surface of the metal substrate. 3 is a schematic view showing a conductive line formed on a first surface of a metal substrate according to an embodiment of the present technical solution. 4 is a schematic cross-sectional view along line IV-IV of FIG. 3. 5 is a schematic view of the second embodiment of the metal substrate after the second insulating layer is formed on the second surface of the metal substrate. 6 is a schematic cross-sectional view taken along line VI-VI of FIG. 5. 7 is a schematic view showing a first via post formed in a first via hole and a second via post formed in a second via hole provided by an embodiment of the present technical solution. 8 is a schematic view of the first embodiment of the first insulating layer and the second insulating layer after forming a glue layer. [0044] FIG. 9 is a schematic diagram of a plurality of circuit board regions stacked and pressed according to an embodiment of the present technical solution. 10 is a schematic diagram of a plurality of circuit board regions provided by embodiments of the present technical solution stacked and pressed to form a shape. [Main component symbol description] 099116969 Form No. A0101 Page 16 of 31 0992030146-0 201143567 [0046] Circuit board: 100 [0047] First board area: 101 [0048] Second board area: 102 [0049] Third circuit board area: 103 [0050] Fourth circuit board area: 104 [0051] Metal substrate: 110 [0052] Ο First area: 111 [0053] First product area: 1111 [0054] First peripheral area :1112 ' [0055] Second area: 112 [0056] Second product area: 1121 '[0057] Second peripheral area: 1122 [0058] Ο Third area: 113 [0059] Third product area: 1131 [0060] Third Peripheral Area: 1132 [0061] Fourth Area: 114 [0062] Fourth Product Area: 1141 [0063] Fourth Peripheral Area: 1142 [0064] First Surface: 11 5 099116969 Form Number Α 0101 Page 17 / 31页 0992030146-0 201143567 [0065] Second surface: 11 6 [0066] First insulating layer: 120 [0067] First via: 121 [0068] First alignment hole: 122 [0069] First conduction Column: 123 [0070] First conductive line: 130 [0071] Second conductive line: 140 [0072] Third conductive line: 150 [0073] Fourth conductive line: 1 60 [0074] Second alignment hole: 170 [0075] Second. Insulation: 180 [0076] Second. Through hole: 181 [ 0077] Third. Registration hole: 182 [0078] Second. Conduction column: 183 [0079] Adhesive layer: 190 [0080] Third. Through hole: 191 099116969 Form No. A0101 Page 18 of 31 0992030146- 0