TWI388129B - All digital frequency synthesizer device - Google Patents

Description

Full digital frequency synthesizer

The present invention relates to a frequency synthesizing apparatus, and more particularly to an all-digital frequency synthesizing apparatus.

The frequency synthesizer is an important part of the communication system. It has also been widely used in system single-chip design. It is usually used in computer and communication systems, and with the continuous evolution of process technology, The trend in body circuit design has evolved toward system-on-a-chip, which has the advantage of making design more efficient, but it also increases design complexity and design considerations. In the prior art, a frequency synthesizing device using a flying adder circuit (refer to the prior art document [1]) must use a type of phase-locked loop plus a fast adder circuit, so the circuit must be integrated by means of mixing, however, Process conversion and system integration are not as convenient as full digital circuits.

Previous technical literature:

[1] L. Xiu, and Z. You, "A flying-adder architecture of frequency and phase synthesis with scalability," IEEE Trans. on VLSI Systems, vol. 10, no. 5, pp. 637-649, Oct. 2002.

The main object of the present invention is to provide a full digital frequency synthesizing device comprising a full digital phase locked loop, a delay string circuit and a fast adder circuit, the delay string circuit having N sequential serial connection delays The buffer, N is a positive integer greater than 1, wherein the first buffer is connected to the full digital phase locked loop, and the fast adder circuit is connected to the buffers of the delay string circuit. The full digital frequency synthesizing device of the present invention has the delay string circuit, and the full digital frequency synthesizing device locks a fixed frequency signal by using the full digital phase locked loop, and generates the same frequency and different phases through the delay string circuit. The signal is input to the flying adder circuit, so that all the circuit systems are implemented in a digital circuit, and can be quickly integrated with the system, and can quickly switch the required frequency signals for use in systems with different clocks.

Referring to FIG. 1 , which is a first preferred embodiment of the present invention, an all-digital frequency synthesizing device 100 includes an all-digital phase-locked loop 110 , a delay string circuit 120 , and a fly-fast adder circuit 130 . The digital phase-locked loop 110 includes a phase frequency detector (PFD), a phase search controller (PSC) connected to the phase frequency detector 111, and a phase search. The controller 112 is provided with a feedback digital-controlled oscillator 113 (FB_DCO), a frequency divider (FDIV) connected to the phase frequency detector 111 and the feedback digital control oscillator 113. And an output digital-controlled oscillator 115 (OUT_DCO) connected to the phase search controller 112, the delay string circuit 120 has N buffers 121 connected in series, and the N system is greater than 1 An integer, and the first buffer 121 is connected to the all-digital phase-locked loop 110. In this embodiment, the delay string circuit The first buffer 121 of the 120 is connected to the output digital control oscillator 115 of the full digital phase locked loop 110. The fast adder circuit 130 is connected to the buffers 121 of the delay string circuit 120.

Referring to FIG. 1 again, the full digital phase locked loop 110 is configured to control the output frequency signal reset according to an external reset signal (RESET), wherein the full digital phase locked loop 110 receives an external reference. The pulse signal 140 (CLK_IN) and an external frequency division control signal 150 (MOD) are used to control the generated one of the locked clock signal frequencies, and the delay string circuit 120 is provided as a required input signal, in this embodiment. The external reference clock signal 140 is received by the phase frequency detector 111 of the all-digital phase-locked loop 110, and the external frequency-dividing control signal 150 is the frequency divider 114 of the all-digital phase-locked loop 110. Receiving, please refer to FIG. 1 again, when the phase frequency detector 111 detects the difference between the frequency and phase of the external reference clock signal 140 and a feedback signal 116 (FB_CLK), the phase frequency detector 111, the first control signal 117a (UP), 117b (DOWN) is generated to the phase search controller 112, and the phase search controller 112 is based on the first control signals 117a of the phase frequency detector 111, 117b, using a binary search algorithm to produce a change The second control signal 118a (COARSE), 118b (FINE) for controlling the oscillation frequency of the oscillator 113, and the feedback digital control oscillator 113 switches the output according to the second control signals 118a, 118b. The oscillation frequency of the clock transmits a feedback signal 119 (CLK_FB_M) to the frequency divider 114. The frequency divider 114 receives the external frequency division control signal 150 and the feedback signal 119 and generates the feedback signal 116. The feedback signal 116 is fed back to the phase frequency detector 111. The above action is repeated until the phase frequency detector 111 cannot detect the source. The difference between the pulse and the feedback clock, that is, the lock state. Then, when the phase search controller 112 enters the locked state, it raises a lock signal 118c (LOCK) from the low level to a high level, and transmits the signal to the output digital control oscillator, and transmits the first The average and maximum control signal averages 118a', 118b' (AVG_COARSE, AVG_FINE) of the 64 reference periods of the two control signals 118a, 118b to the output digital control oscillator 115 and the output digital control oscillator 115 outputs an output Pulse frequency signal 160 (OUT_CLK), which has the effect of reducing the jitter of the output clock frequency signal 160. After that, when the output digital control oscillator 115 enters the locked state, if the phase frequency detector 111 detects that the feedback clock is different from the source clock, the above steps are repeated to adjust until the lock is again locked. .

Next, referring to FIG. 1 , the delay string circuit 120 receives the output clock frequency signal 160 generated by the full digital phase locked loop 110. After multiple phase delays, each of the buffers 121 generates a buffer. The clock signal 121a is a clock signal of the same frequency multiple phase to provide the fast adder circuit 130 as a required input signal. In this embodiment, the delay string The circuit 120 has 32 sequentially connected buffers 121. The first buffer 121 of the delay string circuit 120 is connected to the output digitally controlled oscillator 115 of the all-digital phase-locked loop 110.

Referring to FIGS. 1 and 2, the fast adder circuit 130 is coupled to the buffers 121 of the delay string circuit 120 to receive the buffer clocks generated by the buffers 121 of the delay string circuit 120. The signal 121a, the fast adder circuit 130 also receives an external input frequency control signal 170 (FCW) to control the synthesis of the buffer clock signals 121a. The frequency. Referring to FIG. 2 again, the flying adder circuit 130 has a first adder 131a, a first register 132a connected to the first adder 131a, and a second connected to the first register 132a. The register 132b, a first multiplexer 133a connected to the second register 132b, a second adder 131b connected to the first register 132a, and a third temporary connected to the second adder 131b The storage unit 132c, a fourth temporary storage unit 132d connected to the third temporary storage unit 132c, a second multiplexer 133b connected to the fourth temporary storage unit 132d, a first multiplexer 133a and the first The third multiplexer 133c of the second multiplexer 133b, a D-type flip-flop 134 connected to the third multiplexer 133c, and an inverter 135 connected to the D-type flip-flop 134 are in this embodiment. The first multiplexer 133a and the second multiplexer 133b are 32-to-1 multiplexers, the third multiplexer 133c is a 2-to-1 multiplexer, and the first multiplexer 133a and The second multiplexer 133b is connected to the buffers 121 of the delay string circuit 120.

Referring to FIG. 2 again, the fast adder circuit 130 receives the buffer clock signal 121a and an external input frequency control signal 170 (FCW) of the delay string circuit 120. In this embodiment, the external input The frequency control signal 170 can be divided into a first external input frequency control signal 171 (FCW1, FCW[9:0]) and a second external input frequency control signal 172 (FCW2, FCW[10:6]), and the The flying adder circuit 130 divides the circuit into two parts, a path A and a path B. The D-type flip-flop 134 of the flying fast adder circuit 130 is connected to the third multiplexer 133c, which utilizes a first clock. Signal 136 (CLK1) selects the signal to output path A or the signal of path B, where path A and path B are the same circuit, the main difference is that the number of bits of the adder used is different, in this embodiment The number of bits of the second adder 131b used by the path A The number of bits of the first adder 131a used by the path B is 10 bits, and the output of the first adder 131a and the second adder 131b is 32 to 1. The multiplexer selects an address signal for selecting the 32 signal lines (DCO[31:0] outputted by the delay string circuit 120, that is, the buffer clock signals 121a) to be transmitted to the first The signal of the three multiplexer 133c. The following describes the flow of path A and path B separately.

Path A: the second adder 131b receives the second external input frequency control signal 172 and the value output by the first register 132a (bit9~bit5) and the second adder 131b the second external The result of adding the input frequency control signal 172 and the value (bit9~bit5) is stored in the third temporary register 132c whose trigger source is a second clock signal 137 (CLK2), and waits for the next time when the second time The positive edge of the pulse signal 137 is triggered, and the value (bit9~bit5) is transmitted to the fourth register 132d whose trigger source is the first clock signal 136, and then waits for the next first clock signal 136. The edge triggers the fourth register 132d, and sends the value (bit9~bit5) of the fourth register 132d to the selected signal address of the second multiplexer 133b to select 32 signal lines to be output to The value of the third multiplexer 133c.

Path B: the first adder 131a receives the first external input frequency control signal 171 and a value (bit9~bit0) output by the first register 132a, and the first adder 131a the first external The result of adding the input frequency control signal 171 and the value (bit9~bit0) is stored in the first register 132a whose trigger source is the second clock signal 137, waiting for the next positive time of the second clock signal 137. Edge triggering, and then transmitting the value (bit9~bit5) to the trigger source is also the second temporary storage of the second clock signal 137 The device 132b finally waits for the positive edge trigger of the second clock signal 137, and then sends the value of the second register 132b to the selected signal address of the first multiplexer 133a to select 32 signals. The value to be output to the third multiplexer 133c.

Therefore, it can be seen that the reverse relationship between the first clock signal 136 and the second clock signal 137 achieves the interlocking function of the path A and the path B, so whether the second multiplexer 133b of the path A or The first multiplexer 133a of the path B selects a signal that is always a signal before half a cycle, and does not trigger a circuit output error due to a glitch that may be generated when the multiplexer selects a signal conversion (trigger) The operation of the frequency synthesis is incorrect, and the output of the second multiplexer 133b of the path A or the first multiplexer 133a of the path B is transmitted to the third multiplexer 133c, and the first time is utilized. The pulse signal 136 is selected to output the path A or the path B to trigger the D-type flip-flop 134 of the next stage to generate the desired frequency. Moreover, in the system operation, if the output frequency is to be changed, the external input frequency control signal 170 only needs to be externally changed, and the switching speed is extremely fast without re-locking. The full digital frequency synthesizing device 100 of the present invention has the delay string circuit 120, and the all-digital frequency synthesizing device 100 locks a fixed frequency signal by the full digital phase locked loop 110, and generates the delayed frequency circuit 120. Signals of different phases at the same frequency are input to the fast adder circuit 130, and the output of the multiplexer in the flyweight adder circuit 130 is selected by the external input frequency control signal 170 to trigger the D-type flip-flop 134 to generate a desired The output frequency signal does not need to re-lock the frequency, so all circuit systems can be implemented in digital circuits, so it can be quickly integrated with the system, and can quickly switch the required frequency signals for use in systems with different clocks.

In addition, please refer to Figures 3A and 3B. In order to demonstrate the superiority and feasibility of the present invention, it is implemented by a 0.18 μm 1P6M CMOS process provided by Taiwan Semiconductor Manufacturing Co., Ltd. Please refer to FIG. 3A again, which is the simulated situation, wherein the output clock frequency signal 160 is the frequency of the full digital phase locked loop 110 locked by 80 MHz, and the external input frequency is used to control the change of the signal 170. The frequency of the first clock signal 136 is the output of the full-digit frequency synthesizing device 100 using the flying adder circuit 130, and the synthesized frequency is converted from 39.38 MHz to 170 MHz. Please refer to FIG. 3B again. The output clock frequency signal 160 is input to the delay string circuit 120 to generate a multi-phase output clock waveform for use by the fly-fast adder circuit 130. The invention is realized by full digitization, is convenient for rapid integration with other systems, is applied to a single wafer of the system, and has the convenience of being immediately replaceable during process conversion.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧All-digit frequency synthesizer

110‧‧‧All digital phase-locked loop

111‧‧‧ phase frequency detector

112‧‧‧ Phase Search Controller

113‧‧‧Reward digital control oscillator

114‧‧‧Delephone

115‧‧‧Output digitally controlled oscillator

116‧‧‧Reward signal

117a, 117b‧‧‧ first control signal

118a, 118b‧‧‧ second control signal

Average of 118a’, 118b’‧‧‧ second control signals

118c‧‧‧Lock signal

119‧‧‧Reward signal

120‧‧‧Delay string circuit

121‧‧‧buffer

121a‧‧‧Buffer clock signal

130‧‧‧Fast Adder Circuit

131a‧‧‧First Adder

131b‧‧‧second adder

132a‧‧‧First register

132b‧‧‧Second register

132c‧‧‧ third register

132d‧‧‧fourth register

133a‧‧‧First multiplexer

133b‧‧‧Second multiplexer

133c‧‧‧ third multiplexer

134‧‧‧D type flip-flop

135‧‧‧Inverter

136‧‧‧First clock signal

137‧‧‧second clock signal

140‧‧‧External reference clock signal

150‧‧‧External frequency division control signal

160‧‧‧ Output clock frequency signal

170‧‧‧ External input frequency control signal

171‧‧‧First external input frequency control signal

172‧‧‧Second external input frequency control signal

Figure 1 is a flow chart of a full digital frequency synthesizing apparatus in accordance with a preferred embodiment of the present invention.

2 is a flow chart of the flyweight adder circuit of the full digital frequency synthesizing device in accordance with a preferred embodiment of the present invention.

3A and 3B are diagrams showing simulation results of a 0.18 μm 1P6M CMOS process provided by Taiwan Integrated Circuit Manufacturing Co., Ltd. according to a preferred embodiment of the present invention.

100‧‧‧All-digit frequency synthesizer

110‧‧‧All digital phase-locked loop

111‧‧‧ phase frequency detector

112‧‧‧ Phase Search Controller

113‧‧‧Reward digital control oscillator

114‧‧‧Delephone

115‧‧‧Output digitally controlled oscillator

116‧‧‧Reward signal

117a, 117b‧‧‧ first control signal

118a, 118b‧‧‧ second control signal

Average of 118a’, 118b’‧‧‧ second control signals

118c‧‧‧Lock signal

119‧‧‧Reward signal

120‧‧‧Delay string circuit

121‧‧‧buffer

121a‧‧‧Buffer clock signal

130‧‧‧Fast Adder Circuit

136‧‧‧First clock signal

137‧‧‧second clock signal

140‧‧‧External reference clock signal

150‧‧‧External frequency division control signal

160‧‧‧ Output clock frequency signal

170‧‧‧ External input frequency control signal

Claims (6)

An all-digital frequency synthesizing device comprising: at least: a full-digital phase-locked loop; a delay string circuit having N sequentially connected buffers, N-system being a positive integer greater than 1, wherein the first buffer The device is coupled to the full digital phase locked loop; and a fast adder circuit is coupled to the buffers of the delay string circuit. The full digital frequency synthesizing device according to claim 1, wherein the all-digital phase-locked loop comprises a phase frequency detector, a phase search controller connected to the phase frequency detector, and a phase connecting the phase a feedback control digital oscillator of the search controller, a frequency divider connected to the phase frequency detector and the feedback digital control oscillator, and an output digital control oscillator connected to the phase search controller, the delay string circuit The first buffer is coupled to the output digitally controlled oscillator of the full digital phase locked loop. The full digital frequency synthesizing device according to claim 1, wherein the flying adder circuit has a first adder, a first register connected to the first adder, and a first temporary connection a second temporary register of the memory, a first multiplexer connected to the second temporary register, a second adder connected to the first temporary register, and a third temporary storage connected to the second adder a fourth temporary register connected to the third temporary register, a second multiplexer connected to the fourth temporary register, a second multiplexer connected to the fourth temporary register, and a connection a first multiplexer and a third multiplexer of the second multiplexer, a D-type flip-flop connected to the third multiplexer, and an inverter connected to the D-type flip-flop. The full digital frequency synthesizing device according to claim 3, wherein The first multiplexer and the second multiplexer are 32-to-1 multiplexers. The full digital frequency synthesizing device according to claim 3, wherein the third multiplexer is a 2-to-1 multiplexer. The full digital frequency synthesizing device of claim 3, wherein the first multiplexer and the second multiplexer are connected to the buffers of the delay string circuit.