TWI388126B - Clock integrated circuit - Google Patents

Description

Clock circuit of integrated circuit (3)

The present invention relates to an integrated circuit having a clock circuit that can tolerate variations such as temperature, ground noise, power supply noise, and the like.

The operation of the clock circuit of the integrated circuit varies with factors such as temperature, ground noise, and power noise. Since these variations affect the final timing of the output clock signal, a number of studies have been conducted to address this problem, resulting in a more uniform output clock signal in the presence of the above variations.

For example, U.S. Patent No. 7,142,005 to Gabory uses the addition of active load snubber circuits, independent bias circuitry, and bias circuitry to isolate the effects of power fluctuations on the clock signal. In order to achieve the impact of isolated power fluctuations on the clock signal, these relatively complex snubber circuits result in a significant increase in die area and cost.

Therefore, there is a demand, and it is hoped that these variability problems can be solved, but with less complicated structure and less cost.

The present invention provides a technique of a device having a clocked integrated circuit.

The clock integrated circuit has a latch that generates a clock signal output of the clock integrated circuit. The latch includes an interactively coupled logic gate such that an output of the alternately coupled logic gate in the latch is coupled to an input of the alternately coupled logic gate in the latch.

The clock integrated circuit also has a timing circuit coupled to an output of the latch, an output of the sequential circuit switching between a first reference signal and a second reference signal, the rate of the switching being A temperature dependent time constant is determined. The output of the timing circuit determines the timing of the output of the clock signal.

The clock integrated circuit also has an inverting circuit that compares one of the output of the sequential circuit with a temperature compensation reference value, such that the timing of the clock signal output of the clock integrated circuit can withstand temperature fluctuations, and the inverting circuit An output is coupled to an input of the latch.

In some embodiments, the time constant is an exponential signal.

In some embodiments, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit is charged from the first reference voltage to the second reference voltage The state is switched between a state in which the second reference voltage is discharged to the first reference voltage.

In some embodiments, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit is responsive to the inverter circuit at the first reference voltage A state of charging to the second reference voltage is switched between a state of discharging from the second reference voltage to the first reference voltage. The temperature compensation trigger point of the inverter circuit is a third reference voltage, which decreases as the temperature increases. In one embodiment, the temperature compensation trigger point of the inverter circuit is generated by a temperature compensated power supply.

Another object of the present invention is to provide an apparatus having a clocked integrated circuit in which the inverter is replaced by a Schmitt trigger circuit.

It is still another object of the present invention to provide an apparatus having a clocked integrated circuit in which an inverter is replaced by an operational amplifier circuit and a current generator type reference circuit is added to generate the temperature compensated reference value.

In many different embodiments, the current generator type reference circuit is a current generator and a resistance characteristic device comprising any one of a resistor, a diode, and a MOS transistor; and some other The device is a device having at least one of CTAT (inverse temperature to temperature) characteristics and PTAT (for proportional to temperature) characteristics.

It is still another object of the present invention to provide an apparatus having a clocked integrated circuit including a latch to generate a clock signal output of the clocked integrated circuit. The latch includes a first logic gate and a second logic gate coupled to each other. One of the first logic gate outputs is coupled to a first input of the second logic gate. One of the second logic gate outputs is coupled to a first input of the first logic gate. The output of the second logic gate and the second input of the first logic gate are coupled via at least a first timing circuit and a first inverter. The output of the first logic gate and the second input of the second logic gate are coupled via at least a second timing circuit and a second inverter.

The first sequential circuit has an output that is switched between a first reference signal and a second reference signal at a first rate, the first rate being determined by a temperature dependent first time constant.

The second sequential circuit has an output that is switched between the first reference signal and the second reference signal at a second rate, the second rate being determined by a temperature dependent second time constant.

The outputs of the first sequential circuit and the second sequential circuit determine the timing of the output of the clock signal.

The first inverter compares an output of the first sequential circuit with a first temperature compensation reference value, which is a first temperature compensation trigger point of the first inverter.

The second inverter compares one of the output of the second sequential circuit with a second temperature compensation reference value, which is a second temperature compensation trigger point of the second inverter.

In an embodiment, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the first sequential circuit and the second sequential circuit are from the first reference voltage A state of charging to the second reference voltage is switched between a state of discharging from the second reference voltage to the first reference voltage. In an embodiment, the temperature compensation reference values are a third reference voltage that decreases as the temperature increases.

In an embodiment, the first and second time constants are an exponential signal.

In an embodiment, the first and second temperature compensation reference values are generated from a common reference circuit.

In an embodiment, the first and second temperature compensation reference values are generated from different reference circuits.

Another object of the present invention is to provide an apparatus having a clocked integrated circuit in which an array inverter is replaced by an array Schmitt trigger circuit.

Another object of the present invention is to provide an apparatus having a clocked integrated circuit in which an arrayed inverter is replaced by an array operational amplifier circuit and a current generator type reference circuit is added to generate the temperature compensated reference value.

Figure 1 shows a block diagram of an integrated circuit clock circuit having, for example, temperature, ground voltage, or power supply voltage variation tolerance.

The integrated circuit clock circuit is usually a one-loop structure, and has a sequential circuit 102, a level switching circuit 104, and a latch circuit latch circuit 106. The latch circuit latch circuit 106 generates a feedback signal from the latch circuit latch circuit 106 to the timing circuit 102 and a clock output signal 110. The timing circuit 102 switches between two reference signals in accordance with a time constant. This time constant thus determines the timing of the integrated circuit clock circuit. A typical time constant example is an exponential time constant that characterizes the rise and fall times of an RC circuit or RL circuit. This level switching circuit monitors the output of the timing circuit 102 and changes its output depending on whether the timing circuit 102 is sufficiently high or low. Examples of the latch circuit 106 are an SR latch, an SR NAND latch, a JK latch, a gate SR latch, a gate D latch, a gate trigger latch, and the like. The latch circuit circuit 106 has two stable states and switches between the two stable states to generate a clock output signal 110.

The two reference signals on which the timing circuit 102 is dependent are generated by the circuit 116, which also produces a level switching reference signal upon which the level switching circuit 104 depends. The circuit 116 can be reduced to the reference signal on which the sequential circuit 102 depends and the level switching circuit 104 by generating the dependent reference signal for the sequential circuit 102 and generating the dependent level switching reference signal for the level switching circuit 104. The level of the noise of the noise signal shared by the reference signal is switched by the reference level. Because the phase of any noise is small, the peak value of the noise signal in the reference signal and the peak value of the noise signal in the reference switching signal of the level switching system 104 and the level switching circuit 104 are dependent on Valley value synchronization.

The level switching reference signal 112 on which the level switching circuit 104 depends is selected by the circuit 118 to couple it to the level switching circuit 104. In some embodiments, this will hold the ground noise as a sample, so the same ground noise will be held by the timing circuit 102 and will be referenced by the level switching reference circuit on which the level switching circuit 104 depends. Maintain.

Although the block diagram shown herein can address temperature, ground voltage, or supply voltage variations, an improved clock circuit in various embodiments of the present invention addresses only one of these varying parameters (eg, only for temperature). Noise, only for ground voltage noise or only for supply voltage noise), or two of these variations (for example: temperature and supply voltage noise only, temperature and ground voltage noise only or It is only for power supply voltage and ground voltage noise).

Figures 2A and 2B show a circuit diagram of an integrated circuit clock circuit with tolerance to temperature variations, including an inverting circuit to evaluate the output of the sequential circuit.

The sequence shows parallel placed timing circuits 202A and 202B, parallel placed inverting circuits 204A and 204B, and a latch circuit 206. The timing circuits 202A and 202B are typically an inverter having a resistor RX or RY that is charged or discharged from a capacitor CX or CY to change the output voltage of OX or OY.

Figure 2A shows an embodiment in which the capacitor CX or CY is coupled to a common ground. Although not all possible variations are explicitly illustrated in the drawings, the techniques of the present invention include sequential circuits having capacitors CX or CY in all embodiments, wherein the timing circuits can be modified to couple capacitors CX or CY to a common ground.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor having opposite ends that are decoupled from the common ground of the inverter.

Figure 2B shows an embodiment in which the capacitor CX or CY is coupled to a common power source. Although not all possible variations are shown in the drawings, the techniques of the present invention include a sequential circuit having capacitors CX or CY in all embodiments, wherein the timing circuit can be modified to couple the capacitor CX or CY to a common power source.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor having opposite ends that are decoupled from the common supply terminal of the inverter.

The inverter circuits 204A and 204B are driven by a CTAT power supply or a power supply that is inversely proportional to temperature, which decreases as the temperature increases.

This inverter is quite different from the op amp version. In the op amp version, a Vref is compared to the output of the sequential circuit (such as the rise/fall of the RC circuit). In the inverter version, the power supply of the inverter is controlled to change the stroke of the inverter and thus the output of the sequential circuit (such as the rise/fall of the RC circuit). In this inverter version, an additional temperature relationship regarding the power supply and inverter travel is taken into account.

This inverter has the following advantages over the op amp version: (1) lower operating voltage VDD; (2) smaller circuit size (inverter has only two MOS transistors and op amp has Five or more MOS transistors); (3) simpler design; (4) lower active current (inverter has one current path, and op amp has two or three current paths and contains An additional current mirror); and (5) a higher operating speed (the inverter has a phase delay and the op amp has two or three phase delays).

The latch circuit 206 is alternately coupled such that the output of one logic gate is coupled to the input of another logic gate. One input of a logic gate is directly coupled to the output of another logic gate. The other input of the logic gate is directly coupled to the output of another logic gate via a timing circuit and a level detection circuit.

Figure 2C shows another embodiment of a sequential circuit. Although mostly similar to FIG. 2A, the sequential circuits 202A and 202B placed in parallel in FIG. 2C are driven by a PTAT power supply or a power supply proportional to temperature, which increases as the temperature increases. Although not all possible variations are shown in the drawings, the techniques of the present invention include sequential circuits having CTAT power supplies in all embodiments, where the CTAT power supply can be replaced by a PTAT power supply.

Similarly, although not all possible variations are shown in the drawings, the techniques of the present invention include sequential circuits having PTAT power supplies in all embodiments, where the PTAT power supply can be replaced by a CTAT power supply.

Figure 2D shows a circuit schematic of an integrated circuit clock circuit with tolerance to temperature variations, including a Schmitt trigger circuit to evaluate the output of the sequential circuit.

Although similar to FIG. 2B, the Schmitt trigger circuit of the level switching circuits 210A and 210B in FIG. 2D is driven by a CTAT power supply and includes an operational amplifier having a closed loop through the resistor.

Figure 2E shows a schematic of a Schmitt trigger circuit.

Figure 3 shows a circuit diagram of an integrated circuit clock circuit with tolerance to temperature variations, including an operational amplifier circuit for performing level detection of the output of the sequential circuit by comparing the output with a reference value.

Parallelly placed sequential circuits 302A and 302B, parallel placed level switching circuits 304A and 304B, and a latch circuit 306 are shown. The level switching circuits 304A and 304B are an operational amplification comparator having a reference voltage CTAT_REF. In addition, this clock circuit is roughly similar to FIG. 2A.

Fig. 4A is a circuit diagram showing a reference signal of a level detecting circuit including a current source having an increased current output as temperature increases.

Figure 4A shows how the CTAT power signal is dependent on the level detection circuit, shown as CTAT_REF 428 in this figure. A quantized PTAT_I current source 426 will generate a current proportional to temperature from the power regulator 422 via the resistor RES 424, which increases as the temperature increases. This power regulator 422 outputs a constant voltage independent of temperature. This regulated power supply provides a certain amount of power and does not change with VDD and temperature. For example, the output of this regulator has a band reference value. This output is inversely proportional to temperature because the voltage drop across this resistance increases as the temperature increases, and the offset at the output end of the lower end of the voltage drop is reduced. An example of this current source is shown in Figure 4E.

Figure 4B is a variation of the circuit of Figure 4A, wherein the PTAT_I constant current source 426 is replaced by the CTAT_I constant current source 430, and the CTAT_REF 428 of the CTAT power supply signal dependent on the level detection circuit is controlled by the PTAT of the level-dependent detection circuit. The power signal is replaced by PTAT_REF 432. An example of this current source is shown in Figure 4G.

Figure 4C is a variation of the circuit of Figure 4A with a bypass capacitor 434 in parallel with resistor RES 424 to reduce noise. In addition, this current source includes a current mirror. An example of this current source is shown in Figure 4D.

Figure 4D is a schematic diagram of a current generator that provides PTAT current from a PMOS device in accordance with a reference circuit.

Figure 4E is a schematic diagram of a current generator that provides PTAT current from an NMOS device in accordance with a reference circuit.

In Figures 4D and 4E, this circuit uses two delta_Vgs of the same current NMOS transistor with a temperature proportional to temperature. So delta_Vg/resistance = PTAT_I. In the 4Dth and 4Eth drawings, the two transistors having a circle are the same.

Figure 4F is a schematic diagram of a current generator that provides CTAT current from a PMOS device in accordance with a reference circuit.

Figure 4G is a schematic diagram of a current generator that provides CTAT current from an NMOS device in accordance with a reference circuit.

A current generator according to the reference circuit described herein is preferred because in many embodiments a single temperature dependent parameter can be controlled instead of two temperature dependent material related parameters, which have different Temperature correlation.

Figure 5A is a circuit diagram showing a reference signal of a level detecting circuit including a current source having a reduced current output as temperature increases.

Figure 5A shows how the CTAT power signal is dependent on the level detection circuit, shown as CTAT_REF 528 in this figure. A quantized PTAT_I current source 526, from the power regulator 522 via the resistor RES 524, produces a current that is inversely proportional to temperature and decreases as the temperature increases. This output is inversely proportional to temperature because the voltage drop across this resistor is also reduced as the temperature increases, and the offset of the output end of the upper end of the voltage drop is also reduced.

One example of the current source shown is a stacked current source.

Figures 5B, 5C, 5D, and 5E are other examples of generating a reference voltage signal.

Figure 5B is a variation of the circuit of Figure 5A, wherein the CTAT_I constant current source 526 is replaced by the PTAT_I constant current source 530, and the CTAT_REF 528 of the CTAT power supply signal dependent on the level detection circuit is controlled by the PTAT of the level-dependent detection circuit. The power signal is replaced by PTAT_REF 532.

Figure 5C is a variation of the circuit of Figure 5A in which the resistor RES 524 is replaced by a diode DI0 530. An example of this current source is shown in Figure 4F.

Figure 5D is a variation of the circuit of Figure 5A, in which the CTAT_I constant current source 526 is replaced by the PTAT_I constant current source 530, and the offset of the output terminal is shifted from the voltage drop across the upper end of the constant current source to across the constant current. The pressure drop at the lower end of the source.

Figure 5E is a variation of the circuit of Figure 5C in which the CTAT_I constant current source 526 is replaced by a resistor RES 524.

Figure 6A shows a set of time-to-size trajectory curves showing how this clock circuit has temperature variation tolerance, and its resulting clock timing can vary greatly with temperature.

Figure 6A shows a trajectory interval for a high temperature, a low temperature, and a medium temperature. The lower the temperature, the faster the timing circuit becomes, and the higher the temperature, the slower the timing circuit becomes. Because of the common reference signal of the sequential circuits, this sequential circuit will reach the reference value faster at low temperatures than at high temperatures. Therefore, the timing of this clock circuit will be faster at low temperatures than at high temperatures.

Figure 6B shows a set of time-to-size trajectory curves showing how this clock circuit has temperature variation tolerance because the circuit shown in Figures 2 through 5 produces clock timing that is essentially not temperature dependent. Change with change.

Figure 6B shows a trajectory interval for a high temperature, a low temperature, and a medium temperature. As shown in Fig. 6A, the lower the temperature, the faster the timing circuit becomes, and the higher the temperature, the slower the timing circuit becomes. However, since the different sequential circuits are used in FIG. 6B, they are different from the sequential circuits used in FIG. 6A. Although the sequential circuit will reach the reference value faster than at high temperatures at low temperatures, the reference value of this sequential circuit is relatively higher. Therefore, the timing of this clock circuit shows a small temperature variation, but causes the speed of the clock circuit to fluctuate.

Figures 7A and 7B are other embodiments showing the falling signal instead of the rising signal in Figures 6A and 6B, but still showing the same time constant.

A clock signal is dependent on the rising signal in Figures 6A and 6B or the falling signal in Figures 7A and 7B, depending on whether the capacitance CX or CY is coupled to the ground in Figure 2A or in Figure 2B. Power supply depends.

8A and 8B are circuit diagrams showing an integrated circuit clock circuit having a capability to withstand ground noise fluctuations, including a transistor selectively coupled to ground noise to serve as a level detector for the output of the sequential circuit. Part of the reference signal measured.

Parallelly placed sequential circuits 802A and 802B, parallel placed level switching circuits 804A and 804B, and a latch circuit 806 are shown. The level switching circuits 804A and 804B are selectively coupled to ground noise from the level switching reference circuits 816A and 816B, and stored in the capacitor node REF X or REF Y, respectively, according to the switching enabled by the signal ENX. The switching behavior of transistor 818A and switching transistor 818B turned on by signal ENY is determined. This will hold the ground noise as a sample, so the same ground noise will be held by the timing circuit 802A or 802B, and the node REF X of the reference switching circuit will be switched by the level switching circuit 104. It is held by REF Y.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor having opposite ends that are decoupled from the common supply terminal, the common supply being coupled to RX or RY.

The OX remains grounded when ENX is high. After that, ENX turns to the low level to turn off the NMOS; at this point the ground noise is held at OX. If the noise is high level, the pre-charging speed is very fast; if the noise is low level, the pre-charging speed is very slow. This circuit allows REFX or REFY to maintain the same ground noise at the same time.

In Figure 8A, the switching reference circuit references node REFX or REFY, including the capacitive circuit coupled to ground. In FIG. 8B, the switching reference circuit is referenced to node REFX or REFY, and includes a capacitor circuit coupled to the power source.

In various embodiments, the level shift reference circuits 816A and 816B can be two different sets of circuits or the same set of circuits shared by the parallel placed timing circuits and the multi-level switching circuits 804A and 804B.

Figure 9 is a plot of voltage vs. time showing how the clock circuit has the ability to withstand ground noise variations, and the clock timing that can be generated can vary greatly with respect to ground noise that changes over time.

Figure 9 shows how the traces OX and OY are affected by ground noise, which is affected by the REF_LO signal in this figure. When the ground noise has a peak, the timing circuit will start charging from REF_LO to REF_HI, causing the timing circuit to charge from REF_LO to REF_HI in less time. Therefore, this clock signal output 910 has a wide variation in this clock cycle.

When ENX is high, OX remains grounded and the voltage varies with ground noise. When ENX is low and the NMOS is turned off, the ground noise is held at OX. However, the reference level still varies with ground noise. In the worst case, OX maintains a high level of ground noise and the reference circuit is subjected to a negative ground level during charging; this reference value will be much lower than expected. Therefore a similar sample and hold structure maintains the same ground noise in REFX or REFY.

Figure 10 is a set of voltage vs. time graphs showing how the clock circuit has the ability to withstand ground noise variations. Because of the circuit in Figure 8, the ground noise can be changed over time. A relatively stable clock timing is generated.

Figure 10 shows how the traces OX and OY are affected by ground noise, which is affected by the REF_LO signal in this figure. When the ground noise has a peak or other change, the peak or other changes are stored in the capacitor node REF X or REF Y in Figure 8. Because the influence of ground noise on the REF_LO signal is tracked by the reference circuit after sampling, the level detection circuit is the same ground noise as the self-alignment detection reference circuit and the sequential circuit. After the ground noise is sampled and held, the ground noise will continue to change and the coupling will be decoupled. Therefore, this timing circuit does not start from the REF_LO charging to REF_HI program. Although there is ground noise, this sequential circuit still needs the same time to charge from REF_LO to REF_HI. Thus, this clock signal output 910 still has the same clock cycle under a widely varying ground noise.

In another embodiment, the ground noise is sampled and then the ground noise is decoupled from the sampling circuit during discharge, instead of being grounded during charging as shown in FIGS. 9 and 10. The noise is uncoupled from the sampling circuit. This embodiment poses an additional problem because the power supply noise problem generated by the self-noise power conditioner must be resolved.

In another embodiment (similar to Figure 2C), the sample and hold circuit maintains power supply noise rather than ground noise.

11A and 11B are circuit diagrams showing an integrated circuit clock circuit having power supply noise tolerance capability, including a power supply for the transistor and the timing circuit power supply, and a reference signal for the level detection of the output of the sequential circuit. The power noise shared the noise phase.

Parallelly placed sequential circuits 1102A and 1102B, parallel placed level switching circuits 1104A and 1104B, and a latch circuit 1106 are shown. As shown, the timing power supply and level switching reference value generators 1116A and 1116B are also included, which generate the same power noise as the power supply noise of the timing circuit power supply and the reference signal of the timing circuit output. Phase of the signal.

In Fig. 11A, the capacitor circuit CX or CY is coupled to ground. In FIG. 11B, the capacitor circuit CX or CY is coupled to the power source 1116A or 1116B.

Figure 12 shows a circuit diagram of a power supply circuit that shares the same noise phase as the power supply noise of the timing circuit power supply and the power supply noise of the reference signal of the timing circuit output.

Figure 12 shows a power supply 1236 for driving an operational amplifier 1232. This operational amplifier has a reference signal REF_OP 1234 at its non-inverting input. An example of this REF_OP 1234 is a bandgap reference circuit at 1.3V. A MOS field effect transistor 1238 has a logic gate coupled to the output of the operational amplifier 1232, a drain coupled to the power supply 1236, and a source coupled to the timing power output 1246. The timing power supply output 1246 and the level switching reference value 1248 are separated by a resistor R1 1240. The level switching reference value 1248 and the negative feedback point of the operational amplifier 1232 are separated by a resistor R2 1242. Finally, resistor R3 couples this negative feedback point to ground.

Another embodiment uses the capacitive coupling of the floating node to maintain the same noise phase between the timing power supply output 1246 and the level switching reference value 1248, wherein one of the timing power supply output 1246 and the level switching reference value 1248 is floating. of.

Although the above embodiment is specifically designed to maintain the same noise phase between the timing power supply output 1246 and the level switching reference value 1248, this is not the case in other designs. In other designs, the timing power supply output 1246 and the level switching reference value 1248 have different noise phases for one or more of the following reasons: (1) because the configuration of the die makes the reference circuit not close to the sequential circuit (2) The reference circuit in the regulator has a power supply rejection ratio (PSRR) better than the VDD power supply; and (3) even the RC power supply has a power regulator because of different output loads and transitions, a noise phase The difference will still be maintained and the power regulator must support large currents and large output transitions.

Figure 13 is a set of voltage vs. time graphs showing how the timing circuit power supply and the reference signal used for the level detection of the output of the sequential circuit are compared between the timing signals as shown in Fig. 11 or Fig. 12. Have the same noise phase.

Figure 13 shows that the power supply noise between the sequential circuit power supply 1301 and the reference signal used for the level detection of the sequential circuit output 1302 has the same noise phase. Placing the track 1303 over the tracks 1301 and 1302 can indicate that although the size of the power supply noise is changed, the peaks and valleys of the power supply noise of the tracks 1301 and 1302 are synchronized.

Figure 14 is a plot of voltage vs. time showing how this clock circuit has the ability to withstand power supply noise fluctuations, which can generate clock timing in power supply noise that changes significantly over time.

Figure 14 shows how the traces OX and OY are affected by the power supply noise 1401. When there is a large drop in power supply noise, the timing circuit begins to charge from REF_LO to REF_HI, causing the sequential circuit to charge from REF_LO to REF_HI in less time. Similarly, when the power supply noise has a peak, the program that charges the REF_LO from REF_LO to REF_HI becomes slower, causing the timing circuit to take more time to charge from REF_LO to REF_HI. These changes occur after switching the reference value from a stable (fixed) level. Therefore, this clock signal output 1410 has a wide variation in this clock cycle.

Figure 15 is a set of voltage vs. time graphs showing how the clock circuit has the ability to withstand power supply noise fluctuations, which can be significantly greater over time due to the circuits in Figures 11 and 12. A relatively stable clock timing is produced in the changed power supply noise.

Figure 15 shows how the trajectories OX and OY are affected by ground noise 1401. Different from the 14th figure, when the power supply noise 1501 has a peak or other changes, the reference switching reference value may have a synchronous peak or other variation. Although this peak or other variation has a smaller size in this level switching reference value compared to the power supply noise, the synchronization characteristic between the sequential circuit power supply 1501 and the level switching reference value greatly reduces the clock. Signal changes. Therefore, the clock signal output 1510 still has a common clock period in the case where the ground noise has a wide variation.

Figures 16A and 16B show a circuit diagram of an integrated circuit clock circuit with power supply noise tolerance to switch the power of this clock. When the power is turned on, if the stable power has not been reached and the VDD power is needed to generate a clock to the logic circuit. The logic circuit will wait for the set time of the stable power supply. When a stable power supply is reached, the clock switches to a stable clock.

Parallelly placed sequential circuits 1602A and 1602B, parallel placed level switching circuits 1604A and 1604B, and a latch circuit 1606 are shown. The figure also includes timing power supply and level switching reference value generators 1616A and 1616B, which generate the same power noise as the power supply noise of the timing circuit power supply and the reference signal of the timing circuit output. Phase of the signal. The switch also includes a switch 1620A between the VDD and the timing power supply and the level switching reference value generator 1616A, and a switch 1620B between the VDD and the timing power supply and the level switching reference value generator 1616B. A switch 1620C between the level switching circuit 1604A and the latch circuit 1606, and a switch 1620D between the level switching circuit 1604B and the latch circuit 1606.

In Fig. 16A, the capacitor circuit CX or CY is coupled to ground. In FIG. 16B, the capacitor circuit CX or CY is coupled to the power source 1616A or 1616B.

Figure 17 is a block diagram showing a memory circuit of the present invention having an improved integrated circuit clock circuit.

Figure 17 is a schematic block diagram of an integrated circuit 1700 including a memory array 1712. A word line/block selection decoder and driver 1714 are coupled to, and have electrical communication therewith, a plurality of word line lines 1716 and a string selection line arranged along the column direction of the memory cell array 1712. A one-line (row) decoder 1718 is coupled to the plurality of bit lines 1720 arranged along the row of the memory array 1712, and has electrical communication therewith for self-reading data or writing data to , memory cell array 1712 in the memory cell. The address is provided through bus bar 1722 to word line and block select decoder 1714 and bit line decoder 1718. The sense amplifier and data input structures in block 1724, including current sources as read, program, and erase modes, are coupled to bit line decoder 1718 via bus bar 1726. The data is transferred from the input/output port on the integrated circuit 1710 through the data input line 1728 to the data input structure of block 1724. In the illustrated embodiment, other circuits 1730 are also included in the integrated circuit 1710, such as a general purpose processor or special purpose circuit, or a combination module supported by the memory array to provide a single wafer system function. The data is transmitted by the sense amplifier in block 1724, through data output line 1732, to the input/output port on integrated circuit 1700 or to other data destinations within or outside of integrated circuit 1700. The state mechanism and the improved clock circuit (as discussed herein) are in circuit 1734.

Figure 18 is a circuit diagram similar to Figure 16, showing a circuit diagram of an integrated circuit clock circuit having tolerance to power supply noise fluctuations, and further including a switching circuit between the reference generator and the operational amplifier. As shown in Fig. 8, switching transistor 818A is turned on by signal ENX and switching transistor 818B is turned on by signal ENY. Similar to Figure 8, the grounded noise from the timing power and level switching generators 1616A and 1616B is stored in the capacitive node REFX or REFY.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

102. . . Sequential circuit

104. . . Level switching circuit

106. . . Latch circuit

108. . . Feedback signal

110. . . Clock signal

112. . . Level switching reference value

114. . . Sequential circuit reference

116. . . Generating a circuit with a temperature compensation level switching reference value and a timing circuit reference value

118. . . a circuit selectively coupled to noise

202A, 202B, 302A, 302B, 802A, 802B. . . Sequential circuit

1102A, 1102B, 1602A, 1602B. . . Sequential circuit

204A, 204B. . . Inverting circuit

206, 306, 806, 1106, 1606. . . Latch circuit

210A and 210B. . . Schmitt trigger circuit

304A, 304B, 804A, 804B. . . Level switching circuit

1104A, 1104B, 1604A, 1604B. . . Level switching circuit

422, 522. . . Power conditioner

816A, 816B. . . Level switching reference circuit

1116A, 1116B. . . Timing power supply and level switching reference generator

1234. . . Reference signal REF_OP

1236. . . power supply

1238. . . Gold oxygen half field effect transistor

1246, 1301. . . Timing power supply

1248, 1302. . . Level switching reference value

1303. . . Power supply and reference value

1616A, 1616B. . . Timing power supply and level switching reference generator

1620A, 1620B, 1620C, 1620D. . . Toggle switch

1700. . . Integrated circuit

1712. . . Memory array

1714. . . Character line/block selection decoder and driver

1716. . . Word line

1718. . . Bit line decoder

1720. . . Bit line

1722, 1726. . . Busbar

1724. . . Amplifier and data input structure

1728. . . Data input line

1732. . . Data output line

1736. . . Bias adjustment supply voltage current source

1734. . . State mechanism and clock circuit

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figure 1 shows a block diagram of an integrated circuit clock circuit having, for example, temperature, ground voltage, or power supply voltage variation tolerance.

2A and 2B are circuit diagrams showing an integrated circuit clock circuit having tolerance to temperature fluctuations, including an inverting circuit for evaluating the output of the sequential circuit, wherein FIG. 2A has a capacitive sequential circuit coupled to the ground. Figure 2B has a capacitive sequential circuit coupled to the power supply.

Figure 2C shows a circuit diagram of an integrated circuit clock circuit with tolerance to temperature variations, similar to Figure 2A, but receiving power from a PTAT source instead of from a CTAT source.

Figure 2D shows a circuit schematic of an integrated circuit clock circuit with tolerance to temperature variations, including a Schmitt trigger circuit to evaluate the output of the sequential circuit.

Figure 2E shows a schematic diagram of a Schmitt trigger circuit, such as in Figure 2D.

3A and 3B are circuit diagrams showing an integrated circuit clock circuit having tolerance to temperature fluctuations, including an operational amplifier circuit for performing level detection of the output of the sequential circuit by comparing the output with a reference value, wherein Figure 3A has a capacitive sequential circuit coupled to ground and Figure 3B has a capacitive sequential circuit coupled to the power supply.

Fig. 4A is a circuit diagram showing a reference signal of a level detecting circuit including a PTAT current source having a reduced current output as temperature increases.

Figure 4B is a circuit diagram showing a reference signal of a level detection circuit including a CTAT current source having an increased current output as temperature increases.

Fig. 4C is a circuit diagram showing a reference signal of the level detecting circuit, which includes a PTAT current source having a reduced current output as the temperature increases, and further having a capacitor in parallel with the load resistance of a current mirror.

Figure 4D is a schematic diagram of a current generator that provides PTAT current from a PMOS device in accordance with a reference circuit.

Figure 4E is a schematic diagram of a current generator that provides PTAT current from an NMOS device in accordance with a reference circuit.

Figure 4F is a schematic diagram of a current generator that provides CTAT current from a PMOS device in accordance with a reference circuit.

Figure 4G is a schematic diagram of a current generator that provides CTAT current from an NMOS device in accordance with a reference circuit.

Fig. 5A is a circuit diagram showing a reference signal of the level detecting circuit, which includes a current source having a reduced current output as the temperature increases, and an output which decreases as the temperature increases.

Fig. 5B is a circuit diagram showing a reference signal of the level detecting circuit, which includes a current source having an increased current output as the temperature increases, and an output which increases as the temperature increases.

Figure 5C is a circuit diagram showing a reference signal of a level detecting circuit including a current source having a reduced current output as temperature increases, and an output that increases as temperature increases.

Fig. 5D is a circuit diagram showing a reference signal of the level detecting circuit of Fig. 5C, but including a current source having an increased current output as temperature increases.

Figure 5E is a variation of the circuit of Figure 5C in which the CTAT_I constant current source 526 is replaced by a resistor RES 524.

Figure 6A shows a set of trajectory curves of time versus rise magnitude, showing how this clock circuit has temperature variation tolerance, and its resulting clock timing can vary greatly with temperature.

Figure 6B shows a set of trajectory curves of time versus rise magnitude, showing how this clock circuit has temperature variation tolerance, because using the circuits shown in Figures 2 through 5, the clock timing generated is essentially not The temperature changes and changes.

Figure 7A shows a set of trajectory curves of time versus descent magnitude, showing how this clock circuit has temperature variation tolerance, and its resulting clock timing can vary greatly with temperature.

Figure 7B shows a set of trajectory curves for the relationship between time and drop size, showing how this clock circuit has temperature variation tolerance, because using the circuit shown in Figures 2 through 5, the clock timing generated is essentially not The temperature changes and changes.

8A and 8B are circuit diagrams showing an integrated circuit clock circuit having a capability to withstand ground noise fluctuations, including a transistor selectively coupled to ground noise to serve as a level detector for the output of the sequential circuit. A portion of the reference signal is measured, wherein the 8A diagram has a capacitive sequential circuit coupled to ground and the 8B diagram has a capacitive sequential circuit coupled to the power supply.

Figure 9 is a plot of voltage vs. time showing how the clock circuit has the ability to withstand ground noise variations, and the clock timing that can be generated can vary greatly with respect to ground noise that changes over time.

Figure 10 is a set of voltage vs. time graphs showing how the clock circuit has the ability to withstand ground noise variations. Because of the circuit in Figure 8, the ground noise can be changed over time. A relatively stable clock timing is generated.

11A and 11B are circuit diagrams showing an integrated circuit clock circuit having power supply noise tolerance capability, including a power supply for the transistor and the timing circuit power supply, and a reference signal for the level detection of the output of the sequential circuit. The power supply noise shares the noise phase, wherein the 11A picture has a capacitive sequential circuit coupled to the ground and the 11B picture has a capacitive sequential circuit coupled to the power supply.

Figure 12 shows a circuit diagram of a power supply circuit that shares the same noise phase as the power supply noise of the timing circuit power supply and the power supply noise of the reference signal of the timing circuit output.

Figure 13 is a set of voltage vs. time graphs showing how the timing circuit power supply and the reference signal used for the level detection of the output of the sequential circuit are compared between the timing signals as shown in Fig. 11 or Fig. 12. Have the same noise phase.

Figure 14 is a plot of voltage vs. time showing how this clock circuit has the ability to withstand power supply noise fluctuations, which can generate clock timing in power supply noise that changes significantly over time.

Figure 15 is a set of voltage vs. time graphs showing how the clock circuit has the ability to withstand power supply noise fluctuations, which can be significantly greater over time due to the circuits in Figures 11 and 12. A relatively stable clock timing is produced in the changed power supply noise.

16A and 16B are circuit diagrams showing an integrated circuit clock circuit having power supply noise tolerance capability, including a power supply noise of a transistor and a sequential circuit power supply, and a reference signal for the level detection of the output of the sequential circuit. The noise phase shared by the power supply noise is similar to that of Figure 11, and a switching circuit is added, such as selectively bypassing the noise tolerance circuit when the power is turned on.

Figure 17 is a block diagram showing a memory circuit of the present invention having an improved integrated circuit clock circuit.

Figure 18 is a circuit diagram similar to Figure 16, showing a circuit diagram of an integrated circuit clock circuit having tolerance to power supply noise fluctuations, and further including a switching circuit between the reference generator and the operational amplifier.

102. . . Sequential circuit

104. . . Level switching circuit

106. . . Latch circuit

108. . . Feedback signal

110. . . Clock signal

112. . . Level switching reference value

114. . . Sequential circuit reference

116. . . Generating a circuit with a temperature compensation level switching reference value and a timing circuit reference value

118. . . a circuit selectively coupled to noise

Claims (24)

An integrated circuit device comprising: a clock integrated circuit comprising: a first reference signal comprising a variability noise; a sequential circuit having a first reference signal and a second reference signal An output of the switching, the rate of the switching being determined by a time constant determining a clock signal output timing of the clock integrated circuit, wherein the output of the sequential circuit changes in the output of the sequential circuit (1) When the second reference signal falls to the first reference signal and (2) rises from the first reference signal to the second reference signal, the value of the variability noise included in the first reference signal is stored. a reference circuit having an output selectively coupled to the variant noise such that the output of the reference circuit changes in the output of the sequential circuit (1) from the second reference signal to the first a reference signal and (2) storing the value of the variability noise when the first reference signal rises between the second reference signal; and a level switching circuit for comparing the output of the reference circuit with The timing The output path, so that a level of the output switching circuit outputs the clock signal determines the clock of the integrated circuit. The device of claim 1, wherein the timing circuit selectively receives the variability noise included in the first reference signal, the output according to the sequential circuit is at (1) The second reference signal drops to the state of the first reference signal or (2) the state from the first reference signal to the second reference signal. The device of claim 1, wherein the output of the reference circuit coupled to the variability noise corresponds to the timing circuit descending from the second reference signal to the first reference signal, and The output of the reference circuit decoupled from the variability noise corresponds to when the timing circuit rises from the first reference signal to the second reference signal. The device of claim 1, wherein the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit is switched to be charged from the first reference voltage. And discharging the second reference voltage from the second reference voltage to the first reference voltage. The device of claim 1, wherein the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit is switched to be charged from the first reference voltage. And discharging the second reference voltage from the second reference voltage to the first reference voltage, and wherein the output of the reference circuit changes in the output of the timing circuit from (1) falling from the second reference voltage The value of the variability noise is stored until the first reference voltage to (2) rises from the first reference voltage to the second reference voltage. The device of claim 1, wherein the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the variability noise is a variability noise voltage. . The device of claim 1, wherein the first reference signal is a ground reference voltage. The device of claim 1, wherein the time constant is an exponential signal. The device of claim 1, wherein the level switching circuit compares the output of the reference circuit with the stored variability noise value, and the chronological circuit includes the stored variability The output under the noise value to determine the clock signal output of the clock integrated circuit. The device of claim 1, wherein the timing circuit is configured to couple the first reference signal to the sequential circuit and to dissociate the second reference signal from the sequential circuit, wherein the first reference signal Having the variability noise, such that the timing circuit discharges the second reference signal to the first reference signal; and wherein the timing circuit is configured to dissociate the first reference signal from the sequential circuit, and the The second reference signal is coupled to the timing circuit, wherein the first reference signal has the variability noise, such that the timing circuit charges the first reference signal to the second reference signal. The device of claim 1, wherein the timing circuit is configured to couple the first reference signal to the sequential circuit, and dissociate the second reference signal from the sequential circuit, wherein the first reference signal has The variating noise is such that the timing circuit discharges the second reference signal to the first reference signal; wherein the timing circuit is configured to dissociate the first reference signal from the sequential circuit and the second reference signal And coupled to the timing circuit, wherein the first reference signal has the variability noise, such that the timing circuit charges the first reference signal to the second reference signal; and wherein the timing circuit is set to be at the timing The output of the circuit is stored (1) from the second reference signal until the first reference signal changes to (2) the value of the variability noise is stored when the first reference signal rises to the second reference signal. The device of claim 1, wherein the output of the reference circuit is set to couple the variability noise, and the (1) falls from the second reference signal to the first reference signal in response to the (1) signal; And wherein the output of the reference circuit is set to dissociate the variability noise in response to the (2) rising from the first reference signal to the second reference signal, and wherein the output of the reference circuit is set The output is stored in the timing circuit from (1) when the second reference voltage drops to when the first reference voltage changes to (2) the first reference voltage rises from the first reference voltage to the second reference voltage, the variability is stored The value of the noise. The device of claim 1, wherein the clock integrated circuit further comprises: a latch circuit for generating the clock signal output of the clock integrated circuit in response to the output of the level switching circuit. A method for generating a clock signal, comprising: determining a timing of a clock integrated circuit, by switching a sequential circuit output between a first reference signal and a second reference signal, a rate of the switching is performed by the clock The time constant determined by the timing of the integrated circuit is determined, wherein an output of the one of the sequential circuits is varied at (1) from the second reference signal to the first reference signal and (2) And storing, when the first reference signal rises between the second reference signal, a value of the variability noise included in the first reference signal; selectively coupling the variability noise to enable the reference circuit The output, when the output of the sequential circuit varies between (1) falling from the second reference signal to the first reference signal and (2) rising from the first reference signal to the second reference signal, storing The value of the variability noise; and comparing the output of the reference circuit with the output of the sequential circuit to determine a clock signal output of the clock integrated circuit. The method of claim 14, wherein the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit is switched to be charged from the first reference voltage. And discharging the second reference voltage from the second reference voltage to the first reference voltage. The method of claim 14, wherein the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the variability noise signal is a variability noise Voltage. The method of claim 14, wherein the first reference signal is a ground reference voltage. The method of claim 14, wherein the time constant is an exponential signal. The method of claim 14, wherein the comparing step comprises: comparing the output of the reference circuit to the stored variability noise value, and the chronological circuit includes the stored variability The output under the signal to determine the clock signal output of the clock integrated circuit. The method of claim 14, wherein the step of determining the timing comprises: coupling the first reference signal to the sequential circuit, and dissociating from the second reference signal from the sequential circuit, wherein the first The reference signal has the variability noise signal, so that the timing circuit charges the second reference signal to the first reference signal; and dissociates from the first reference signal, and couples the sequential circuit to the second reference signal The first reference signal has the variability noise signal, such that the timing circuit discharges from the first reference signal to the second reference signal. The method of claim 14, wherein the step of determining the timing comprises: coupling the first reference signal to the sequential circuit, and dissociating from the second reference signal from the sequential circuit, wherein the first The reference signal has the variability noise signal, such that the timing circuit discharges from the second reference signal to the first reference signal; dissociates from the first reference signal, and couples the sequential circuit with the second reference signal, The first reference signal has the variability noise signal, so that the timing circuit charges from the first reference signal to the second reference signal, including: when the output changes (1) from the second reference signal to The first reference signal and (2) store the value of the variability noise when the first reference signal rises between the second reference signal. The method of claim 14, wherein the selectively coupling comprises: in response to the (1) falling from the second reference signal to the first reference signal, the reference circuit output and the variation The noise signal is coupled; and in response to the (2) rising from the first reference signal to the second reference signal, the output is dissociated from the reference circuit output from the variator signal, including: when the timing circuit is The output changes from (1) falling from the second reference voltage to the first reference voltage to (2) rising from the first reference voltage to the second reference voltage, storing the value of the variogram signal at the timing Circuit. The method of claim 14, wherein the comparing comprises: generating the clock signal output of the clock integrated circuit using a latch circuit after comparing the output of the reference circuit with the output of the sequential circuit. A method of fabricating a device, comprising: providing a clock integrated circuit, comprising: providing a first reference signal including a variability noise signal; providing a timing circuit having the first reference signal and a first And an output of the switching between the two reference signals, the rate of the switching is determined by a time constant determining a clock signal output timing of the clock integrated circuit, wherein the output of the sequential circuit is changed at the output of the sequential circuit And (1) storing the variation included in the first reference signal when the second reference signal drops to the first reference signal and (2) rises from the first reference signal to the second reference signal a value of the noise; providing a reference circuit having an output selectively coupling the variant noise such that the output of the reference circuit changes in the output of the sequential circuit from (1) Storing the value of the variability noise when the reference signal drops to the first reference signal and (2) rising from the first reference signal to the second reference signal; and providing a level switching circuit for comparing The output of the reference circuit and the output of the timing circuit, so that a level of the output switching circuit determines the clock of the clock signal output of the integrated circuit.