TWI383368B - Driving device of liquid crystal display - Google Patents

Description

Driving device for liquid crystal display device

The present invention relates to a driving device for a liquid crystal display device, and more particularly to a driving device for a liquid crystal display device which can be operated in a full color display and an 8-color color mode.

In the liquid crystal display device, although there is a demand for full-color display for high image quality, on the other hand, in the standby state, full color is not required, and it is not preferable to use less color (for example, 8 colors). ) Display can suppress power consumption. Among them, the 8-color color mode is the most representative. In the 8-color color mode, the three primary colors are not gradated, but the three primary colors are switched on or off to obtain eight states.

In full color display, sufficient tone control must be performed for each color.

Fig. 1 is a view showing a typical configuration example for performing the above-described full color tone.

When a pixel is displayed, the data code corresponding to the tone is applied to the driving device, and is converted to a voltage signal corresponding to the data code on the driving device side, and the voltage signal is applied to the source line of the thin film transistor, the film The drain of the transistor is connected to the liquid crystal cell, and the voltage signal is applied to the liquid crystal cell and the transmittance is changed by applying a high voltage to obtain a desired image, wherein the high voltage is used to open the thin film transistor. The gate or the connected gate line.

In this case, the relationship between the data code and the driving voltage is nonlinear, but has the characteristics of a gamma (gamma) curve. A typical structure for obtaining a voltage corresponding to this gamma curve is shown in FIG.

Here, the curve shown is the relationship between the data code and the voltage. From the above, the voltage of 256 steps is obtained, and the data code is from 0 to 255, that is, the data of 8 bits is applied, and the data is obtained from the data. The voltage.

First, in order to obtain a voltage range, a voltage of 17 types from V0 to V16 taken out by resistor division is obtained by the reference voltage generator 10 having 18 resistor dividers connected in series between the power source and the source. The 4-bit switch matrix 20 selects one of 16 voltage ranges according to the upper 4 bits of the data to output V _n and V _{n+1 of the} display voltage range. Using the 4-bit lower bits of the data, a 4-bit linear digital analog converter (DAC) 30 is used to obtain any of the 16 voltages within the selected voltage range. In the example of Fig. 1, the voltage is cut into any one of the voltages corresponding to the data codes 223 to 239 in the voltage range V14-V15.

The circuit structure of Fig. 1 can be used as a structure for applying a switching source voltage to a source bus bar for a three-color pixel line of a color liquid crystal display device.

When voltage data is supplied for application to the red liquid crystal cells of the nth column of pixels, as described in FIG. 1, 17 kinds of voltage values are taken out from the reference voltage generator 10, and 16 kinds of the 17 kinds of voltage values are used. The voltage range is obtained by the voltage selector 20 (consisting of a 4-bit digital analog converter) using the upper 4 bits of the voltage data and outputting a corresponding voltage range (V _n and V _n+1 ), which is used for the voltage range. Applying to the source bus bar of the pixel column to be displayed, and outputting the voltage values V _n and V _{n+1 of} the voltage range to the 4-bit lower bit digital analog converter 30 to obtain a corresponding voltage range The voltage of the internal data value. This voltage is stabilized by a buffer (not shown), and this voltage is output to the source bus of the red pixel line by using a 1-to-3 (1:3) demultiplexer (not shown). Further, a precharge circuit (not shown) is further provided to prevent display operation delay due to large voltage fluctuations on the source bus bars of the respective colors.

Therefore, when a voltage is applied to the source busbars of the respective n columns, the precharge is performed first, and the red busbars of the nth column are prepared and driven, and then the green busbar of the nth column is performed. Preparation and driving, then, preparation and driving of the blue busbar in the nth column.

The conventional full-color display driving device shown in Fig. 1 has a large circuit scale and is very power-consuming.

As described above, in the driving device of the liquid crystal display device that switches between the full color mode and the eight color mode, the source driver has been prepared to perform the switching operation in response to the full color mode and the eight color mode. Therefore, the circuit component for full color does not completely stop the operation, and the desired effect of reducing current consumption cannot be obtained.

The object of the present invention is to provide a corresponding full color mode and 8 colors. In the driving device of the liquid crystal display device of the color mode, current consumption can be remarkably reduced by a simple structure.

According to one of the features of the present invention, a driving device for a liquid crystal display device is provided to drive a liquid crystal display element by a step voltage supplied to a source bus bar, wherein the driving device of the liquid crystal display device includes: a full color mode 1 drive unit, second drive unit for 8-color color mode, second, third, fourth and fifth switches.

The first driving unit for the full color mode includes: a reference voltage generator for generating a voltage value, wherein the voltage value is used to determine a rough range in the tone voltage; and the first digital analog converter is used And extracting, by the reference voltage generator, a value indicating a voltage range corresponding to a tone voltage to be applied to the liquid crystal cell of the display object; the second digital analog converter Selecting a detailed value from a voltage range specified by the first digital analog converter and selectively outputting the detailed value of the first digital analog converter; and demultiplexing the multiplexer The output of the second digital analog converter is supplied to the source bus.

The second driving unit for the 8-color color mode has a capacitor and a first switch, and the capacitor is connected to a power source or a ground by control of one of the data codes. The second, third, and fourth switches are activated in the eight-color mode by the switching signals of the full-color mode and the eight-color mode to stop the reference voltage generator and the first digital analog converter. The individual power supplies of the second digital analog converter. The fifth switch switches the capacitor output of the second drive unit to the demultiplexer.

Further, according to a second aspect of the present invention, a driving device for a liquid crystal display device is provided which drives a liquid crystal display element by a gradation voltage supplied to a source bus bar, and the driving device of the liquid crystal display device includes: a full color mode The first drive unit, the second drive unit for the 8-color color mode, and the third, fourth, fifth, and sixth switches.

The first driving unit for the full color mode includes: a reference voltage generator for generating a voltage value, wherein the voltage value is used to determine a rough range in the tone voltage; and the first digital analog converter is used And extracting, by the reference voltage generator, a value indicating a voltage range corresponding to a tone voltage to be applied to the liquid crystal cell of the display object; the second digital analog converter Selecting a detailed value from a voltage range specified by the first digital analog converter, and selectively outputting the detailed value of the first digital analog converter; and a demultiplexer, The output of the second digital analog converter is supplied to the source bus.

The second driving unit for the 8-color color mode includes a capacitor and a first switch, and the capacitor is connected to a power source or a ground by controlling one of the data codes; and the second switch is white when set. It is shown that the second open relationship connects the source bus bar to the power source, and is black for display when set, and the second open relationship connects the source bus bar to the ground. The third, fourth, and fifth switches are activated in the eight-color mode by the switching signals of the full-color mode and the eight-color mode to stop the reference voltage generator and the first digital analog converter. The individual power supplies of the second digital analog converter. The sixth switch, the 8-color color mode The capacitor output of the second driving portion is switched to be connected to the demultiplexer.

According to the present invention, the structure for the full-color display and the structure of the 8-color color display are disposed in one driving circuit, and the operation of the power-consuming DA converter or the buffer is stopped, so that the 8-color color mode can be adopted. Significantly reduce power consumption.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Fig. 2 is a block diagram showing a schematic configuration of a driving device of the present invention for explaining a column structure including three color pixels. This drive is based on a drive unit that displays in full color mode.

The clock generator and data lock 100, although not shown in Fig. 1, is used to latch the received image data and use the desired timing to select the upper bit D7-D4 and the lower bit D3- D0 output.

The reference voltage generator 110 for obtaining the voltage range is identical to the reference voltage generator 10 shown in FIG. 1, and has 17 resistor dividers between the power source and the ground, and the 17 resistor dividers are connected in series. 18 resistors and 17 switches SW1 are formed, and each of the 17 switches SW1 is connected to a connection point of any two resistors. It is used to obtain 17 kinds of voltages (V0~V16) obtained by dividing by resistance. These 17 voltages are applied to a voltage selector 120 composed of a 4-bit digital analog converter (DAC) through a 17-bit bus.

The voltage selector 120 outputs the voltage values V _n and V _{n+1 of the} display voltage range according to the upper 4 bits of the output data from the clock generator and the data lock 100.

The voltage values V _n and V _n+1 are applied to a 4-bit linear digital analog converter (DAC) 130.

The 4-bit linear DAC 130 obtains any of the 16 voltages within a specified voltage range based on the 4 bits below the output from the clock generator and data lock 100.

Since it is sufficiently understood that the above two DAC systems use a capacitor having a unit capacity ratio of 1:2:4:8 to generate a voltage, the description thereof will be omitted. Further, the power supply voltage V _DD is supplied to the DAC by the switch SW2, and the switch SW2 is operated only when it is ON.

The output of DAC 130 is stabilized by buffer 140. The reference current is supplied from the reference current generator 150 to the buffer 140 by the switch SW3.

The output of the buffer 140 is sequentially switched by the demultiplexer 160 and supplied to the source bus bars SB _R , SB _G , SB _B corresponding to the three colors.

Further, in order to increase the speed of display operation, a precharge circuit 170 for setting the potential of the source bus line before applying the buffer output to the source bus line is also provided.

The portion indicated by reference numeral 200 is a voltage generating device for performing 8-color color display, and is provided with a switch SW11 capable of switching connection between the power source and the ground, and a capacitor C1 disposed between the switch SW11 and the ground. . The switch SW11 further has one switching terminal and is connected to the input side of the demultiplexer 160.

Of the outputs of the clock generator and data lock 100, only the most significant bit data D7 is applied to the voltage generating device 200. Further, a control signal CTR for setting switching with the drive is also input to the voltage generating device 200.

Fig. 2 shows the case of full color display, in which SW1~SW3 are in the ON state, and SW11 is not connected anywhere.

In the state of the above switch, the voltage selector 120 selects two voltages V _n and V _{n+1 for} displaying the voltage range based on the upper bits of the data code, and outputs the same to the 4-bit linear digital analog converter (DAC) 130. The data code is derived from 17 voltage values taken from the reference voltage generator 110.

This four yuan by linear digital to analog converter (DAC) 130 may have a unit capacity than 1C, 2C, 4C, 8C of the capacitor 5 and the voltage V _n or V _{n + 1} is connected to the bit data obtained under 4 yuan Corresponding voltage value.

This voltage value is maintained within a 4-bit linear digital analog converter (DAC) 130. During pre-charging, in the source busbar pre-charged through the pre-charge circuit 170, the source busbar selected by the demultiplexer 160 is held in a 4-bit linear digital analog converter (DAC). The voltage within 130 is subjected to impedance transformation using buffer 140 and applied to the selected source bus during driving.

Fig. 3 is a view showing the same circuit configuration as that of Fig. 2, showing the case of the 8-color color mode.

First of all, the information applied to the clock generator and data lock 100 is only D7 of the uppermost bit, when the signal is at the high level, the switch SW11 is switched to the power supply side to charge the capacitor C1; when the D7 signal is at the low level, the switch SW11 is switched to the ground side to make the capacitor C1 Discharge.

In addition, since either of the switches SW1, SW2, and SW3 is turned off, the reference voltage generator 110, the voltage selector 120, and the 4-bit linear digital analog converter (DAC) 130 are turned off due to the power required for the operation. , so it becomes a state of non-action.

After the charge and discharge of the capacitor C1 is completed, the switch SW11 is connected to the demultiplexer side by the control signal CTR, and a voltage is applied to any one of the selected three source bus bars, or no voltage is applied.

With regard to any of the three source bus bars, any one of eight colors can be obtained by performing the same operation.

Fig. 4 is a circuit diagram for making the second and third figures more clear, and parts corresponding to those of Figs. 2 and 3 are given the same reference numerals. For the sake of simplicity, the multiplexer is omitted, and the two DACs are arranged into one element for display.

On the other hand, the switch SW111 is controlled by the data D7 for the purpose of charging and discharging the capacitor C1, and the switch SW112 is switched in response to the setting mode and the driving mode to connect the capacitor C1 to the source bus. Further, the precharge power source V _PC is connected to the source bus bar by the SW 12, wherein the SW 12 is controlled by the precharge control signal C _PC . The capacitors of the respective source bus bars L _{SX are} denoted by C _SB . Further, the switches SW2 and SW3 are controlled by an 8-color color display switching signal M8.

The operation of the 8-color color mode of the present invention will be described below using FIGS. 6-9. The circuit diagrams shown in FIGS. 6-9 are the clock map of FIG. 5 and one of the third and fourth figures. Take out the parts.

In the sixth to ninth diagrams, the 8-color color display is performed under the control of the 8-color color display switching signal M8, that is, the switches SW2 and SW3 are in a close state. In addition, here, although the power supply voltage is 5V, the precharge voltage is 2.5V.

As shown in Fig. 5, a series of actions are performed during a horizontal period 1H; during the first half horizontal period, the control signal CTR is set when the control signal CTR is at the low level (Lo); during the second half horizontal period, the control signal is The CTR is set to a high level (Hi).

First, in the case of black display, the supply data D7 is at a low level and the control signal CTR is at a low level. As shown in FIG. 6, the switch SW11 is connected to the ground side to discharge the capacitor C1. And, due to the pre-charge control signal Cpc being turned on, the pre-charging of the source bus can be performed at a voltage of, for example, 2.5V.

Further, as shown in Fig. 7, during the driving period in which the control signal CTR is at the high level (Hi), the capacitor C1 is connected to the source bus bar by the switch SW11, and the switch SW12 is open. At this time, the output voltage V _OUT on the source bus is determined by the capacitance of the capacitor C1 and the capacitor C _SB of the source bus. That is, since there is a relationship of C1 × 0 + C _SB × V _PC = (C1 + C _SB ) × V _OUT , V _OUT (black) = (C _SB / (C1 + C _SB )) × V _PC .

Specifically, once V _PC = 2.5 V, C1 = 40 pF, and C _SB = 10 pF are substituted, V _OUT (black) = 0.5 V is obtained.

Next, in the case of performing white display, the supplied data D7 is at the high level (Hi), and during the period when the control signal CTR is at the low level (Lo), as shown in FIG. 8, since the switch SW11 is connected to the power supply side. Capacitor C1 is charged and the precharge control signal is turned on, so pre-charging of the source busbar can be performed at a voltage of, for example, 2.5V.

Further, as shown in Fig. 9, during the driving period in which the control signal CTR is at the high level (Hi), the capacitor C1 is connected to the source bus bar by the switch SW11, and the switch SW12 is opened. At this time, the output voltage V _OUT on the source bus is determined by the capacitance value of the capacitor C1 and the capacitor C _SB of the source bus. That is, since there is a relationship of C1 × V _DD + C _SB × V _PC = (C1 + C _SB ) × V _OUT , it becomes V _OUT (white) = (C1/(C1 + C _SB )) × V _DD + (C _SB / (C1+C _SB )) × V _PC Specifically, when V _DD = 5V, V _PC = 2.5V, C1 = 40pF, and C _SB = 10pF are substituted, V _OUT (white) = 4.5V.

In this way, white and black display can be performed.

Fig. 10 is a circuit diagram showing the second embodiment, which is based on the circuits shown in Figs. 6 to 9. Among them, DE-MUX represents a connection formed by the demultiplexer 160.

In this modification, in the 8-color color mode, two capacitors connected to the source bus are provided for white display and black display, and are used separately according to the content of the D7 signal.

Specifically, for the white display, when the D7 signal is at the high level (Hi), the capacitor C1 is connected to the power supply VDD by the switch SW21; for the black display, when the D7 signal is at the low level (Lo) The capacitor C2 is grounded by the switch SW22.

In the above structure, the following relationship is obtained: V _OUT (white) = (C1/(C1 + C _SB )) × V _DD + (C _SB / (C1 + C _SB )) × V _PC V _OUT (black) = (C _SB / ( C2+C _SB ))×V _PC , by appropriately selecting the values of C1 and C2, the source line driving voltage can be independently selected under the white display and the black display.

Figure 11 is a circuit diagram showing a third embodiment of the present invention.

In this embodiment, the same portion (switch SW31) and switch SW32 as the voltage generating circuit 200 shown in Fig. 2 are provided, and a precharge circuit is not provided. Wherein, when the switch SW32 is set, the source bus bar is connected to the power source V _DD when the D7 is at the high level, and the source bus bar is grounded when the D7 is at the low level.

In the circuit of Fig. 11, in the case of the control signal CTR, the low level indicates the setting, and the high level indicates the driving. In the case of data D7, the high level indicates white display and the low level indicates black display.

In the case of white display, since the switch SW31 is connected to the ground side at the time of setting, the capacitor C1 is discharged. On the other hand, since the switch SW32 is connected to V _DD , the source bus bar capacitance is charged at V _DD .

When driving, the switch SW31 is connected to the source busbar side, and the switch SW32 is not connected to the source busbar side, so the output voltage becomes V _OUT (white) = (C _SB / (C1 + C _SB )) × V _DD .

In the case of black display, since the switch SW31 is connected to the V _DD side at the time of setting, the capacitor C1 is charged. On the other hand, the switch SW32 grounds the source bus bar, so the source bus bar capacitor is charged at V _DD .

At the time of driving, since the switch SW31 is connected to the source busbar side and the switch SW32 is not connected to the source busbar side, the output voltage is V _OUT (black) = (C1/(C1 + C _SB )) × V _DD .

It can be seen from the above formula of the output voltage that the smaller the capacitor is, the closer it is to the white display output, and the black display voltage is intended to be close to zero. In fact, once V _DD = 5V, C1 = 1.4pF, and C _SB = 10pF are substituted, V _OUT (white) = 4.505VV _OUT (black) = 0.494V, even if the capacity of C1 is significantly reduced, the embodiment 1 or 2 may also be the same action. Since the capacity of C1 is good even if it is small, the capacitor formation area can be reduced. In addition, since the precharge circuit does not require at least an 8-color color mode, the precharge circuit can be simplified.

Fig. 12 shows a fourth embodiment which is a combination of the second and third embodiments. That is to say, for the dialogue display, when the D7 signal is at the high level, the capacitor C1 is connected to the power source V _DD by the switch SW41; in addition, when the D7 signal is at the low level, the capacitor C2 is grounded by the switch SW42. . Moreover, the switch SW43 is provided, and the pre-charging circuit is not provided; wherein, when the switch SW43 is set, the source bus bar is connected to the power source V _DD when the data D7 signal is at the high level, and the source bus bar is connected when the level is low. Ground.

With this configuration, the effects obtained in the second and third embodiments can be obtained. That is to say, in addition to the free choice of the values of the capacitors C1 and C2, the value of C1 can also be reduced.

The above embodiments are not particularly limited, and those skilled in the art can make any modifications or substitutions within the scope of the invention.

10‧‧‧Reference voltage generator

20‧‧‧4 bit switch matrix

30‧‧‧4-bit linear digital analog converter

110‧‧‧reference voltage generator

120‧‧‧Voltage selector

130‧‧‧4-bit DAC

140‧‧‧buffer

150‧‧‧Reference current generator

160‧‧ ‧ multiplexer

170‧‧‧Precharge circuit

200‧‧8 color color mode voltage generation loop

C1, C2‧‧‧ capacitor

C _PC ‧‧‧Precharge control signal

C _SB ‧‧‧Source Bus Capacitor

CTR‧‧‧ control signal

L _sx , SB _R , SB _G , SB _B ‧‧‧ source bus

M8‧‧8 color color display switching signal

SW1, SW2, SW3, SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42, SW43‧‧‧ switch

V _DD ‧‧‧ power supply

V _pc ‧‧‧Precharge power supply

Figure 1 is a schematic diagram showing a conventional structure for obtaining a driving voltage from a data code.

2 is a block diagram showing a schematic configuration of a driving device of the present invention for displaying a state of a full color mode, wherein the driving device can source a color liquid crystal display device in a full color mode and an 8-color color mode. The source bus voltage is applied to the pole bus.

Fig. 3 is a view showing a state in which a source voltage is applied to a source busbar in an 8-color color mode in Fig. 2;

Figure 4 is a schematic circuit diagram depicting the portion associated with driving in 8-color color mode.

Fig. 5 is a view for explaining the operation in the structure of Fig. 4.

Fig. 6 is a schematic circuit diagram showing the setting operation of the black display in the 8-color mode.

Fig. 7 is a schematic circuit diagram showing the driving operation of the black display in the 8-color color mode in detail.

Fig. 8 is a schematic circuit diagram showing the setting operation of the white display in the 8-color color mode in detail.

Figure 9 is a schematic circuit diagram showing the driving motion of the white display in the 8-color mode.

Fig. 10 is a circuit diagram showing a second embodiment of the driving device of the present invention.

Figure 11 is a circuit diagram showing a third embodiment of the driving device of the present invention.

Fig. 12 is a circuit diagram showing a fourth embodiment of the driving device of the present invention.

100‧‧‧ Clock generator and data lock

110‧‧‧reference voltage generator

120‧‧‧Voltage selector

130‧‧‧4-bit linear DAC

140‧‧‧buffer

150‧‧‧Reference current generator

160‧‧ ‧ multiplexer

170‧‧‧Precharge circuit

200‧‧8 color color mode voltage generation loop

C1‧‧‧ capacitor

SW1, SW2, SW3, SW11‧‧‧ switch

SB _R , SB _G , SB _B ‧‧‧ source bus

Claims (5)

A driving device for a liquid crystal display device drives a liquid crystal display device by supplying a first-order voltage to a source bus, the driving device of the liquid crystal display device comprising: a first driving portion for a full color mode, including a reference voltage generator for generating a voltage value for determining a coarse range of the tone voltage; a first digital analog converter by a data bit upper bit And extracting, from the reference voltage generator, a value indicating a voltage range corresponding to a gradation voltage to be applied to the liquid crystal cell of the display object; a second digital analog converter, by using the lower bit of the data code And selecting a detailed value from the voltage range specified by the first digital analog converter, and selectively outputting the detailed value of the first digital analog converter; and a demultiplexer, the second The output of the digital analog converter is supplied to the source bus; the second driving portion of the 8-color color mode has a capacitor and a first switch, and the first switch is controlled by a part of the data code And connecting the capacitor to a power source or a ground; a second, third, and fourth switches, by switching between the full color mode and one of the eight color modes, operating in the eight color mode Stopping the individual power supply of the reference voltage generator, the first digital analog converter, and the second digital analog converter; a fifth switch for switchingly connecting a capacitor output of the second driving portion to the demultiplexer, wherein the capacitor is formed by a first capacitor connected to the power source and a second capacitor connected to the ground The first open relationship is performed by switching one of the first capacitors between the power source and the source busbar, and switching one of the second capacitors between the ground and the source busbar for the second time. The switch is composed of. The driving device for a liquid crystal display device according to claim 1, wherein a buffer is activated between the second digital analog converter and the demultiplexer only in the full color mode. The driving device for a liquid crystal display device according to claim 1, wherein a part of the data code is a highest bit. The driving device for a liquid crystal display device according to any one of claims 1 to 3, further comprising: a circuit for precharging the source bus bar. A driving device for a liquid crystal display device drives a liquid crystal display device by supplying a first-order voltage to a source bus, comprising: a first driving portion for a full color mode, comprising: a reference voltage generator, For generating a voltage value, wherein the voltage value is used to determine a coarse range of the tone voltage; a first digital analog converter is taken from the reference voltage generator by a bit bit of a data code Representing a value of a voltage range corresponding to a gradation voltage to be applied to a liquid crystal cell of a display object to be displayed; a second digital analog converter, selecting a detailed value from the voltage range specified by the first digital analog converter by the bit bit under the data code, and selectively outputting the first digital analog converter The detailed value; and a demultiplexer for supplying the output of the second digital analog converter to the source bus; the second driving unit for an 8-color color mode, comprising: a capacitor; a switch, connected to a power source or a ground by control of a portion of the data code; and a second switch for white display when set, the second switch connecting the source bus to the power source For setting black, the second switch connects the source bus to the ground; a third, fourth, and fifth switches switch signals by the full color mode and one of the eight color modes Actuating in the eight-color mode to stop the individual power supply of the reference voltage generator, the first digital analog converter, and the second digital analog converter; and the sixth switch to use the eight-color mode The capacitor of the second driving part An output switch is coupled to the demultiplexer, wherein the capacitor is formed by a first capacitor connected to the power source and a second capacitor connected to the ground; the first open relationship is between the power source and the source The first bus switch switches between the first bus and the second switch of the second capacitor between the ground and the source bus.