200905659 九、發明說明： 【發明所屬之技術領域】 本發明係有關於液晶 關於可以在全彩色顯示及 示裝置之驅動裝置。 顯示裝置之驅動裝置，特別是 8色彩色模式下作動之液晶顯 【先前技術】 在液晶顯示裝置中’雖然為了高晝質化而要 色顯示之要求越來越多，但是，另一方面，在待機狀態 下並不需要全彩色’不如以較少的顏色（例如8色）進 仃顯示，可以抑制電力消耗。其中，以 具代表性。8色彩色模心㈣μ “ 式最 巴棋式係非對3原色施予階調，而是對 该3原色之開啟或_狀態進行⑽而得到⑽狀態。 以全彩色顯示而言，必須針對各色進行充分 控制。 構例第1圖係顯示用於進行上述全彩色之階調的典型結 在某I素進行顯示時，與階賴應之:#料碼施於驅 動裝置’在驅動裝置侧被轉換為對應此資料碼之電麼信 號’該電|信號施加至薄膜電晶體之源極線，該薄膜^ 晶體之沒極係連接液晶胞，藉由施加高電壓，而將前述 電壓信號施於液晶胞並改變透過率，以得到所欲之影 像，其中’該高電壓係用於打開此薄膜電晶體之閘極： 連接之閘極線。 5 〇773-A33283TWF;KB05007 200905659 在胃此種情況下，資料碼與驅動電壓之關係並非線 性，而是具有伽瑪（gamma; r )曲線之特性。用於得到與 此τ曲線對應之電壓之習知的典型結構如圖丨所示。 在此，圖示之曲線係為資料碼對電壓之關係，從上 述得到256階調之電壓，資料碼係從〇到255，也就是說， 施加8位元之資料，並從此資料得到所欲之電壓。 首先’為了得到電㈣圍’藉由具有在電源與源極 間串連之18個電阻分割器的參照電壓產生器1〇，得到藉 由電阻分料取出之從V G到V〗6之丨7種類的電壓，^ 用4位元開關矩陣2〇，依資料之上位4位元而選擇_ 電壓範圍之一個，以輸出顯示電壓範圍之、與Vn+i。使 用資料之下位4位元，藉由4位元線性數^類比η變換器 (DAC) 3G’得到在所選擇之該電壓範圍内之16種電壓 中之任-個。在第1圖之例中，係將電壓範圍YU—州 内被切割成對應資料碼223至239之電壓中的任一 以輸出。 第1圖之電路構造，在彩色液晶顯示裝置之金 素線用之雜匯流排上’能_為施加切換源 =200905659 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a liquid crystal device for driving a display device in full color. Driving device for display device, in particular, liquid crystal display operating in 8-color color mode [Prior Art] In the liquid crystal display device, although there are more and more requirements for color display for high quality, on the other hand, In the standby state, it is not necessary to use full color 'it is better to enter the display with less color (for example, 8 colors), and power consumption can be suppressed. Among them, it is representative. 8-color color core (4) μ "The most bar type is not the tone of the 3 primary colors, but the (3) state is obtained by the opening or _ state of the 3 primary colors. In the full color display, it is necessary to fully perform for each color. Control. Fig. 1 shows that the typical knot used to perform the above-mentioned full-color tone is displayed when a certain element is displayed, and the order is: #料码为驱动装置' is converted to the drive side Corresponding to the data signal of the data code, the signal is applied to the source line of the thin film transistor, and the thin film of the thin film is connected to the liquid crystal cell, and the voltage signal is applied to the liquid crystal cell by applying a high voltage. And change the transmittance to get the desired image, where 'the high voltage is used to open the gate of the thin film transistor: the connected gate line. 5 〇773-A33283TWF; KB05007 200905659 In the case of stomach, The relationship between the data code and the drive voltage is nonlinear, but has the characteristics of a gamma (r) curve. A typical structure for obtaining a voltage corresponding to this τ curve is shown in Fig. 在. The curve is shown as The relationship between the material code and the voltage, the voltage of 256 steps is obtained from the above, and the data code is from 〇 to 255, that is, the data of 8 bits is applied, and the desired voltage is obtained from the data. First, in order to obtain electricity (4) By using a reference voltage generator 1 具有 having 18 resistor dividers connected in series between the power source and the source, a voltage of 7 types from VG to V 6 taken out by the resistor shunt is obtained. The 4-bit switch matrix 2〇 selects one of the _ voltage ranges according to the upper 4 bits of the data to output the display voltage range and Vn+i. Use the lower 4 bits of the data, and use the 4-bit linear number. ^ Analog η converter (DAC) 3G' obtains any of the 16 voltages in the selected voltage range. In the example of Fig. 1, the voltage range YU-state is cut into corresponding data. Any one of the voltages of the codes 223 to 239 is output. The circuit configuration of Fig. 1 is applied to the switching bus for the gold-line of the color liquid crystal display device.
德：ik ~ 王WJ 當徒供電壓資料用以施加在第^晝素之紅色P 胞上時’如第1圖所述’從參照電壓產生_ 取曰曰 種之電壓值^等17種電|㈣的16種電壓範圍 由電壓選擇器20(由4位元數位類比變換 電壓資料之上位4位元，而輸出對應之電壓上= 〇773-A33283TWF;KB〇5〇〇7 6 200905659 vn+1)，δ亥電壓範圍係用以施加至所要顯示晝素列的源極 匯流排上，並將該電壓範圍的電壓值、及;…輸出給4 位元下位位元數位類比換變器3〇,而得到一對應於該電 壓範圍内資料值的電壓。利用緩衝器（未圖示）穩定此電 壓，再利用！對3⑽之解多工器（未圖示），將此電壓輸 出至紅色晝素線之源極匯流排上。此外，纽置有預充 電電路（未圖示）’用㈣止由於各色之源極匯流排上的大 電壓變動所造成之顯示動作延遲。 藉此，在對某n列之各色的源極匯流排施加電壓 時，最初進行預充電，並推斿諠 χι 电 X進仃第n列之紅色用匯流排之 準備與驅動，接著，進; 有進仃第η列之綠色用匯流排之準備 與驅動，然後，進行第η方丨丨七#々 去 丁第η列之藍色用匯流排之準備與驅 動。 第1圖所不之傳統全彩色顯示之驅動裝置，有電路 規模大而且非常耗電之問題。 如前所述’在城全彩色模纽8色彩色模式而進 仃.4不之液晶顯示裝置的驅動裝置中，一直 驅動器為因應全彩色;8 “、 , ㈣式及8色彩色模式之用而準備谁 仃切換動作；因此，關於全 備進 會完全停止動作Up , 構成。卩分並不 嗖果 …、去件到所期待之削減電流消耗的 【發明内容】 本發明之目的係提供—種對應全彩色模式及8色彩 〇773-A33283TWF;KB05007 200905659 色模式之液晶顯不裝置的驅動裝置’可以藉由簡單結構 而顯著地降低電流消耗。 〇根據本發明特徵之一，係提供一種液晶顯示裝置之 ，動裝置’藉由供給至源極匯流排之階調電壓以駆動液 曰^顯不7G件，該液晶顯示裝置之驅動裝置包括：全彩色 模式用之第1驅動部，8色彩色模式用之第2驅動部，第 2、第3、第4以及第5開關。 。該王彩色模式用之第】驅動部，包括··參照電壓產 2 ’用於產生一電壓值’而該電壓值用以決定該階調 電壓中的粗略範圍；第i數位類比變換器，係藉由資料 碼之上位位元而從該參照電壓產生器取出表示電壓範圍 =值’該資料觸職於㈣加幼狀顯㈣象液晶 胞的階調電壓；第2數位類比變換器’藉由該資料碼之 :位位兀而自該第1數位類比變換器所指定之電壓範圍 選擇詳細值’並且選擇性地輸出該第1數位類比變換器 ^該詳細值；以及，解多工器，將該第2數位類比變換 器之輸出供給至該源極匯流排。 該8色彩色模式用之第2驅動部，具有電容器及 1開關’藉由該資料碼之一部分的控制，將該電容 =源或接地。該第2、第3及第4開關，藉由該全彩色 模式與該8色彩色模式之切換信號，在該8色 時作動以停止該參照電壓產生器、第i數位類比變換号式 第2數位類比變換器之個別電源供給。該第$開關： 該第2驅動部之電容器輸出切換連接至該解多工器。 0773-A33283TWF;KB05007 8 200905659 另外，根據本發明特徵之二，係提供—種 裝置之驅動裝置，藉由供給至源極匯流: 驅動液晶顯示元件，該液晶顯示裝置之驅動穿而 全衫色模式用之第1驅動部，8色彩色模式用之第2备 部，第3、第4、第5以及第6開關。用之第2驅動 “王色拉式用之第1驅動部’包括：參照電墨產 器’用於產生一電壓值’而該電壓值用以決定該 電壓中的粗略範圍；第1數位類比變換器，係藉由資： 碼之上位位元而從該參照㈣產生器取出表示電壓範圍 之值’該讀碼係制於㈣加至相對之顯㈣ 胞的階調電壓，·第2數位類比變換器，藉由該資料碼： 下位位兀而自該第1數位類比變換器所指定之電壓範圍 内選擇詳細值，並謂擇性地輸出該第丨數位類比變換 :之該詳細值；以及解多工器，將該第2數位類比變換 器之輸出供給至該源極匯流排。 該8色彩色模式用之第2驅動部，包括：電容器及 第1開關，藉由該資料碼之一部分的控制，將該電容器 連接至電源或接地；及第2開關’在設定時，對於白顯 示》亥第2開關係將该源極匯流排連接至電源，在設定 於黑顯不’該第2開關係將源極匯流排連接至接地。 該第3、第4及第5開關，藉由該全彩色模式與該8色彩 色杈式之切換信號，在該8色彩色模式時作動以停止該 參照電壓產生器、f 1數位類比變換器、第2數位類比 變換益之個別電源供給。該第6開關，將該8色彩色模 〇773-A33283TWF;KB05007 9 200905659 切換連接至該解多 式用之第二驅動部之電容器輪出 器。 根據本發明，係將用於全 色顯示之結構設置於"固驅動迴路De: ik ~ Wang WJ When the voltage data is applied to the red P cell of the 昼素素, as shown in Fig. 1, 'from the reference voltage _ take the voltage value of the ^ type, etc. 17 kinds of electricity (4) The 16 voltage ranges are selected by the voltage selector 20 (the 4-bit digital analogy converts the voltage data to the upper 4 bits, and the output corresponds to the voltage = 〇773-A33283TWF; KB〇5〇〇7 6 200905659 vn+ 1), the δ-Hui voltage range is applied to the source bus bar of the pixel column to be displayed, and the voltage value of the voltage range, and ... is output to the 4-bit lower bit digital analog converter 3 Oh, and get a voltage corresponding to the data value in the voltage range. Use a buffer (not shown) to stabilize this voltage and reuse it! For the 3(10) demultiplexer (not shown), this voltage is output to the source busbar of the red halogen line. In addition, a pre-charging circuit (not shown) is used to delay the display operation due to a large voltage fluctuation on the source busbar of each color. Therefore, when a voltage is applied to the source busbars of the respective n columns, the pre-charging is performed first, and the preparation and driving of the red busbars in the nth column are pushed, and then advanced; There is a preparation and driving of the green busbar of the nth column, and then the preparation and driving of the blue busbar of the nth square 丨丨7#々丁丁η column. The conventional full-color display driving device shown in Fig. 1 has a large circuit scale and is very power-consuming. As mentioned above, in the driving device of the liquid crystal display device of the full-color model in the city, the driver is always in full color; 8 ", (4) and 8-color mode In addition, the person who prepares for the switching operation; therefore, the full standby will completely stop the action Up, and the composition will not result in the result of the reduction of the current consumption. [Invention] The object of the present invention is to provide Corresponding to full color mode and 8 color 〇 773-A33283TWF; KB05007 200905659 color mode liquid crystal display device 'drive device' can significantly reduce current consumption by simple structure. 〇 According to one of the features of the present invention, a liquid crystal display is provided. The driving device of the liquid crystal display device includes: a first driving portion for the full color mode, and an 8-color color by the urging voltage supplied to the source bus bar. The second driving unit for the mode, the second, third, fourth, and fifth switches. The driving unit for the king color mode includes a reference voltage product 2' for generating a voltage value' The voltage value is used to determine a rough range in the tone voltage; the i-th analog converter is taken from the reference voltage generator by the bit bit on the data code to indicate the voltage range=value. (4) adding a gradation voltage of the liquid crystal cell; and the second digital analog converter selects the detailed value by the voltage range specified by the first digital analog converter by the data bit: Selecting the detailed value of the first digital analog converter selectively; and demultiplexing the output of the second digital analog converter to the source bus. The second color mode is used for the second The driving part has a capacitor and a switch 'by controlling one of the data codes, the capacitance=source or ground. The second, third and fourth switches, by the full color mode and the 8-color color mode The switching signal is activated in the eight colors to stop the individual power supply of the reference voltage generator and the i-th analog analog type second digital analog converter. The first switch: the capacitor output switching of the second driving unit Connect to the solution In addition, according to a second feature of the present invention, a driving device for a device is provided, which is connected to a source and sinks: a liquid crystal display device is driven, and the driving of the liquid crystal display device is worn. The first driving unit for the color mode, the second standby unit for the 8-color color mode, and the third, fourth, fifth, and sixth switches. The second driving unit for the second driving "the first driving portion for the king color drawing type" includes : refer to the electric ink generator 'for generating a voltage value' and the voltage value is used to determine a rough range in the voltage; the first digital analog converter is from the reference by the capital: code upper bit The generator extracts the value indicating the voltage range'. The reading system is applied to (4) the gradation voltage applied to the relative display (four) cell, and the second digital analog converter, by the data code: the lower bit 兀 from the first Selecting a detailed value within a voltage range specified by the digital analog converter, and selectively outputting the third digit analog conversion: the detailed value; and a demultiplexer supplying the output of the second digital analog converter to The source bus. The second driving unit for the 8-color color mode includes a capacitor and a first switch, and the capacitor is connected to a power source or a ground by control of one of the data codes; and the second switch is set to be white. The display of the second open relationship connects the source busbar to the power supply, and the source busbar is connected to the ground in the second open relationship. The third, fourth, and fifth switches are activated in the eight-color mode by the full-color mode and the eight-color color switching signal to stop the reference voltage generator and the f 1 digital analog converter The second digital analogy converts the individual power supply. The sixth switch switches the 8-color color module 773-A33283TWF; KB05007 9 200905659 to the capacitor driver of the second driving unit for the demultiplexing type. According to the present invention, the structure for full-color display is set to "solid drive circuit
變換器或緩衝器之作動停止，θ 之DA 顯著地減少電力消耗。此’可以8色彩色模式 【實施方式】 以下， >圖面說明本發明之實施例。 第2圖係繪示本發明之驅動裝置之概略結構的 圖’用於說明包含有3色晝素之列結構。此驅動裝置係 以進行全彩色模式顯示之驅動裝置作為基礎。 時脈產生器及資料存鎖100,雖然並未顯示於第玉 圖，但是其作用係將所接收之影像資料鎖存，並利用所 要的時序將上位位元D7_D4及下位位元D3_D〇輸出。 用於得到電壓範圍之參照電壓產生器11〇係與第i 圖所示之參照電壓產生器10完全相同，在電源與接地間 具有17個電阻分割器，該17個電阻分割器係由串接之 18個電阻器以及17個開關SW1所構成’每一該17個開 關SW1係分別連接至任兩個電阻器之連接點。用以得到 透過電阻分割而取得的17種電壓（V0〜V16)。此17種電 壓’通過17位元匯流排而施加至由4位元數位類比變換 器（DAC)所構成之電壓選擇器120。 電壓選擇器120,依據來自時脈產生器及資料存鎖 〇773-A33283TWF;KB05007 10 200905659 100輸出資料之上位4位元，輸出顯示電壓範圍之電壓值 V』Vn+1。 電壓值乂。與Vn+1係施加於4位元線性數位類比變 換器（DAC) 130。 此4位元線性DAC 130，依據來自時脈產生器及資 料存鎖100輸出資料之下位4位元，而得到位於指定之 電壓範圍内之16種電壓中任一者。 由於已經充分瞭解上述2個DAC係使用單位容量比 為1:2:4: 8之電容器而產生電壓的緣故，因此省略說 明。另外，電源電壓VDD係藉由開關SW2而供給至上述 DAC，開關SW2僅於ON時進行作動。 DAC130之輸出係藉由缓衝器140而安定化。藉由 開關SW3，從參照電流產生器150供給參照電流至緩衝 器 140。 缓衝器140之輸出係藉由解多工器160而依序切換 並供給至與3色對應之源極匯流排SBr、SBG、SBb。 而且，為了謀求顯示作動之高速化，亦設置預充電 電路170,而此預充電電路170係在將緩衝器輸出施加於 源極匯流排之前，用於使源極匯流排電位上昇。 參考符號200所示之部分，為用以執行8色彩色顯 示之電壓產生裝置的結構，具備能在電源與接地之間進 行切換連接之開關SW11、以及設於此開關SW11與接地 間之電容器C1。開關SW11更具有1個切換端子，與解 多工器160之輸入侧連接。 0773-A33283TWF;KB05007 11 200905659 時脈產生器及資料存鎖100之輸出中，僅最高位位 元之資料D7施加於電壓產生裝置200。另外，用於設定 與驅動之切換的控制信號CTR也輸入至電壓產生裝置 200。 第2圖係顯示全彩色顯示之情況，其中SW1〜SW3 成為ON之狀態，而SW11並未連接至任何地方。 在上述開關之狀態下，電壓選擇器120基於資料碼 之上位位元而選擇用以顯示電壓範圍之兩個電壓Vn與 Vn+1，並輸出給4位元線性數位類比變換器（DAC)130 ; 資料碼係得自於從該參照電壓產生器110取出之Π種電 壓值。 藉由此4位元線性數位類比變換器（DAC) 130可 以將具有單位容量比1C、2C、4C、8C之5個電容器與 電壓Vn4 Vn+1連接，而得到與資料之下位4位元對應的 電壓值。 此電壓值係保持在4位元線性數位類比變換器 (DAC) 130内。在預充電期間，於透過預充電電路170 而被預充電的源極匯流排中，由解多工器160所選擇的 源極匯流排上，使保持在4位元線性數位類比變換器 (DAC) 130内之電壓，利用緩衝器140執行阻抗變換， 並在驅動期間施加至該所選擇的源極匯流排。 第3圖係顯示與第2圖相同之電路結構，說明8色 彩色模式之情況。 首先，施於時脈產生器及資料存鎖100之資料僅為 0773-A33283TWF;KB05007 12 200905659 最上位位兀之D7，於此信號為高準位之時，開關swn 係切換至電源側而使電容H C1充電；D7信號為低準位 時，則是開關swn切換至接地侧而使電容器C1放電。 另外’由於開關SW卜SW2、SW3任一個都關閉的 緣故，因此，參照電壓產生器11〇、電壓選擇器12〇、4 位元線性數位類比變換器（DAC)13〇由於動作所需的電 源被切斷，所以成為非動作之狀態。 電容器C1之充放電終了後，藉由控難號CTR， 開關swu係與解多工器側連接，並對選擇之3條源極 匯流排之任一個施加電壓，或不施加電壓。 關於3條源極匯⑽巾任何-條，#由進行同樣之 作動’可以得到8色中任何一個。 第4圖係使第2及第3圖更明確之電路圖，而與第 2圖及第3圖對應之部分係賦予相同的參考符號。為了簡 化起見，f略了解多工器’而2個DAC係整理成上個元 件而顯示。 另一方面，開關SW⑴，為了對電容器^ 目的，而由資料D7控制；開關swn2，回應設定 模式”驅純^進行對狀切換，以將電容以 至源極匯流排。另外，預充電電源v p C係藉由s w i 2而盥 二原極匯流排連接’其中’ SW12係利用預充電控制作號 c_PC而控制。將各個源極匯流排Lsx之電容器以c : 二：：:開關SW2與SW3係由δ色彩色顯示切‘號 0773-A33283TWF;KB05007 13 200905659 以下使用第6〜9 ®，說明本發明之8色 動作；其中第6〜9圖顯示之電路圖動作，係由、二的 時脈圖及第3圖及第4圖之1份取“得。圖之 下而第/Γ1係以在8色彩色顯示切換信號M8之控制 SW3:關門:f顯广乍為前題，也就是說，開關SW2及 二”閉(close)狀態。另外’在此，雖然電源 5V’但疋，預充電電壓為2.5v。 马 如第5圖所示’一連串之動作係在一水 間進灯，在前半水平期間，為#控制㈣ 位（Lo)時㈣行設定；在 處於低準 ⑽變成高準位(兩而= 期間’為當控制信號 .首先，在進行黑顯示之情況下，供給之資 低準位而控制信號CTR為低準位之設定期間，如第6圖 所不，因為開關swii係與接地側連接而使電容器ci放 電，且因預充電控制信號Cpc開啟的緣故，可以在例如 2.5V之電壓下進行源極匯流排之預充電。 另外，如第7圖所示，在控制信號CTR成為高準位 (=)之驅動期間’電容器。藉由開關swu而與源極匯 /；，L 、接，而開關SW12係開放（0Pen)。此時，源極匯流 排士，輪出電壓V〇ut，係由電容器C1與源極匯流排2 電容器CSB之電容值決定。也就是說，因為有 C1x〇H-CsbXVpc= (C1 + Csb) xV〇ut 之關係，所以成為 ν〇υτ (黑）=(CSB/ (C1 + CSB) ) XVPC。 〇773-A33283TWF；KB〇5〇〇7 14 200905659 代：而二一成旦〜2.5V、C1，、， V〇ut (黑）=〇.5V。 一接著，在進行白顯示之情況下，供給之資料〇7係 高準位㈣’而在控制信號CTR為低準位㈣期間，如 第8圖所示’因為開關SW11與電源侧連接，電容器ci 被充電’預充電控制信號被打開，所以可以在例如 之電壓下進行源極匯流排之預充電。 另外’如第9圖㈣，在控健號CTR成為高準位 (則之驅動期間’ t容器C1藉由開關swu而與源極匯 流排連接’而開關SW12係開放。此時，在源極匯流排 輸出電壓V0UT係藉由電容器C1與源極匯流排之電 容器CSB之電容值而決定。也就是說，因為有 C1xVdd+CsbxVpc= (C1 + Csb) χν〇υτ 之關係’所以成為The operation of the converter or buffer stops, and the DA of θ significantly reduces power consumption. This can be an 8-color color mode. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 2 is a view showing a schematic configuration of a driving device of the present invention for explaining a column structure including three color halogens. This drive is based on a drive unit that displays in full color mode. The clock generator and data lock 100, although not shown in the first figure, function to latch the received image data and output the upper bit D7_D4 and the lower bit D3_D〇 using the desired timing. The reference voltage generator 11 for obtaining the voltage range is identical to the reference voltage generator 10 shown in the figure i, and has 17 resistor dividers between the power source and the ground, and the 17 resistor dividers are connected in series The 18 resistors and the 17 switches SW1 constitute 'each of the 17 switches SW1 are respectively connected to the connection point of any two resistors. It is used to obtain 17 kinds of voltages (V0 to V16) obtained by dividing by resistance. These 17 voltages are applied to the voltage selector 120 composed of a 4-bit digital analog converter (DAC) through a 17-bit bus. The voltage selector 120 outputs a voltage value V 』Vn+1 of the display voltage range according to the upper 4 bits of the output data from the clock generator and the data lock 〇 773-A33283TWF; KB05007 10 200905659 100. The voltage value is 乂. The Vn+1 system is applied to a 4-bit linear digital analog converter (DAC) 130. The 4-bit linear DAC 130 obtains any of the 16 voltages within a specified voltage range based on the 4 bits below the output from the clock generator and the data lock 100. Since it is well understood that the above two DAC systems use a capacitor having a unit capacity ratio of 1:2:4:8 to generate a voltage, the description will be omitted. Further, the power supply voltage VDD is supplied to the DAC by the switch SW2, and the switch SW2 is operated only when it is ON. The output of DAC 130 is stabilized by buffer 140. The reference current is supplied from the reference current generator 150 to the buffer 140 via the switch SW3. The output of the buffer 140 is sequentially switched by the demultiplexer 160 and supplied to the source bus bars SBr, SBG, SBb corresponding to the three colors. Further, in order to increase the speed of display operation, a precharge circuit 170 for setting the potential of the source bus line before applying the buffer output to the source bus line is also provided. The portion indicated by reference numeral 200 is a voltage generating device for performing 8-color color display, and is provided with a switch SW11 capable of switching connection between the power source and the ground, and a capacitor C1 disposed between the switch SW11 and the ground. . The switch SW11 further has one switching terminal and is connected to the input side of the multiplexer 160. 0773-A33283TWF; KB05007 11 200905659 Among the outputs of the clock generator and data lock 100, only the most significant bit data D7 is applied to the voltage generating device 200. Further, a control signal CTR for setting switching with driving is also input to the voltage generating device 200. Fig. 2 shows the case of full color display, in which SW1 to SW3 are in an ON state, and SW11 is not connected anywhere. In the state of the above switch, the voltage selector 120 selects two voltages Vn and Vn+1 for displaying the voltage range based on the upper bit of the data code, and outputs it to the 4-bit linear digital analog converter (DAC) 130. The data code is derived from the voltage values taken from the reference voltage generator 110. By using the 4-bit linear digital analog converter (DAC) 130, five capacitors having a unit capacity ratio of 1C, 2C, 4C, and 8C can be connected to the voltage Vn4 Vn+1 to obtain a bit corresponding to the lower 4 bits of the data. Voltage value. This voltage value is maintained within a 4-bit linear digital analog converter (DAC) 130. During pre-charging, in the source busbar pre-charged through the pre-charge circuit 170, the source busbar selected by the demultiplexer 160 is held in a 4-bit linear digital analog converter (DAC). The voltage within 130 is subjected to impedance transformation using buffer 140 and applied to the selected source bus during driving. Fig. 3 is a view showing the same circuit configuration as that of Fig. 2, showing the case of the 8-color color mode. First of all, the data applied to the clock generator and data lock 100 is only 0773-A33283TWF; KB05007 12 200905659 The highest position is D7. When the signal is at the high level, the switch swn is switched to the power supply side. The capacitor H C1 is charged; when the D7 signal is at the low level, the switch swn is switched to the ground side to discharge the capacitor C1. In addition, since either of the switches SW, SW2, and SW3 are turned off, the reference voltage generator 11A, the voltage selector 12A, and the 4-bit linear digital analog converter (DAC) 13 are required for operation. It is cut off, so it is in a state of non-action. After the charge and discharge of the capacitor C1 is completed, the switch swu is connected to the demultiplexer side by the control of the hard disk CTR, and a voltage is applied to any one of the selected three source bus bars, or no voltage is applied. Regarding any of the three source sinks (10), the # can be obtained by performing the same action. Fig. 4 is a circuit diagram for making the second and third figures more clear, and parts corresponding to those of Figs. 2 and 3 are given the same reference numerals. For the sake of simplicity, f simplifies the multiplexer' and the two DACs are organized into the last component for display. On the other hand, the switch SW(1) is controlled by the data D7 for the purpose of the capacitor; the switch swn2 responds to the set mode "drive pure ^ to switch the pair to connect the capacitor to the source bus. In addition, the pre-charge power supply vp C The swi 2 is connected to the second-order busbar connection. The SW12 system is controlled by the pre-charge control number c_PC. The capacitors of the respective source bus bars Lsx are c: 2::: switches SW2 and SW3 are connected. δ color display cut 'No. 0773-A33283TWF; KB05007 13 200905659 The following is a description of the 8-color operation of the present invention using the 6th to 9th; wherein the circuit diagrams shown in Figures 6 to 9 are based on the clock map of Take the first picture of Figure 3 and Figure 4. Below the figure, the first / Γ 1 is in the 8-color color display switching signal M8 control SW3: closing the door: f is broadly defined as the premise, that is, the switch SW2 and the two "close" state. In addition, 'here Although the power supply is 5V', but the pre-charge voltage is 2.5v. As shown in Figure 5, 'a series of actions is to enter the light in a water. During the first half level, it is #4 (4) (Lo) (4) Setting; when the low level (10) becomes the high level (two and the period ' is the control signal. First, in the case of the black display, the supply low level and the control signal CTR is the low level. As shown in Fig. 6, since the switch swii is connected to the ground side to discharge the capacitor ci, and the precharge control signal Cpc is turned on, the source bus can be precharged at a voltage of, for example, 2.5V. As shown in Fig. 7, during the driving period when the control signal CTR becomes the high level (=), the capacitor is connected to the source by the switch swu, L, and the switch SW12 is open (0Pen). At this time, the source busbars, the voltage V〇ut, is the capacitor C1 and the source. The capacitance of the bank 2 capacitor CSB is determined. That is, because of the relationship of C1x〇H-CsbXVpc= (C1 + Csb) xV〇ut, it becomes ν〇υτ (black)=(CSB/ (C1 + CSB) ) XVPC. 〇773-A33283TWF; KB〇5〇〇7 14 200905659 Generation: And 2% to 2.8V, C1,,, V〇ut (black) = 〇.5V. One by one, white display In the case, the supplied data 〇7 is at the high level (4)' while the control signal CTR is at the low level (4), as shown in Fig. 8 'Because the switch SW11 is connected to the power supply side, the capacitor ci is charged' the precharge control signal It is turned on, so the pre-charging of the source bus can be performed under voltage, for example. In addition, as shown in Fig. 9 (4), the control number CTR becomes a high level (the driving period is 't the container C1 by the switch swu The switch SW12 is connected to the source bus bar. At this time, the source bus bar output voltage VOUT is determined by the capacitance value of the capacitor C1 and the capacitor CSB of the source bus bar. That is, because there is C1xVdd +CsbxVpc= (C1 + Csb) χν〇υτ relationship 'so become
V〇ut ( ^ ) - ( Cl/ ( C1 + CSB) ) xVDD+ ( cSB/ ( Cl + CSB) ) xVPC 具體而言，一旦將 Vdd=5v、Vpc=25v、ci 40pF、CSB= l〇pF代入的話，則變成 V〇ut (白）=4.5V。 如此一來，可以進行白黑顯示。 第圖係顯示第2實施例的電路圖，該電路圖以第 6〜9圖所不之電路為基本。其中，DE_Mux表示透過解 多工器160而形成之連接。 0773-A33283TWF;KB05007 15 200905659 在此變形例中，於8色色彩模式下，係設置2個連 接至源極匯流排之電容器，以供白顯示及黑顯示之用， 且依據D7信號的内容而分開使用。 具體來說，對於白顯示而言，D7信號為高準位（Hi) 時藉由開關SW21而將電容器C1與電源VDD連接；對 於黑顯示而言，D7信號為低準位（Lg)時藉由開關SW22 而將電容器C2接地。 在上述結構中，成為下列關係：V〇ut ( ^ ) - ( Cl / ( C1 + CSB) ) xVDD + ( cSB / ( Cl + CSB) ) xVPC Specifically, once Vdd = 5v, Vpc = 25v, ci 40pF, CSB = l〇pF Then it becomes V〇ut (white) = 4.5V. In this way, white and black display can be performed. The figure shows a circuit diagram of the second embodiment, which is based on the circuits of Figs. Among them, DE_Mux represents a connection formed by the demultiplexer 160. 0773-A33283TWF; KB05007 15 200905659 In this modification, in the 8-color color mode, two capacitors connected to the source bus are provided for white display and black display, and according to the content of the D7 signal. Use separately. Specifically, for the white display, when the D7 signal is at the high level (Hi), the capacitor C1 is connected to the power supply VDD by the switch SW21; for the black display, when the D7 signal is at the low level (Lg) The capacitor C2 is grounded by the switch SW22. In the above structure, the following relationship is made:
V〇UT(^) = (C1/(C1 + CSB) )xVDD+ (CsB/(Cl + CSB) ) xVPC V〇UT(S) = (Csb/(C2+Csb) ) xVpc 一，藉由適當選擇^與㈡之值，可以在白顯示與黑 顯示下獨立選擇源極線驅動電壓。 第11圖係繪示根據本發明之第3實施例的電路圖。 在此實％例中，係具有與圖2所示之 200同樣的部分（開關、，η 4路 ^ 、開關SW31 )、以及開關SW32，而未 設有預充電電路。其中，開關SW32在設㈣nm ^高^位時將源極匯流排與電源Vdd連接，而㈣ 準位時將源極匯流排接地。 主在;第U圖之迴路中，以控制信號CTR而言，低準 位又疋1而而準位表示驅動。以資料D7而言，高準 位表不白顯示’而低準位表示黑顯示。 接i“在、不之情況下，由於在設定時開關SW31係I 接地側連接的緣故，因此，電容器C1放電。另一方面: 0773-A33283TWF；KB05007 16 200905659 由於開關SW32係與Vdd連接的緣故，因此，源極匯流 排電谷被以Vdd進行充電。 在驅動時，開關SW31係與源極匯流排側連接，而 開關SW32係不與源極匯流排侧連接，因此，輸出電壓 成為 vOUT (白）=(Csb/ (c1 + Csb) ) χν〇ϋ 〇 在黑顯示之情況下，於設定時，由於開關SW31係 與VDD侧連接的緣故，因此，電容器C1充電。另一方 面開關SW32係將源極匯流排接地，因此，源極匯流 排電容被以VDD進行充電。 於驅動時，由於開關SW31係與源極匯流排側連 接，而開關SW32係不與源極匯流排側連接，因此，輸 出電壓係成為 vOUT (黑)=(C1 / (c1 + Csb) ) xV〇d 〇V〇UT(^) = (C1/(C1 + CSB) )xVDD+ (CsB/(Cl + CSB) ) xVPC V〇UT(S) = (Csb/(C2+Csb) ) xVpc I, by appropriate selection For the values of ^ and (2), the source line driving voltage can be independently selected under the white display and the black display. Figure 11 is a circuit diagram showing a third embodiment of the present invention. In this example, the same portion (switch, η 4 way ^, switch SW31) and switch SW32 as shown in Fig. 2 are provided, and a precharge circuit is not provided. Wherein, the switch SW32 connects the source bus bar to the power source Vdd when (4) nm ^ high ^ bit, and connects the source bus bar to the ground when (4) is at the level. In the loop of the U-picture, in the case of the control signal CTR, the low level is again 疋1 and the level indicates the drive. In the case of data D7, the high level display is not displayed in white while the low level indicates black display. In the case of "I, if not, the switch SW31 is connected to the ground side of the switch, so the capacitor C1 is discharged. On the other hand: 0773-A33283TWF; KB05007 16 200905659 Because the switch SW32 is connected to Vdd Therefore, the source bus bar is charged by Vdd. When driving, the switch SW31 is connected to the source bus side, and the switch SW32 is not connected to the source bus side, so the output voltage becomes vOUT ( White)=(Csb/ (c1 + Csb) ) χν〇ϋ 〇 In the case of black display, since the switch SW31 is connected to the VDD side at the time of setting, the capacitor C1 is charged. On the other hand, the switch SW32 is connected. The source bus bar is grounded, so the source bus bar capacitor is charged with VDD. When driving, since the switch SW31 is connected to the source bus bar side, and the switch SW32 is not connected to the source bus bar side, , the output voltage is vOUT (black) = (C1 / (c1 + Csb) ) xV〇d 〇
由上述輸出電壓之式可知，電容器愈小則愈接近白 顯示輸出，而黑顯示電壓欲接近〇。實際上，一旦將Vdd = 5V、Cl=i.4pF、CSB=10PF 代入的話，則成為 V〇ut (白）=4.505V ν〇υτ (黑）=0.494V ，即便顯著地減少Cl之容量，實施例丨或2也可 能是同樣之動作。由於C1之容量即便變少也良好的緣 故，因此，可以削減電容器形成面積。另外，由於預充 電電路不需要至少8色彩色模式的緣故，因此，可以使 預充電電路簡化。 0773-A33283TWF；KB〇5〇〇7 17 200905659 第12圖顯示第4實施例’係為第2及第3實施例之 組合。也就是說’對白顯示而言，當的信號為高準位時 藉由開關SW41而將電容器C1與電源Vdd連接；另外， 當D7信號為低準位時藉由開關而將電容器〇接 地而且具有開關SW43，未設置預充電電路；其中， 開關S W4 3在設定_，# f料D 7信號為高準位時將源極 匯流排與電源vDD連接’低準位時則將源極匯流排接地。 藉此結構’可以得到在第2及第3實施例得到的效 果。也就是說’除了可以自由選擇電容器Cl&c2之值 外，亦可縮小C1之值。 以上之實施例係不特別限定，熟習此技藝之人士告 可在本發明之範圍内進行任意之變形或置換。 田 【圖式簡單說明】 第1圖係繪示用於從資料碼得到驅動電壓之習知业 型結構的示意圖。 /、 第2圖係繪示本發明之驅動裝置之概略結構的方塊 圖，用於顯示全彩色模式之狀態，其中，前述驅動裝置 :以^全彩色模式與8色彩色模式下對彩色液晶顯示裝 置之源極匯流排施加源極電壓。 第3圖_示在第2圖巾於8色彩色模式下對源極 匯k排施加源極電壓之狀態的示意圖。 、第4圖係㈣概略迴路圖，用以描述與8色彩色模 式下之驅動有關的部份。 0773-A33283TWF;KB05007 18 200905659 第5圖係用於說明第4圖之結構中的作動。 第6圖係緣示概略迴路圖，用以詳細顯示8色彩色 模式下之黑顯示的設定作動。 第7圖係繪示概略迴路圖，用以詳細"色 模式下之黑顯示的驅動動作。 第8圖係繪示概略迴路圖，用以詳細顯示8色彩色 模式下之白顯示的設定作動。 第9圖係繪频略迴_，用崎細㈣8色彩色 f 模式下之白顯示的驅作動動。 第10圖係繪示本發明之驅動裝置之第2實施例的迴 路圖。 第11圖係繪示本發明之驅動裝置之第3實施例的迴 路圖。 第12圖係緣示本發明之驅動裝置之第4實施例的迴 路圖。 ί 【主要元件符號說明】 10〜參照電麗產生器； 20〜4位元開關矩陣； 3 0〜4位元線性數位類比變換器； 110〜參照電壓產生器；120〜電壓選擇器； 130〜4位元DAC; 140〜緩衝器； 150〜參照電流產生器；160〜解多工器； 170〜預充電電路； 200〜8色彩色模式用電壓產生迴路； 〇773-A33283TWF;KB05007 19 200905659It can be seen from the above formula of the output voltage that the smaller the capacitor is, the closer it is to the white display output, and the black display voltage is to be close to 〇. In fact, once Vdd = 5V, Cl=i.4pF, CSB=10PF are substituted, it becomes V〇ut (white) = 4.505V ν〇υτ (black) = 0.494V, even if the capacity of Cl is significantly reduced, The embodiment 丨 or 2 may also be the same action. Since the capacity of C1 is good even if it is small, the capacitor formation area can be reduced. In addition, since the precharge circuit does not require at least an 8-color color mode, the precharge circuit can be simplified. 0773-A33283TWF; KB〇5〇〇7 17 200905659 Fig. 12 shows a fourth embodiment which is a combination of the second and third embodiments. That is to say, for the dialogue display, when the signal is at the high level, the capacitor C1 is connected to the power source Vdd by the switch SW41; in addition, when the D7 signal is at the low level, the capacitor is grounded by the switch and has The switch SW43 is not provided with a pre-charging circuit; wherein, the switch S W4 3 connects the source bus bar to the power supply vDD when the setting _, #f material D 7 signal is at a high level, and the source bus bar is connected when the low level is low. Ground. With this configuration, the effects obtained in the second and third embodiments can be obtained. That is to say, in addition to the value of the capacitor Cl&c2, the value of C1 can be reduced. The above embodiments are not particularly limited, and those skilled in the art can arbitrarily modify or replace them within the scope of the invention. Field [Simple Description of the Drawings] Fig. 1 is a schematic diagram showing a conventional structure for obtaining a driving voltage from a data code. / Figure 2 is a block diagram showing the schematic structure of the driving device of the present invention for displaying the state of the full color mode, wherein the driving device: the color liquid crystal display in the full color mode and the 8-color color mode The source busbar of the device applies a source voltage. Fig. 3 is a view showing a state in which the source voltage is applied to the source sink k row in the 8-color mode in the second pattern. Figure 4 is a schematic circuit diagram (4) for describing the part related to the driving in the 8-color color mode. 0773-A33283TWF; KB05007 18 200905659 Fig. 5 is for explaining the operation in the structure of Fig. 4. Fig. 6 is a schematic circuit diagram showing the setting operation of the black display in the 8-color mode. Figure 7 is a schematic circuit diagram showing the driving action of the black display in the "color mode. Fig. 8 is a schematic circuit diagram showing the setting operation of the white display in the 8-color mode in detail. The ninth picture is a slight _ of the picture frequency, and is driven by the white display in the fine (four) 8-color color f mode. Fig. 10 is a circuit diagram showing a second embodiment of the driving device of the present invention. Fig. 11 is a circuit diagram showing a third embodiment of the driving device of the present invention. Fig. 12 is a circuit diagram showing a fourth embodiment of the driving device of the present invention. ί [Main component symbol description] 10~ reference electric generator; 20~4 bit switch matrix; 3 0~4 bit linear digital analog converter; 110~reference voltage generator; 120~ voltage selector; 130~ 4-bit DAC; 140~buffer; 150~reference current generator; 160~demultiplexer; 170~precharge circuit; voltage generation loop for 200~8 color mode; 〇773-A33283TWF;KB05007 19 200905659
Cl、C2〜電容器； CPC〜預充電控制信號； C SB〜源極匯流排電容為'， CTR〜控制信號；Cl, C2~ capacitor; CPC~ precharge control signal; C SB~source busbar capacitance is ', CTR~ control signal;
Lsx、SBr、SBG、SBb〜源極匯流排； M8〜8色彩色顯示切換信號； SW卜 SW2、SW3、SW1 卜 SW12、SW2 卜 SW22、SW3 卜 SW32、SW41、SW42、SW43〜開關； VDD〜電源； Vpc〜預充電電源。 0773-A33283TWF;KB05007 20Lsx, SBr, SBG, SBb ~ source bus; M8 ~ 8 color display switching signal; SW SW SW2, SW3, SW1 SW SW12, SW2 SW SW22, SW3 SW SW32, SW41, SW42, SW43 ~ switch; VDD ~ Power supply; Vpc ~ pre-charge power. 0773-A33283TWF; KB05007 20