TWI377549B - Pixel, display panel and driving method thereof - Google Patents

Description

1377549 P061106SEZ1TW 23519twf.doc/p IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a display using a fourth-order drive ("(5) addressmg) technology" and particularly relates to a fourth-order transfer technology _Reversal-driven pixel, display surface

[Prior Art] ^ In mobile devices, especially mobile phones, personal mobile assistants (a) as her nt, PDA), etc., the power source is usually the charging pen pool 'example pure battery U power, if the power consumption of the mobile device is too Shang, the financial system will be closed, called the acceptance of low-lying people. Coupled with the sister-in-law (4), the awareness of energy conservation has risen, so electronic products are demanding energy-saving effects to reduce power consumption.

The liquid crystai dispiay (LCD) of the mobile device is the main source of power consumption. If the power consumption required for the LCD display is effectively reduced, the battery life can be effectively improved. Currently, more and more mobile devices use an active matrix liquid crystal display (acdve matrix liquid crysta) [, aMLCD) to reduce the power consumption of the backlight. In terms of driving, the fourth-order driving technology is used to drive the pixel electrode, and the driving waveform of the gate is directly changed by the scanning waveform of the gate to reduce the driving polarity of the pixel to reduce the power consumption of the source driver. . However, the conventional fourth-order driving technique can only be applied to a display using a driving method in which column inversion or line inversion is performed, which cannot be matched with dot inversion. P061106SEZ1TW 23519twf.doc/p [Summary of the Invention] ▲ The purpose of this issue (4) is to provide a kind of display panel, using the layout method of 昼素死错' to make the four-p drive technology applicable to dot reversal 'to reduce power consumption. The purpose of this month is to provide a driving method for the display panel, which is a driving method of the fourth-order driving technology and a dot inversion driving method, and the power consumption of the driving device is low. The invention provides a display panel comprising at least a first-order element, a first quart: and a second inter-pole line, wherein the first elementary column has a plurality of drawing-forms, and is divided into a plurality of A pixel and a plurality of 第-昼-与 and the second element are arranged at intervals, each of the elements includes a body, a liquid crystal capacitor and a compensation capacitor, and the liquid crystal capacitor has a gate-gate light The wire of the transistor connected to the first pixel is connected to the other end of the capacitor; the gate of the first gate of the second gate of the gold. The first element and the polarity: the polarity of the driving force is opposite. When the second element is a positive element, the output of the line is a positive driving waveform, and when the second element is 'I & driving, the first gate The output of the line is a negative drive waveform. In the column, the display panel of the above-mentioned display panel further includes a second scorpionfish, a scorpion scorpion-gate line, wherein the second sputum column has a plurality of third rafts 2, = 昼 昼 昼 与 and the above The four pixels are the compensation capacitors of the fourth element. Wherein, the second 昼" a 〃 adjacent" and the third 昼 与 and the fourth 昼 1 1377549 P061106SEZ1 TW 23519 twf.doc/p are opposite in driving polarity, when the fourth element is positively driven The wheel of the first gate line is a positive driving waveform, and when the fourth element is driven by a negative polarity, the output of the second gate line is a negative driving waveform. In an embodiment of the invention, the above The first pixel and the third pixel are odd pixels, and the second pixel and the fourth pixel are even pixels. In another embodiment of the invention, the first and third cells are even The second element and the fourth element are odd numbers. In the present invention, the negative driving waveform includes the first and second periods. In the first period, the first voltage is obtained. Level, in the second period 'has a second voltage level, the second voltage level is less than the first pressure level: and greater than - the reference voltage. wherein the second period is after the first period, after the second period, the negative drive The waveform returns to the reference voltage. In an embodiment of the invention, the above is positive The driving waveform includes a first period: a first period. In the first period, the positive driving waveform has a first voltage level 'and the engraving-electrical suspension A is at a secret voltage level, and the third period After the first period, and after the second period, the negative driving waveform is restored to the reference voltage. The driving unit Tr is implemented, wherein when the second pixels are positive polarity boats, the second gate The output of the line is the negative driving waveform. When the first element is driven by the negative polarity, the rotation of the first closed-circuit line is: driving the present invention to provide another element, including the S-band A and the electric cymbal. The potting liquid and the electric capacitor, the compensation capacitor and the electric body, wherein the compensation capacitor and the liquid crystal capacitor have one end, and the other end of the liquid 1377549 P〇61106SEZ1TW 23519twf.doc/p crystal capacitor is coupled to the common voltage, compensation Slightly - in the first - gate. The transistor is connected to the gate of the data line and the light-handed body is connected to the second gate line, between the first end of the i-electrode, the adjacent line of the electro-crystal line and the first Two gate

From the county point of view, the special (four) out - the type of panel ^ ^ ^ panel includes a plurality of touch lines and a plurality of prime elements including the transistor, liquid crystal capacitors to pay electricity =; capacitance and compensation capacitors have - common terminal, compensation capacitor : the gate of the first gate line 'transistor is coupled to the second gate 2 to include the following steps: sequentially scanning the _ lines; when the first _ = = negative body waveform; and when the first picture The negative polarity = pole J, the second line of the wheel is the negative drive waveform 'the output of the second closed line is the negative drive n. The present invention is a staggered layout of the structure, which can be directly placed.

It is applied to the display with dot inversion to reduce the power consumption of the source drive β and Filker (please add Chinese translation). The above and other objects, features and advantages of the present invention will become more apparent from [Embodiment] _ First f t FIG. 1 is a circuit diagram of a pixel according to an embodiment of the present invention. Alizarin 100 includes liquid crystal capacitor CLC, compensation capacitor CST, and transistor Ml, parasitic 8 1377549

P061106SEZ1TW 23519twf.doc/p =CGD indicates that the closed end of the transistor M1 and the source (none) of the capacitor CST have a common terminal with the liquid crystal capacitor, and the other end of the CLC is connected to the common voltage vc〇m,

The other end of the gate is connected to the gate line 〇 曰 1 valley CST continued 〆 t its gate is the gate line Gm. Closed Green = i, Gm is the adjacent gate line in the layout of the display panel. When the gate 3G M _! is enabled, the interpole signal will pass through the compensation capacitor c s τ

When the gate line Gm is enabled, its gate signal generates a feedthrough (Ldafter) electric dust on the liquid crystal capacitor CLC via the parasitic capacitance CGD. In other words, the polarity of the driving voltage on the liquid crystal capacitor CLC can be affected by the interpolar signal waveform on the closed line. Second embodiment

With the above-described pixel structure, the layout in a staggered configuration can be applied to the dot inversion display, and Fig. 2 is an electrical diagram of the display panel according to the second embodiment of the present invention. The display panel 2 includes a pixel column psi, PS2 (the remaining pixel arrays are not shown), and each of the pixel columns PS1 and PS2 includes a plurality of pixels. The pixel column PS1 includes pixels 211 to 214 (the remaining It is shown that the halogen column PS2 includes halogens 221 to 224 (the rest is not shown). The gate lines GM-i, GM, GM+1: ^ data lines DL1 DL DL5 are coupled to the pixels 211 214 214, 221 224 224. In order to match the driving method of dot inversion, the coupling states of adjacent pixels in the same pixel column are different. Taking the pixel column PS2 as an example, the pixels 221 to 224 in the pixel column PS2 are divided according to the order of arrangement. The odd elements 221, 223 and the even elements 222, 224, the odd elements 221, 223 and the even elements 222, 9 1377549 P061106SEZ1TW 23519twf.doc/p 224 are arranged in a spaced manner. The gate of the transistor of the odd-numbered elements 221 and 223 is coupled to the gate line Gm, and the other end of the compensation capacitor CST is connected to the gate line GM_i; the gate of the transistor of the even-numbered elements 222, 224 The pole is coupled to the gate line GM+1, and the compensation capacitor CST is coupled to the Gm. The pixel column PS1 is correspondingly coupled between the gate lines, and the positive integer ' is used to identify the gate line in the display panel. In the dot-inversion driving mode, the driving polarities of the odd-numbered pixels and the even-numbered pixels are different, and the polarities of the adjacent pixels are different. During scanning, each element is affected by the current and previous gate lines and its driving polarity is changed. Taking the prime column PS1 as an example, when the even pixels 212 and 214 are positively driven, the gate line (the output of the gate 1 is a positive driving waveform, and the output of the gate line GM is a negative driving waveform to make an even number The halogen elements 212 and 214 generate a positive polarity drive. When the even elements 212 and 214 are negatively driven, the output of the gate line Gm+ is a negative drive waveform, and the output of the gate line is a positive drive = waveform. The even-numbered halogens 212 and 214 are driven to generate a negative polarity. In other words, the output waveform of the gate line connected to the pixel via the compensation capacitor is the same as the axis of the pixel, and the fourth line of the battery is difficult. The lower-column element drives the polarity and adjusts its output waveform. Regarding the above-mentioned gate line, please refer to the diagram and FIG. 3A for the positive driving waveform diagram according to the embodiment, and FIG. 3B is based on the present embodiment. As shown in the figure, when the gate output from the gate line is the JL drive waveform, the gate signal has the _ period period, and the second period T2' rises from the reference voltage % to the level in the _ period T1. Vb and in the second period T2, the voltage level % is reduced to V4, I377549 P〇611〇6SEZlTW 235 19twf.doc/p: After the period T2 of f, the gate signal is restored to the reference voltage V3. The electric gong 35 is used to turn on the poor material in the corresponding element, and also through the parasitic capacitance. The liquid crystal is energized repeatedly. In the second period Τ2, when the gate is restored to the reference voltage V3 by the ,2, it will be merged into the liquid valley by the compensation power i, and the bias of the liquid crystal capacitor is pulled up. Forming a positive polarity drive. = Figure 3B does not. When the gate signal output from the gate line is a negative drive waveform, the interpole signal will rise in the second period τ2 during the first period, T1. The gate signal will be the voltage bit %. In the first period / the middle ": two = main = to the reference voltage *. , . ^ The pressure level vi is mainly used to open the corresponding crystal in the loyalty to write people The data, also through the parasitic capacitance: the feedthrough voltage is generated on the liquid crystal capacitor. The second period == voltage level V2 returns to the reference voltage v3 _, the capacitor 'and the step-down liquid crystal capacitor she pulls out the wave : Ming: Dan 212 as an example of 'matching the gate line ~ 1, ~ round out wave pure display panel fine drive France. Please also refer to FIG. 2

If4 is a driving waveform diagram according to the second embodiment of the present invention. In Γ Γ 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二The driving polarity of the halogen element 212 is determined by the voltage across the voltage of the pixel plate. The driving method of the present embodiment is taken as an example to illustrate the driving method of the display panel 2〇〇, so the drawing 11 1377549 P061106SEZ1TW 23519twf The driving polarity of .d〇c/p 212 is different in different kneading planes. First, when the halogen 212 is driven by the negative polarity, the gate signal s is the negative drive waveform ' and the gate signal SGm is the positive drive waveform. When the = SGm.J rises to the voltage level V1, the pixels are torn off: the primes 211, 213 are turned on and the even pixels 212, 214 are generated by the compensation power: cst, so the voltage of the pixel is pw The rising gate signal sgm is enabled to turn on the odd number '223 on the pixel column pS2'. The pixel voltage PW will also be due to the gate signal: ', the feed signal voltage generated by the rise of the signal SGm is decreased. When the gate gate Pseudo-No. 8 (^1 enters the reference voltage V3 from the voltage level V2), the pixel voltage pw will fall further and form a negative drive polarity. Finally, when the gate signal SGm returns to the reference voltage v, The pixel voltage PW will be slightly increased due to the feedthrough voltage, such as the region. When entering the next plane, the driving polarity of the pixel will change, and the drawing will change from negative driving polarity to positive driving polarity. , is the positive drive waveform, and the gate signal SGm is the negative drive wave η == for the gate signal _ and rises, " Γ decreases and falls, at this time will also receive the idle letter: Μ ~ 曰. The pole signal sgm] is reset by the voltage level V4 n π - the MW will rise accordingly, then the gate U sgm The pressure V3 is reduced to the reference cake v PW is affected by it* and then slightly increased, such as the regional sample-spear in the region 410, 420, the halogen voltage pw is due to the closed-circuit signal (6) 12 1377549 P061106SEZ1TW 23S19twf.doc/p The total surface voltage and the total falling voltage and the total rising voltage generated by the feedthrough effect of the gate signal s〇M are mainly affected by the voltage change of the gate signal, the parasitic capacitance CGD, the liquid crystal capacitance CLC, and the compensation capacitance CST. 5B is an enlarged view of a region according to the regions 41〇, 42〇 in FIG. 4. As shown in FIG. 5A, the total falling voltage is equal to (dvl+dV2_dV3), and as shown in FIG. 5B, the total rising voltage is equal to (_dV4+dV5_dV6). With the above circuit parameter value and the voltage change of the gate signal, the following equation can be summarized: dVl + dV2-dV3 = {VG *CGD + VEl* CST}/[CST + CLC + CGD] -dV4 + dV5- dV6 = {-VG* CGD + VE2 * CST}l[CST + CLC + CGD] where CST, CLC, and CGD represent the compensation capacitor, liquid crystal capacitor, and gate (source) parasitic capacitance of the transistor, respectively. The design (layout) of the elementary structure is adjusted; VE1 represents the voltage level V2 The difference from the reference voltage V3, VE2 represents the difference between the reference voltage V3 and the electric dust level V4, which can be adjusted by the waveform of the gate signal. Therefore, by adjusting the component parameters in the pixel structure and The gate signal can change the driving polarity of the pixel, thereby reducing the power consumption of the source driver. In the dot-inversion driving mode, the even-numbered elements (e.g., 212, 214) in the pixel column PS1 have the same driving polarity. The driving method is as described above for the driving mode of the pixel 212, and will not be described again. However, the driving polarities of the odd pixels (such as 211, 213) in the pixel column PS1 are opposite to those of the even pixels 212 and 214, and only the output waveforms of the gate lines Gm-i and Gm-2 need to be adjusted correspondingly. Technique 13 1377549 P061106SEZ1TW 23519twf.doc/p The person skilled in the art has a general knowledge. The driving waveforms of the remaining gate lines should be easily inferred by the disclosure of the present invention, and will not be described here. The third embodiment of the JL integrates the above embodiments, and the present invention is directed to a driving method for a display panel, which is applicable to the display panel 200. The driving method includes the following steps: First, the step S610 sequentially scans the open lines in the display panel 200. Then, in step S620, when the pixel is positively driven, the output of the second gate line is a positive driving waveform, and the output of the second gate line is a negative two-motion waveform; in step S630, When driving for the negative polarity, the rotation of the first gate line is a negative drive waveform, and the rotation of the second gate line is a negative drive waveform. Therefore, the first gate line represents the last gate line, and the coupling voltage is generated to the currently scanned pixel via the compensation capacitor, and the second gate line represents the currently scanned gate line, which is mainly used to turn on the pixel. The transistor is also coupled to the pixel of the next pixel column via the compensation capacitor. For the rest of the above-mentioned driving methods, please refer to the descriptions of the first and second embodiments above. Those skilled in the art have the knowledge of the present invention. According to the disclosure of the present invention, 4/t L. 丄 "J is easily inferred, and is not described here. In summary, the present invention proposes a new panel pixel layout method, so that the fourth-order driving technology can be directly applied to the dot inversion display, thereby reducing the power consumption of the dynamic circuit. - ° Although the present invention has been a preferred embodiment The above disclosure is not intended to limit the invention, and any one skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the patent application is defined as 14 1377549 P061106SEZ1TW 23519twf.doc/p • BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a pixel according to an embodiment of the present invention. FIG. 2 is a diagram showing a second embodiment of the present invention. 3A is a positive driving waveform diagram according to the present embodiment. Fig. 3B is a negative driving waveform diagram according to the present embodiment. Fig. 4 is a second driving diagram according to the present invention. Driving diagram of the embodiment. Lutu 5A is an enlarged view of the area according to the area 410 in Fig. 4. Fig. 5B is an enlarged view of the area according to the area 420 in Fig. 4. Fig. 6 is a driving according to the third embodiment of the present invention. Flow chart of the method. [Main component symbol description] 100: Alizarin 200: Display panel DL1 to DL5: Data line Gm-2 to GM+1: Gate line PS1, PS2: Alizarin column • 211 to 214, 221 〜 224: pixel CLC: liquid crystal capacitor CST: compensation capacitor M1: transistor CGD: parasitic capacitance T1: first period • T2: second period V3: reference voltage 15 1377549 P061106SEZ1TW 23519twf.doc/p VI~V4: voltage level PW: halogen voltage VCOM: common voltage SGM_!, SGM: gate signal VE1: voltage difference VE2: voltage difference S610~S630: steps

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Claims (1)

1377549 _ w July July must be corrected page 101-7-18 X. Patent application scope: 1. A display panel comprising: a first elementary column having a plurality of elements, according to the arrangement of the elements The sequence is divided into a plurality of first pixels and a plurality of second pixels, the first pixels are spaced apart from the second pixels, and each of the elements includes a transistor, a liquid crystal capacitor and a compensation capacitor having a common terminal with the liquid crystal capacitor; a first gate line coupled to the gate of the first pixel of the first pixel and coupled to the second pixel The other end of the compensation capacitor; and a second gate line coupled to the gates of the second halogen transistors; wherein the first pixels and the second pixels are in the same plane The driving polarity is opposite. When the second pixels are positively driven, the output of the first gate line is a positive driving waveform, wherein the positive driving waveform has a reference voltage, and the positive driving waveform includes a positive Driving the first period of the waveform and a second period of the positive driving waveform, wherein The positive driving waveform is maintained at the reference voltage during a period other than the first period of the positive driving waveform and the second period of the positive driving waveform, and when the second pixels are negatively driven, the first gate line The output is a negative driving waveform, wherein the negative driving waveform has the reference voltage, and the negative driving waveform includes a negative driving waveform first period and a negative driving waveform second period, wherein the negative driving waveform is in the negative driving waveform A period and a period other than the second period of the negative drive waveform are maintained at the reference voltage. 2. The display panel as claimed in claim 1, further comprising: a second halogen column having a plurality of third halogens and a plurality of fourth turns 17 1377549 101-7-18 (four) January The δ-day correction replaces the page element, the third element is spaced apart from the fourth element, the third element of the transistor is coupled to the second gate line; and a third gate line And a compensation capacitor coupled to the fourth pixel; wherein the second pixel column is adjacent to the first pixel column, and the third pixels are in the same picture as the fourth pixels The driving polarity is opposite. When the fourth halogen is positively driven, the output of the second gate line is the positive driving k shape, and when the fourth halogen is negative driving, the second gate The output of the polar line is the negative drive waveform. 3. The display panel of claim 2, wherein the first pixels and the third pixels are odd pixels, and the second pixels and the fourth pixels are even numbers Prime. 4. The display panel of claim 2, wherein the first element and the third element are even elements, and the second element and the fourth element are odd numbers Prime. 5. The display panel of claim 1, wherein the negative driving waveform comprises: a first driving period of the negative driving waveform having a first voltage level; and a second period of the negative driving waveform having a first a second voltage level, the second voltage level being less than the first voltage level and greater than the reference voltage; wherein the second period is after the first period, after the second period, the negative driving waveform is recovered To the reference voltage. 6. The display panel of claim 1, wherein the positive driving waveform comprises: the first driving period of the positive driving waveform, having a first voltage level, the 18th month; the δ day correction replacement page 101- 7-18: a voltage level is greater than the reference voltage; and a second period of the positive driving waveform has a third voltage level, the second voltage level being less than the reference voltage; wherein the second period is at the After a period, and after the second period, the negative drive waveform returns to the reference voltage. The display panel of claim 1, wherein in each of the pixels, the transistor is secreted between the data line and the common terminal, and the other end of the liquid crystal capacitor is coupled to A common voltage. & 8. The application panel of claim 1, wherein when the second pixels are positively driven, the output of the second gate line is the driving waveform, 'when the first When the two pixels are driven by the negative polarity, the output of the first gate line is the positive drive waveform. Η2: driving method of the seed plate' The display panel includes a plurality of gate lines and a plurality of pixels, and the pixels of the pixels include: a body, a liquid crystal capacitor and a compensation capacitor, and the liquid crystal The capacitor and the complement=having-shared terminal's other end of the compensation capacitor are connected to the first gate of the transistor, and the gate is coupled to a second gate. The following steps are performed: Some gate lines; when the first and the second elements are positively driven, the first interrogation line: a positive driving waveform, and the output of the second second gate line is a negative driving waveform, and the positive driving The waveform has a reference voltage, and the positive drive waveform includes a positive drive waveform first-period and a positive drive waveform second pass, wherein the positive drive waveform is in the positive drive waveform first period and the positive drive waveform second period year 1 On the 8th of the month, the period 1 of the modified replacement page 101-7-]8 is maintained at the reference voltage; and for the =: the open pixel is the negative polarity drive, the output of the first gate line is the 兮_gate line The output is the negative drive waveform, the negative drive has the reference voltage, and the negative Motion waveform comprising - a movable during H and - in the negative rotation drive waveform during the second scale depends Discussion eds San Bu ==. 'Driver's special (4) 9 items of the method, in which the negative 2 negative drive waveform - during the period - has the - first electric house level; 2 negative drive waveform during the second period, with a first pressure level - 1 bit quasi? After the first voltage level is greater than the reference voltage f, the second period is after the first period, and during the second period, the negative driving waveform is returned to the reference voltage. Driving full-time (4) 9 items of Lai Zhihe Yang, wherein the positive, positive driving waveform first period has a -first voltage level, the voltage level is greater than the reference voltage; and, during the second period of the positive driving waveform, has a third voltage The level, a voltage level is less than the reference voltage; between ί== after the first period, and after the second period, the negative driving waveform returns to the reference voltage. 20