200903428 ^υο 1 iuosc-^ι a 23519twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種應用四階驅動（four level addressing)技術之顯示器，且特別是關於一種可配合四階 驅動技術與點反轉驅動方式之晝素、顯示面板與其驅動方 法。 【先前技術】 p 對於行動裝置’尤其手機、個人行動助理（personal digital assistant ’ PDA )等而言，其電力來源通常為充電 電池，例如链電池。電池電力有限，若行動裝置的功率消 耗太南’則其使用時間將會受到限制，而降低消費者的接 爻度。再加上在歐盟環保條款的訂定，使得節能意識抬頭， 因此電子產品紛紛要求具有節能功效，以降低功率消耗。 行動裝置的液晶螢幕（liquid cryStal display, LCD)通 常為主要的功率消耗來源，若能有效降低液晶螢幕顯示所 , 需的功率消耗，則可以有效提高電池的使用時間。目前， 1 有愈來愈多的行動裝置使用主動矩陣液晶顯示器（active matnx liquid crystd，AMLCD )來減少背光的功率消耗。而 在驅動方面，則使用四階驅動技術來驅動晝素電極，利用 閘極的掃描波形以耦|合與饋通（feedthrough)的方式直接 改.交晝素的驅動極性，以降低源極驅動器的功率消耗。 但習知的四階驅動技術僅能使用在列反轉或行反轉 的顯不器中，無法配合點反轉之驅動方式應用於顯示器上。 200903428 1 ^ 23519twf.d〇c/p 【發明内容】 本發明的目的之一是在提供—種顯示面板，利用畫素 父錯的佈局方式，使四階驅動技術可以適用於點反轉之顯 示器，以降低功率消耗。 本發明的目的之一是在提供一種顯示面板之驅動方 法，結合四階驅動技術與點反轉之驅動方式，以降低顯示 益驅動裝置的功率消耗。 ) 本發明提出—種顯示面板，至少包括第〆畫素列、第 一閘極線以及第二閘極線，其中第一晝素列具有複數個晝 素，根據畫素的排列順序，分為複數個第一畫素與複數個 第2晝素，第一晝素與第二晝素為間隔排列，每—畫素包 括電晶體、液晶電容與補償電容，補償電容與液晶電容具 有一共用端；第一閘極線耦接於上述第一畫素之電晶體之 閘極，並耦接於第二晝素之補償電容之另一端；第二閘極 ，耦接於上述第二畫素之電晶體之閘極。其中第—畫素與 第一晝素在同一晝面中之驅動極性相反，當第二晝素為正 極性驅動時，第—閘極線的輪出為正驅動波形，當第二晝 素為負極性驅動時，第一閘極線的輸出為負驅動波形。 在本發明一實施例中，上述之顯示面板更包括第二晝 二列^及第二閘極線，其中第二晝素列具有複數個第三晝 數個第四晝素’上述第三晝素與上述第四晝素為間 =列’上述第三晝素之電晶體紐於第二閘極線，而第 —閘極線耦接於上述第四晝素之補償電容。1中，圭 素列與第-晝素列相鄰，且上述第三晝素與^述第四= 200903428 jruonuoist:乙 1 上 23519twf.doc/p 在=晝M之驅動極性相反’當上述第四晝素為正極性 弟二閘極線的輸出為正驅動波形，當上述第四晝 動ϊ，第二閘極線的輪出為負驅動波形。一 *勃貝施例中，上述之第—晝素與*三晝素為 可數晝素，而弟二晝素與第四晝素為偶數晝素。一 在本發明另-實施例中，上述之第—晝素盘第三*素 為偶數晝素’而第二晝素與第四晝素為奇數晝素。一、 門愈η;二::例中，上述之負驅動波形包括第-期 間與弟一綱。㈣巾’具有第—電壓鱗，在第 二期間中’具有第二電壓位準，第二電壓鱗小於第一電 壓位準，並大於-基準電壓。其中第二朗在第期間之 後’在弟二期之後，負驅動波形回復至基準電壓。 在本發明-實施例中，上述之正驅 間與第二期間。在第―湘鬥由Έsr.^ ^ ,.^ g _ ^ , B中，正驅動波形具有第一電壓 位準’且該電壓位準大於該基準電壓；在第二期間中， 波！ί有第三電壓位準，且該第三電壓位準小於基 2 期間在第一期間之後，且在第二期間 之後，該負驅動波形回復至該基準電壓。 實施例中，其中當該些第二晝素為正極性 驅動k，5,弟—祕線的輸出為該負驅動波形，當該些第 二晝素為負極性驅動時，該第-閘極線的輸出為該正驅動 波形。 本提出-種晝素’包括液晶電容、補償電容以 及電曰曰體’其中補償電容無晶電容具有—翻端，且液 200903428 隊乙 uw 235l9twf.d〇C/p 晶電容的另一端耦接於共同電壓，補償带六 於第-閘極線。電晶體耦接於資料線‘：：：另-端耦接 體的閘極耦接於第二閘極線，其中 叫端之間，電晶 線相鄰 、中弟-間極線與第二閘極 、從另一觀點來看，本發明提出一種顯示 决，該顯示面板包括複數條閘極線與複數個栈之驅動方 素中之第一晝素包括電晶體、雷 思素，該些晝 ，補償電容具有一共用端，賞電容，液晶 第—閘極線，電晶體的閘極耦接於 另〜端耦接於 包括下列步驟：依序掃描該些閘極線了; f線，驅動方法 性驅動時’第-閘極線的輸出為正驅畫素為正極 負驅動波形；而當第—晝素為負^性極線 動波形。 閘極線的輪出為負驅 本發明因採用畫素交錯的佈局方式，因 ^動技術應用在點反轉的顯示器上，進而物降 ^動器的功率消耗與Filker(請補充中文譯名）。 為讓本發明之上述和其他目的、特徵和優點能更明顯 董，下文特舉本發明之較佳實施例，並配合所附圖式， 作詳細說明如下。 【實施方式】 戈施例 勺圖1為根據本發明一實施例之畫素電路圖。晝素100 I括液晶電容CLC、補償電容CST以及電晶體Ml，寄生 200903428 ruonuo^ix^ 23519twf.doc/p 電容C G D表示電晶體M1的閘極與源（汲）極 電容。補償電容CST與液晶電容具有—制端，^曰/容 CLC的另—端耦接於共同電壓VCOM，而補償電^曰=ST 的另-端_接於閘極線Gm i，電晶體奶輪於^料線 DL與上述共用端之間，其閘極_接於閘極線Gm。、閘極 線GM·!、GM在顯示面板的佈局中為相鄰的閘極線。 f 當閘極線Gm-i致能時’閘極信號會經由補償電容CST 耦合至液晶電容，而當閘極線Gm致能時，其閘極信號會 經由寄生電容CGD而在液晶電容CLC上產生饋通 through )電壓。換言之’經由閘極線Gm_ ! 〇μ上的閘極信 5虎波形’即可影響液晶電容CLC上的驅動電堡極性。 第二實施例 利用上述之晝素結構，配合交錯配置的佈局方式可應 用於點反轉之顯示器’圖2為根據本發明第二實施例之顯 示面板之電路圖。顯示面板200包括晝素列psi、PS2 (其 餘畫素陣列未繪示）’每一晝素列PS1、PS2包括複數個 畫素’其中晝素列PS1包括晝素211〜214(其餘未繪示）， 晝素列PS2包括晝素221〜224 (其餘未繪示）。閘極線 Gm-i、Gm、GM+1與資料線DL1〜DL5對應耗接於晝素211 〜214 、 221〜224 。 為配合點反轉之驅動方式，在同一晝素列中相鄰的晝 素的耦接狀態不同，以晝素列PS2為例，晝素列PS2中之 畫素221〜224依照排列順序分為奇數晝素221、223以及 偶數晝素222、224，奇數晝素22卜223與偶數晝素222、 200903428 ruoiiuo^^i l \V 23519twf.doc/p 224以間隔方式配置。其中 閑極耦接於閘極線Gm，而复j—、223的電晶趙的 Γ —京222、224的電晶體的閘極耦200903428 ^υο 1 iuosc-^ι a 23519twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a display using a four-level addressing technique, and more particularly to a It is compatible with the fourth-order drive technology and the dot-reverse drive method, the display panel and its driving method. [Prior Art] p For mobile devices, especially mobile phones, personal digital assistants (PDAs), etc., the source of power is usually a rechargeable battery, such as a chain battery. Battery power is limited, and if the power consumption of the mobile device is too low, the usage time will be limited, and the consumer's access will be reduced. Coupled with the establishment of environmental protection clauses in the EU, the awareness of energy conservation has risen, so electronic products have demanded energy-saving effects to reduce power consumption. The liquid cryStal display (LCD) of the mobile device is usually the main source of power consumption. If the power consumption of the LCD screen is reduced, the battery life can be effectively improved. Currently, 1 more and more mobile devices use active matnx liquid crystd (AMLCD) to reduce the power consumption of the backlight. In terms of driving, the fourth-order driving technology is used to drive the pixel electrode, and the driving waveform of the gate is directly changed by the coupling waveform and the feedthrough to reduce the driving polarity of the bismuth element to reduce the source driver. Power consumption. However, the conventional fourth-order driving technique can only be used in the display of column inversion or line inversion, and cannot be applied to the display in conjunction with the dot inversion driving method. 200903428 1 ^ 23519twf.d〇c/p [Invention] One of the objects of the present invention is to provide a display panel, which utilizes the layout mode of the pixel parent to make the fourth-order driving technology applicable to the dot inversion display. To reduce power consumption. SUMMARY OF THE INVENTION One object of the present invention is to provide a driving method for a display panel in combination with a fourth-order driving technique and a dot inversion driving method to reduce the power consumption of the display benefit driving device. The present invention provides a display panel comprising at least a second pixel column, a first gate line, and a second gate line, wherein the first pixel column has a plurality of elements, and is divided according to the order of the pixels. The plurality of first pixels and the plurality of second pixels, the first element and the second element are arranged at intervals, each of the pixels includes a transistor, a liquid crystal capacitor and a compensation capacitor, and the compensation capacitor and the liquid crystal capacitor have a common end The first gate line is coupled to the gate of the first pixel and coupled to the other end of the second pixel; the second gate is coupled to the second pixel The gate of the transistor. The driving polarity of the first pixel and the first pixel in the same plane is opposite. When the second pixel is driven by the positive polarity, the rotation of the first gate line is a positive driving waveform, and when the second pixel is When driving with a negative polarity, the output of the first gate line is a negative drive waveform. In an embodiment of the invention, the display panel further includes a second second column and a second gate line, wherein the second pixel column has a plurality of third plurality of fourth pixels 'the third layer And the fourth pixel is a second gate line of the third pixel, and the first gate line is coupled to the compensation capacitor of the fourth pixel. In 1 , the guillotine column is adjacent to the first 昼 昼 , column, and the third 昼 与 ^ = = = 200903428 jruonuoist: B 1 on the 23519 twf. doc / p in the opposite polarity of the driving force of 昼 M 'When the above The output of the quadruple element is a positive driving waveform of the positive polarity second gate line. When the fourth driving state is 上述, the rotation of the second gate line is a negative driving waveform. In the case of the Bobbe, the above-mentioned 昼- and 昼- 昼 are a countable 昼, while the diterpene and the fourth 为 are even. In another embodiment of the present invention, the third element of the first-dimensional disk is an even-numbered element and the second element and the fourth element are an odd-numbered element. First, the door is more η; two:: In the example, the above negative driving waveform includes the first period and the younger one. (4) The towel 'has a first voltage scale, in the second period 'having a second voltage level, the second voltage scale being less than the first voltage level and greater than the - reference voltage. The second lang is after the second period. After the second phase, the negative drive waveform returns to the reference voltage. In the present invention-embodiment, the above positive drive and the second period. In the first - Xiangdou Έ sr. ^ ^ , .^ g _ ^ , B, the positive drive waveform has a first voltage level ' and the voltage level is greater than the reference voltage; in the second period, the wave! There is a third voltage level, and the third voltage level is less than the base period 2 after the first period, and after the second period, the negative driving waveform is restored to the reference voltage. In an embodiment, when the second pixels are positive polarity driving k, 5, the output of the brother-myster is the negative driving waveform, and when the second pixels are driven by the negative polarity, the first gate The output of the line is the positive drive waveform. The present invention provides a liquid crystal capacitor, a compensation capacitor, and an electrical body, wherein the compensation capacitor has a flip-flop, and the other end of the liquid crystal 200903428 team b uw 235l9twf.d〇C/p crystal capacitor is coupled. At a common voltage, the compensation band is six to the first gate line. The transistor is coupled to the data line '::: the other end of the coupling body is coupled to the second gate line, wherein the terminals are called, the electro-crystal line is adjacent, the middle-dipole line and the second line Gate, from another point of view, the present invention provides a display, the display panel includes a plurality of gate lines and a plurality of stacks of driving elements, the first element includes a transistor, Resin, the 昼, The compensation capacitor has a common terminal, a capacitor, a liquid crystal first gate line, and a gate of the transistor coupled to the other end is coupled to the following steps: sequentially scanning the gate lines; f line, driving method When the driver is driven, the output of the first gate line is the positive drive negative waveform, and the first pass is the negative polarity waveform. The rotation of the gate line is a negative drive. The present invention adopts a pixel-interlaced layout method, and the power consumption is applied to the display of the dot-reversal display, and the power consumption of the object is reduced with Filker (please add Chinese translation) . The above and other objects, features, and advantages of the present invention will be apparent from the description of the appended claims. [Embodiment] FIG. 1 is a diagram of a pixel circuit according to an embodiment of the present invention. Alizarin 100 I includes liquid crystal capacitor CLC, compensation capacitor CST, and transistor M1, parasitic. 200903428 ruonuo^ix^ 23519twf.doc/p Capacitor C G D represents the gate and source (汲) capacitance of transistor M1. The compensation capacitor CST and the liquid crystal capacitor have a terminal, the other end of the CLC capacitor is coupled to the common voltage VCOM, and the other end of the compensation voltage is connected to the gate line Gm i, the transistor milk Between the feed line DL and the common terminal, the gate is connected to the gate line Gm. The gate line GM·! and GM are adjacent gate lines in the layout of the display panel. f When the gate line Gm-i is enabled, the gate signal is coupled to the liquid crystal capacitor via the compensation capacitor CST. When the gate line Gm is enabled, its gate signal is passed through the parasitic capacitor CGD on the liquid crystal capacitor CLC. Generate feedthrough through) voltage. In other words, the drive polarity of the liquid crystal capacitor CLC can be affected by the gate signal on the gate line Gm_! 〇μ. SECOND EMBODIMENT Using the above-described pixel structure, a layout in which a staggered arrangement is applied can be applied to a dot inversion display. Fig. 2 is a circuit diagram of a display panel according to a second embodiment of the present invention. The display panel 200 includes a pixel column psi, PS2 (the remaining pixel arrays are not shown) 'each pixel column PS1, PS2 includes a plurality of pixels', wherein the pixel column PS1 includes pixels 211 to 214 (the rest is not shown) ), the halogen column PS2 includes halogens 221 to 224 (the rest are not shown). The gate lines Gm-i, Gm, GM+1 and the data lines DL1 to DL5 are connected to the pixels 211 to 214 and 221 to 224. In order to match the driving method of dot inversion, the coupling states of adjacent pixels in the same pixel column are different. Taking the pixel column PS2 as an example, the pixels 221 to 224 in the pixel column PS2 are divided according to the arrangement order. The odd elements 221, 223 and the even elements 222, 224, the odd elements 22 223 and the even elements 222, 200903428 ruoiiuo^^il \V 23519twf.doc/p 224 are arranged in a spaced manner. The idle pole is coupled to the gate line Gm, and the gate of the transistor of the complex j-, 223 of the electro-crystal Zhao Γ 京 222, 224
ίΓ目其彳_容咖_於gm。書素列 psi則對應耦接於閘極線 —’J 數，用以識別顯示面板中之ΐ極t、GM之間，M為正整Γ Γ 彳 _ _ _ _ _ _ gm. The book psi is correspondingly coupled to the gate line — 'J number, to identify the drain between the gates t and GM in the display panel, and M is a positive integer.
O 極性不同，:二:::二：’奇數晝素與偶數晝素的驅動 每-個書1動極性也不㈣。在掃描時， 驅動Μ :、以:;列目一條閘極線的影響而改變其 正極ten /素 為例，當偶數晝素212、214為 線Γ極線〜的輸出為正驅動波形，而閘極 貝為負驅動波形，以使偶數晝素犯、2H產 ，極性的驅動。當偶數晝素2l2、214為負極性 蜀極線GM_i的輸出為負妗-’ 為正驅動_，閘極線輸出則 動。換= ,晝素212、214產生負極性的驅 形與晝;的驅:極=貝:容連接至晝素的閘極線的輸出波 線則配合下—列的*知#而經由電晶體控制晝素的閘極 防认 的旦素驅動極性，調整其輪出波形。 圖3Α=上f閑極線的輪出波形則請參照圖3Α與圖3Β， ['、、'艮據本實施例之正驅動波形圖，圖3Β為;攄太# 閘師衫圖3A所示，當閘極線所輪出的 口就為正驅動波形時，閣極信號， 位準ν卜中基準電壓V3升至電屨 在苐一期間T2申，由電壓位準V1降為V4 10 200903428 23519twf.doc/p ruoiiuoati^i j ，在第二顧T2之後’間姉酬回復至基準電魘λ 弟一期間Τ1中的電壓位準v i主要用於開啟> V3。 體以寫入晝素資料’同時也會經由寄生電; 二合上產生饋通電壓。而第二期間τ2中， ：:曰曰 電壓位準V4喊至基準電壓V3時，會透過補償^就由 至液晶電容，而拉升液晶電容的偏壓以形成正極合 ^圖3B所示’當閘極、線所輸出關極信號為叙 /形時，閘極信號會在第—期間T1巾，由基準電壓、 ^電壓位準V卜在第二期間T2中，閘極信號會由電壓位 ^ V1降為V2 ’並在第二㈣Τ2之後’回復至基準電壓 3。在第—顧T1巾’電壓鱗νι主要祕開啟對應 思素中的f晶體以寫人晝素資料，同時也會經由寄生電容 而在液aa電容上產生饋通電壓。而第二期間T2中，當閘 號由電壓位準V2回復至基準電壓V3時，會透過補償 I谷耦合至液晶電容，而進一步降低液晶電容的偏壓而形 成負極性驅動。 接下來，以晝素212為例，配合閘極線Gf^、GM的 輪出波形說明顯示面板2〇〇的驅動方法。請同時參照圖2 〜圖4，圖4為根據本發明第二實施例之驅動波形圖。在 本實施例中’以晝素電壓PW表示在晝素212的晝素電極 上的電壓變化’以閘極信號SGm-!、SGM表示閘極線Gmj、 Qm輸出信號。晝素212的驅動極性則由晝素電壓PW與共 同電壓VC〇M之間的跨壓所決定。由於本實施例以點反轉 的驅動方式為例’說明顯示面板200的驅動方法，因此畫 11 200903428 F061106SbZ,i i vV 23519twf.doc/p 素212在不同晝面中的驅動極性不同。 首先，當晝素212為負極性驅動時，閘極信 為負驅動波形’而閘極信號SGm為正驅動波：:1 號U升至電壓位準VlBf，晝素列 素21卜213開啟，而偶數晝素212、214會因為 ^ cst而產生耗合電壓，因此晝素電壓pw會先上升= 閘極信號SGM致能以開啟晝素列脱上的奇數 ， 223時’晝素電壓pw會同時因為閘極信號” 產生_合電__信號％上升所產生的饋通2 而下降，當閘極信號犯⑹自電壓位準 : 基準電厂請時，晝素電壓PW會再進= 2 。最後’當閘極信號SGm回復至基準/負 ^素電壓擇會因為饋通電壓而稍微上升，如區域41〇守所 合山Γ進入下晝自^，晝素的驅動極性會改變，全♦ 219 為正驅動波形，而閘極信號％為負驅動波二 會先因為閘極信號犯⑹的轉合而上升， :者閘極信號SG，的下降而下降，此時也合受：： 的影響。當閘極信號S(v]由電壓位；：復^ 基準電M V3時，晝素電M Pw會隨 口设至 信號SGM由賴位，V3降至基準電|時間極 ㈣受其縛_生些制树，好麵O Polarity is different, : 2::: 2: 'The drive of odd-numbered elements and even-numbered elements is not (4). During the scan, the drive Μ:, ::; the influence of a gate line changes its positive ten / prime as an example, when the even halogen 212, 214 is the line of the drain line ~ the output is a positive drive waveform, and The gate is a negative drive waveform, so that the even number of elements are produced, the 2H is produced, and the polarity is driven. When the even elements 2l2, 214 are negative, the output of the 蜀-line GM_i is negative 妗-’ is positive drive _, and the gate line output is moving. Change =, halogen 212, 214 produces a negative polarity drive and 昼; drive: pole = shell: the output wave line connected to the gate line of the halogen is matched with the lower-column * know # via the transistor control The gate of the halogen element is protected against the polarity of the denier, and its turn-out waveform is adjusted. Figure 3Α=The round-out waveform of the upper f-quick line is referred to Figure 3Α and Figure 3Β, [',, 艮 according to the positive driving waveform diagram of this embodiment, Figure 3Β is; 摅太# 师师衫 Figure 3A It is shown that when the port that is turned on by the gate line is a positive driving waveform, the reference signal V3 of the level signal, the level ν Bu rises to the power 屦 during the first period T2, from the voltage level V1 to V4 10 200903428 23519twf.doc/p ruoiiuoati^ij , after the second Gu T2 'returns to the reference power λ 弟 弟 1 period Τ 1 voltage level vi is mainly used to turn on > V3. The body writes the data of the halogen' and also passes through the parasitic electricity; the feedthrough voltage is generated on the second. In the second period τ2, when the ::曰曰 voltage level V4 is shouted to the reference voltage V3, the compensation is applied to the liquid crystal capacitor, and the bias voltage of the liquid crystal capacitor is pulled to form the positive electrode as shown in FIG. 3B. When the gate signal of the gate and the line is in the shape of the gate, the gate signal will be in the period of the first period, the reference voltage, the voltage level V, and the second period T2, the gate signal will be voltage. Bit ^ V1 falls to V2 ' and returns to reference voltage 3 after the second (four) Τ 2 . In the first-T1 towel's voltage scale νι, the main crystal is opened to correspond to the f-crystal in the image, and the feed-through voltage is generated on the liquid aa capacitor via the parasitic capacitance. In the second period T2, when the gate is returned from the voltage level V2 to the reference voltage V3, it is coupled to the liquid crystal capacitor through the compensation I valley, and further reduces the bias of the liquid crystal capacitor to form a negative polarity drive. Next, taking the halogen 212 as an example, the driving method of the display panel 2A will be described in conjunction with the wheel-out waveforms of the gate lines Gf^ and GM. Please refer to FIG. 2 to FIG. 4 at the same time. FIG. 4 is a driving waveform diagram according to a second embodiment of the present invention. In the present embodiment, 'the voltage change on the pixel electrode of the halogen 212 is represented by the halogen voltage PW', and the gate signals Gmj, Qm are output signals by the gate signals SGm-! and SGM. The driving polarity of the halogen 212 is determined by the voltage across the pixel voltage PW and the common voltage VC〇M. Since the driving method of the display panel 200 is described by taking the driving method of the dot inversion as an example, the driving polarity of the display panel 200 is different in different kneading planes. First, when the halogen 212 is driven by the negative polarity, the gate signal is a negative drive waveform 'and the gate signal SGm is a positive drive wave: 1:1 U rises to the voltage level VlBf, and the bismuth prime 21 213 turns on. The even-numbered elements 212, 214 will generate a voltage due to ^ cst, so the pixel voltage pw will rise first = the gate signal SGM is enabled to turn on the odd number of the pixel column, and the 223 time 'the pixel voltage pw will At the same time, because the gate signal "generates the ____ signal_% rise, the feedthrough 2 is decreased, when the gate signal is committed (6) from the voltage level: When the reference power plant is requested, the pixel voltage PW will enter again = 2 Finally, when the gate signal SGm returns to the reference/negative voltage, it will rise slightly because of the feedthrough voltage. If the region 41 keeps the mountain and enters the lower jaw, the driving polarity of the element will change. ♦ 219 is the positive drive waveform, and the gate signal % is the negative drive wave. The second will rise first because of the turn-off of the gate signal (6). The gate signal SG drops and falls. The effect is when the gate signal S(v) is from the voltage level; when the reference voltage M V3 is used, the 昼素电M Pw will be set To signal SGM from the lag, V3 to the reference power | time pole (four) by its binding _ some tree making, good face
在區域410、樣甲，晝素電屋_因間極信^I 200903428 ruonuos^i i W 23519twf.doc/p 的搞合效應以及閘極信號SGm的饋通效應所產生的總下 降電壓以及總上升電壓主要受到閘極信號的電壓變化、寄 生電容CGD、液晶電容CLC以及補償電容CST所影響。 圖5A與圖5B為根據圖4中之區域41〇、420之區域放大 圖。如圖5A所示，總下降電壓等於（dvl+dV2_dV3)， 如圖5B所示，總上升電壓等於（_dV4+dV5_dV6)。配合 上述電路參數值與閘極信號的電壓變化，則可歸納出以下 r, 方程式： dV\ + dV2 - dV3 = {VG * CGD + VEl * CST}/[CST + CLC + CGD] ~ dV4 + dV5 - dV6 = {- * CGD + VE2 * C5r}/[OT + CLC + CGD] —其中’ CST、CLC、CGD分別表示補償電容、液晶電 容以及電晶體的閘（源）極寄生電容值，可直接經由晝素 結構的設計（佈局）來調整；VE1則表示電壓位準^盘 基準電壓V3之間的差值，VE;2表示基準電壓vs與電壓位 $ V4之間的差值’可經由閘極信號的波形來調整。因此， 藉由§周整畫素結構中的元件參數與閘極信號即可改變晝素 的驅動極性’進而降低雜驅動器的功率消耗。 在點反轉的驅動方式中，晝素列P S1中的偶數晝素（如 212、214)的驅動極性相同，其驅動方式則如上述晝 ，驅動方式所述’不再累述。*晝素列psl中的奇數畫素 如211、213)的驅動極性與偶數晝素212、214相 僅需對應調整閉極線、‘的輸出波形即可，在本技 13 200903428 nm 1 _乜乙 1JL \V 23519twf.doc/p 術領域具有通常知識者，經由本發明之揭露，應可輕易推 知其餘閘極線之驅動波形，在此不加累述。 S三實施例 、綜合上述實施例’本發明歸納出一種顯示面板之驅動 方法’適用於上述顯示面板2〇〇，此驅動方法包括下列步 驟·首先，步驟S610依序掃描顯示面板2〇〇中之閘極線； 然後在步驟S620中’當晝素為正極性驅動時，使第一問 ^線的輸出為正驅動波形’㈣二閘極、_輸出為一負驅 —波形；在步驟S63G巾，當晝素為負極性驅動時，使第 動=線出ΐ負驅動波形’第二閘極線的輪出為負驅 ' /、中，弟一閘極線表示上一條閘極線，會經由補 電麗至目前掃描的畫素’而第二閘:線則 方法合至下—晝素列的晝素。上述驅動 參照上述第—、二實施例之說明 具有通常知識者’經由本發明之 推知，在此不加累述。 恩J季工易 练合上述，本發明提出新的面 :驅動技術可直接應用於點反轉之顯：:^吏四 動電路的功率消耗。 降低驅 限定然其並非用以 離本發明之精神和在不脫 此本發明之保護範圍當視後附之申;專者: 14 200903428 1 W 23519twf.doc/p 準。 【圖式簡單說明】 圖1為根據本發明一實施例之晝素電路圖。 圖2為根據本發明第二實施例之顯示面板之電路圖。 圖3A為根據本實施例之正驅動波形圖。 圖3B為根據本實施例之負驅動波形圖。 圖4為根據本發明第二實施例之驅動波形圖。 ^ 圖5A為根據圖4中之區域410之區域放大圖。 圖5B為根據圖4中之區域420之區域放大圖。 圖6為根據本發明第三實施例之驅動方法之流程圖。 【主要元件符號說明】 100 :晝素 200 :顯示面板 DL1〜DL5 :資料線 Gjvi-2〜Gm+ 1 ·開極線 PS1、PS2 :晝素列 I; 211 〜214、221 〜224 :晝素 CLC :液晶電容 CST :補償電容 Ml :電晶體 CGD :寄生電容 T1 =第一期間 T2 :第二期間 V3 :基準電壓 15 200903428 ruoi ιυοοη^ι i W 23519twf.doc/p VI〜V4 :電壓位準 PW :晝素電壓 VCOM :共同電壓 SGmj、SGM :閘極信號 VE1 :電壓差值 VE2 :電壓差值 S610〜S630 :步驟In area 410, sample, 昼素电屋_因间信^I 200903428 ruonuos^ii W 23519twf.doc/p and the total falling voltage and total rise caused by the feedthrough effect of the gate signal SGm The voltage is mainly affected by the voltage change of the gate signal, the parasitic capacitance CGD, the liquid crystal capacitance CLC, and the compensation capacitance CST. 5A and 5B are enlarged views of a region according to the regions 41A, 420 of Fig. 4. As shown in FIG. 5A, the total falling voltage is equal to (dvl + dV2_dV3), and as shown in FIG. 5B, the total rising voltage is equal to (_dV4 + dV5_dV6). In conjunction with the above circuit parameter values and the voltage change of the gate signal, the following r can be summarized, the equation: dV\ + dV2 - dV3 = {VG * CGD + VEl * CST} / [CST + CLC + CGD] ~ dV4 + dV5 - dV6 = {- * CGD + VE2 * C5r}/[OT + CLC + CGD] — where 'CST, CLC, CGD represent the compensation capacitor, liquid crystal capacitor, and gate (source) parasitic capacitance of the transistor, respectively. Adjusted by the design (layout) of the pixel structure; VE1 represents the difference between the voltage level reference voltage V3, VE; 2 represents the difference between the reference voltage vs and the voltage bit $V4' can be passed through the gate The waveform of the polar signal is adjusted. Therefore, by changing the component polarity and the gate signal in the whole pixel structure, the driving polarity of the pixel can be changed, thereby reducing the power consumption of the hybrid driver. In the dot-inversion driving mode, the even-numbered elements (e.g., 212, 214) in the pixel column P S1 have the same driving polarity, and the driving mode is as described above, and the driving mode is no longer described. * The driving polarity of odd-numbered pixels in psl, such as 211 and 213), and the even-numbered elements 212 and 214, only need to adjust the output waveform of the closed-loop line, 'in this technology. 13 200903428 nm 1 _乜B1JL \V 23519twf.doc / p has a general knowledge in the field of technology, through the disclosure of the present invention, the driving waveform of the remaining gate lines should be easily inferred, and will not be described here. The third embodiment of the present invention and the above-mentioned embodiment are summarized as follows: 'The driving method of the display panel is applied to the display panel 2'. The driving method includes the following steps. First, the step S610 sequentially scans the display panel 2 The gate line; then, in step S620, when the pixel is positively driven, the output of the first line is made to be a positive drive waveform '(four) two gates, _output is a negative drive-waveform; in step S63G Tow, when the element is driven by the negative polarity, the first action is to make the first drive line of the second gate line negative drive' /, and the middle gate line represents the last gate line. The singularity of the current scan will be passed through the second sluice. The above-described driving is referred to the description of the above-mentioned first and second embodiments, and the person having ordinary knowledge is inferred from the present invention, and will not be described here. In the above, the present invention proposes a new aspect: the driving technique can be directly applied to the dot inversion display: the power consumption of the quadrupole circuit. Reducing the drive is not intended to be used in the spirit of the present invention and is not to be taken as a part of the scope of the present invention; the subject matter is: 14 200903428 1 W 23519twf.doc/p. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a pixel in accordance with an embodiment of the present invention. 2 is a circuit diagram of a display panel in accordance with a second embodiment of the present invention. Fig. 3A is a front drive waveform diagram according to the embodiment. Fig. 3B is a diagram showing a negative driving waveform according to the present embodiment. Figure 4 is a diagram showing driving waveforms in accordance with a second embodiment of the present invention. ^ Fig. 5A is an enlarged view of a region according to the area 410 in Fig. 4. Figure 5B is an enlarged view of a region according to region 420 of Figure 4. Figure 6 is a flow chart showing a driving method in accordance with a third embodiment of the present invention. [Description of main component symbols] 100: Alizarin 200: Display panel DL1 to DL5: Data line Gjvi-2 to Gm+ 1 • Open line PS1, PS2: Alizarin column I; 211 to 214, 221 to 224: Alizarin CLC : Liquid crystal capacitor CST : Compensation capacitor M1 : Transistor CGD : Parasitic capacitance T1 = First period T2 : Second period V3 : Reference voltage 15 200903428 ruoi ιυοοη^ι i W 23519twf.doc/p VI~V4 : Voltage level PW : halogen voltage VCOM: common voltage SGmj, SGM: gate signal VE1: voltage difference VE2: voltage difference S610 to S630: steps
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