\、 發明說明： 【發明所屬之技術領域】 ▲本發㈣關於-種電路檢响路尊檢測 ;法本發_於一種使用萄鏈魏之電路及;:: f先前技術】 4見蝴子產料’除日新_技術創 :。貝及良率蝴也是產品是否料料者所料的^的 品質產品品管上均十分重視’同時對購買之料件 之品 m r式好元件、镇域其間銲接 =機⑸件進行測式。例如在·料、抗壓、高溫環境測試 ’ py使用菊鏈迴路來加以測試。_鏈迴路設計係指將所有 伸路訊號點連接起來，職完整且簡單的迴路，並在兩端點延 、出測試點’即可於製程完成後或試驗雜巾檢測電訊迴路， 進而了解内部迴路是否產生變化或破壞。 、圖la及圖ib所示為傳統電子元件所内建之部分菊鏈迴路 °尺5十及測試電路板上所設之對應部分菊鍵迴路。電子元件1〇 上設有數個接點11，部分接點11間設有導通線路15。測試電 略板20上設有對應接點11之焊點21，部分焊點21間則設有 ^通線路25。如圖lc所示，當電子元件10焊接於測試電路 1375045 板20上後，接點u即與焊點21雛，使所有接點I〗、焊點 21 : ,Ϊ線路i5、25連接成完整之迴路。接著在進行各種強 又，二貝、可罪度或其他試驗時，即可於迴路兩端之測試點a 及a量測減以進行監控或騎。例如㈣部某處之接點與焊 點^產生空谭或斷裂時，測試點&及a，即會測得斷路之結果。 接者可再以微切片或其他分析，確認其失效模式並提出對策加 改差》。\, Description of the invention: [Technical field to which the invention belongs] ▲This issue (4)About the circuit detection of the road detection; the method of the invention is based on a circuit using the chain Wei; and::: f prior art] 4 see the butterfly Production materials 'except for the new _ technology creation:. The quality of the product and the quality of the product are highly valued. The quality of the product is highly valued at the same time. At the same time, the product of the purchased material, the r r-type good component, and the welding between the town and the machine (5) are measured. For example, in the material, compression, high temperature environment test ' py use daisy chain loop to test. _Chain circuit design refers to the connection of all the extension signal points, the complete and simple circuit, and the point of the test point at both ends, can be used after the process is completed or the test wipes detect the telecommunication loop, and then understand the internal Whether the loop changes or destroys. Figure la and Figure ib show the part of the daisy-chain circuit built in the traditional electronic components, and the corresponding part of the daisy-chain circuit on the test circuit board. A plurality of contacts 11 are disposed on the electronic component 1A, and a conductive line 15 is disposed between the plurality of contacts 11. The test board 20 is provided with solder joints 21 corresponding to the contacts 11, and a portion of the solder joints 21 is provided with a pass line 25. As shown in FIG. 1c, when the electronic component 10 is soldered to the test circuit 1375045, the contact point u is soldered to the solder joint 21, so that all the contacts I, the solder joints 21, and the turns i5 and 25 are connected to be complete. The circuit. Then, when performing various strong, two-shell, guilty or other tests, the test points a and a at both ends of the loop can be measured and reduced for monitoring or riding. For example, when the joints and welds of a part of (4) are empty or broken, the test points & and a will measure the result of the open circuit. The receiver can then confirm the failure mode and propose countermeasures to change the difference by micro-slice or other analysis.
、、然日而此制試迴路僅可測得鱗中發生财的情形，而無 法劍仲各接點或焊網產生短路的情^短路之情形可能由势 ，中使狀樹相錢各焊闕_之設料_造成；然而' f能由外在魏辟、產生職或其侧麵造^若無法 =測試出短路的發生，對產品品質及良率的控管將造成一大 【發明内容】 本發明之-目的在贿供—種電職_ 可判斷測試迴路中短路之產生。 八榱劂万居 法本且發在於提供—種魏㈣迴路及其檢測方 法’具有間便使用之特性。 本發明之電路檢測迴路包含第—基板及 板上設有複數個接舰及複數條第一基板線路^一基板線ς 狀接點。第—紐包含設有魏㈣如及魏條第二 丄J / JU斗：) =路。焊點德置倾第—基板上之接點相職，供在組合時 、 =接點焊接。第—基板線路之兩端分舰接至二焊點，且被連 • 接^二谭點係非為最近距相鄰之焊點。 曰第-基板之接點與第二基板之焊麟麟接後，第一基 板線路及第—基板線路即藉*接點及谭點之導通*形成電性 獨立之第—迴路及第二魏。藉由偵測第 一迴路及第二迴路 間之訊號變化或電性特徵，即可測試第一迴路及帛二迴路間是 • 否有通路產生。由於最近距之各烊齡網於不同之迴路，因 此田第-鱗與f二魏㈤無S路產糾，标最近距之各焊 點間未產生絲；當第—迴路與第二迴關產生猶時，表示 某些接點或焊點之間存在短路的現象。 路檢測迴路及檢測方法包含下列步驟：於第一基板上佈 叹複數個接m基板線路分猶接非最近距相鄰之二接 點，於第二基板上饰設複數焊點，以分別對應於第一基板上之 槪’以第二基板線路分別連接非最近距相鄰之二焊點；以及 ，接對應之焊雜接點’卿細立之第—迴路及第二迴路， 每一焊點與最近距相鄰之焊點係分屬於第一迴路與第二迴 路。測試步驟包含偵測第一迴路與第二迴路間之訊號變化。藉 由偵測第-迴路及第二迴路間之訊號變化或電性特徵，即可測 試第一迴路及第二迴路間是否有通路產生。 、 【實施方式】 本發明係提供一種電路檢測迴路及其檢測使用方法。電路 (S ) 7 U/5045 檢測迴路較㈣供進行各麵度及環境之測試實驗使用。例如 彎折試驗、元件接合強度測試、概溫度試驗、_壓試驗等。 此外’電路制迴路亦可·於製程上參數決定、料評估及 良率之測4例如製程上使用之焊料試驗、焊膏測試、焊點間 距試驗、產品良率試驗等。 在圖2所示之實施例中，本發明之電路檢測迴路包含第一 基板100及第二基板200。如圖2及圖3所示，第一基板⑽ 上設有複數個接點11G以及複數條第—基板線路⑽。在圖3 實施例中，虛線表示之接點m係存在於第—基板⑽ 之下方’然而接點110亦可存在於第一基板⑽之上方 基板線路可視設計絲存在於第-Μ 100之上方、下方 =，於^。如圖3所示伽11Q較佳係呈_方 f1疋以方陣形式排列於第-基板_上；_在不同實施例 接點110亦可以其他形式排列於第-基板100上。 母一第-基板翁15G之兩端 麵她麵之加 第接點111與第四垃ϋ η /1 μ y , μ 此相連，而第二二购一基板線路_ 與第四接點_接。第垃113則不與第—接點⑴ 小於第-細η舆第四接點114之距第離;=1距離係 :與第-接點⑴為最近•二接點換二:= 與第四接點m則非為最 接點111 與第三接點113 狀—接點。第-接點112則 具_蝴咖m林與第—接點However, this test circuit can only measure the occurrence of wealth in the scale, but it is impossible to create a short circuit in each joint or welded wire of the sword. The short circuit may be caused by the potential.阙 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Contents] The purpose of the present invention is to provide a short circuit in the test loop. The Eight Diagrams Living Method is based on the provision of a kind of Wei (four) circuit and its detection method. The circuit detection circuit of the present invention comprises a plurality of receiving ships and a plurality of first substrate lines and a substrate line 接-shaped contacts on the first substrate and the board. The first-news include Wei (four) and Wei strip second 丄 J / JU bucket :) = road. The solder joints are placed on the substrate - the contacts on the substrate are used for joint welding and joint welding. The two ends of the first-substrate line are connected to the two solder joints, and are connected to the second solder joint. After the contact between the first substrate and the second substrate is soldered, the first substrate line and the first substrate line are connected by the * contact and the tan point* to form an electrically independent first loop and a second Wei . By detecting signal changes or electrical characteristics between the first loop and the second loop, it is possible to test whether there is a path between the first loop and the second loop. Because of the recent different distances from the various ages, the Tiandi-scale and the f-Wei (five) have no S-circuit production, and no wire is produced between the solder joints of the nearest distance; when the first loop and the second loop When it occurs, it means that there is a short circuit between some contacts or solder joints. The circuit detection circuit and the detection method include the following steps: singing a plurality of m-substrate lines on the first substrate, and connecting the two adjacent contacts that are not closest to each other, and arranging a plurality of solder joints on the second substrate to respectively correspond On the first substrate, the second substrate line is connected to the second solder joint adjacent to the nearest substrate; and the corresponding solder joints are connected to the first loop and the second loop, each soldering The point of the solder joint adjacent to the nearest point belongs to the first loop and the second loop. The test step includes detecting a signal change between the first loop and the second loop. By detecting the signal change or electrical characteristics between the first loop and the second loop, it is possible to test whether there is a path between the first loop and the second loop. [Embodiment] The present invention provides a circuit detection circuit and a method for detecting the same. Circuit (S) 7 U/5045 The test circuit is used in comparison with (4) for various test surfaces and environmental tests. For example, bending test, component joint strength test, temperature test, _ pressure test, and the like. In addition, the circuit circuit can also be used for parameter determination, material evaluation and yield measurement in the process, such as solder test, solder paste test, solder joint distance test, and product yield test. In the embodiment shown in FIG. 2, the circuit detection circuit of the present invention includes a first substrate 100 and a second substrate 200. As shown in FIGS. 2 and 3, the first substrate (10) is provided with a plurality of contacts 11G and a plurality of first substrate lines (10). In the embodiment of FIG. 3, the dotted line indicates that the contact m is present below the first substrate (10). However, the contact 110 may also exist above the first substrate (10). The substrate line visible design wire exists above the first -100 , below =, in ^. As shown in FIG. 3, the gamma 11Q is preferably arranged in a square matrix on the first substrate _ square _; in different embodiments, the contacts 110 may be arranged on the first substrate 100 in other forms. The first contact of the mother-first substrate- 15G is connected to the fourth contact point η /1 μ y , μ , and the second second purchase of a substrate line _ and the fourth contact _ . The first 113 is not separated from the first contact (1) by less than the fourth-th contact 114; the distance is: the closest to the first contact (1), the second contact is replaced by two: = and The four contacts m are not the most contact 111 and the third contact 113-contact. The first contact 112 has a _cafe m forest and a first contact
Ill及第四接‘點114輕接。此外，在此實施例中，相連接之 一接點111與第四接點114為第二近距之二接點；然而在不同 實施例中，第-接點ηι亦可與更遠距之接點相連接而不與第 四接點114連接，例如第四接，點114右侧之接點。 此外’在較佳實施例巾，每—接點m至多解一條第一 連接；亦即每—接點UG可能與—條第—基板線 =150連接或不與第一基板線路15〇連接。由於接點ιι〇之數 里不-疋转數或偶數，因此#雛⑽之數量為奇數時，可 能有接點則在第一基板⑽上不與其他接點110連接之情況 發生由第二基板之線路與其他接點1 3中ΠΧ所示。 心设 如圖2及圖4所示，第二基板包含設有複數個谭點⑽ 以=數條第二基板線路25〇。在如圖2所示之實施例中，第 二可包含連接墊2〇1供谭點21〇谭接，而第二紐線 =〇亦經由連接塾201醜點210轉接。焊點21〇之位置係 j一基板⑽上之接點別相對應，供在組合時與接點ιι〇 祕4所紅實補t，魏絲之焊點係存在於 弟-基板200之上方’然而焊點21〇亦可設置於第二基板· 。第二基板線路可視設計需求存在於第二基板· 陣列方或埋⑨於中間。如^ 4所示，焊點⑽較佳係呈 饰’特別是以方陣形式排_二基請上；此 得口糾Γ211、弟二焊點212、第三焊點213及第四焊點214 係壬矩㈣列’且第-焊點211與第四焊點214呈對角分佈； 1375045 第二焊點212及第三焊點213亦呈對角分佈。然而在不同實施 例中，焊點210亦可以其他形式之陣列或不規則形式排列於第 二基板200上。 每一第二基板線路250之兩端分別連接至二焊點21〇，且被 連接之二焊點210係非為最近距相鄰之焊點21〇。例如在圖4 中，第二焊點212與第三焊點213係藉由第二基板線路250彼 此相連，而第一焊點211及第四焊點214則不與第二焊點212 與第二焊點213耦接。第三焊點213與第一焊點211之距離係 小於第二焊點213與第二焊點212之距離；換言之，第三焊點 213與第一焊點211為最近距相鄰之二焊點，而第三焊點 與第-焊點212則非為最近距相鄰之二焊點。第四焊點214則 與第-焊點211具有類似的相對位置，因此亦不與第二焊點 212及第三焊點213輕接。此外，在此實施例中，相連接之第 二焊點212與第三焊點213為第二近距之斗點；然而在不同 實施例中’第二焊點212亦可與更遠距之焊點相連接而不與第 三焊點213連接，例如第三焊點213右側之焊點。 此外’在較佳實施例巾，每—雜至多與單—條第二 _卩每-焊點2ig可能與―條第二基板線 旦;^ -—二不與第二基板線路連接。由於焊點210之數 :不^他^因此可能有焊點210在第二基板2〇0 、知點210連接之情況發生。例如圖4巾 ㈣其除細上.晴接。M 如圖2及圖5a所示’當第一基板⑽之接點U0與第二基 1375045 板200之焊點210對應焊接後，第一基板線路15〇及第二基板 線路250即藉由接點11〇及焊點21〇之導通而形成 電性獨立之 第一迴路a-a’及第二迴路b-b，。此處所言之電性獨立係表示 第一迴路在a-a’之區段間與第二迴路在b_b，之區段間設計為 電性隔離狀態。藉由偵測第一迴路a-a，及第二迴路b-b，間之 訊號熒化或電性特徵’即可測試第一迴路a_a，及第二迴路b_b， 間疋否有通路產生。由於最近距之各焊點21〇分別屬於不同之 迴路’因此當第一迴路a-a，與第二迴路b-b，間無通路產生時， 表示第一迴路a_a’中任一焊點210與第二迴路b-b，中之任一 焊點210間未產生短路；當第一迴路a_a’與第二迴路b_b，間 產生通路時，表示某些接點11〇或焊點21〇之間存在短路的現 象。 電路檢測迴路另可包含第一測試點510及第二測試點520 刀別連接於第-迴路a_a’及第二迴路b_b，。第—測試點51〇 及第一測試點520較佳係一起設置於第二基板200上。藉由量 測第一測試點510與第二測試點52〇間之電阻、電流、訊號波 形或其他訊號或電性變化，即可測知第一迴路a-a，與第二迴路 b-b’間是否產生通路。此外，亦可將第一迴路a-a，與第二迴路 b b串聯，以進行其他評估測試，例如開路測試等。當檢測出 有短路或_狀況時，仍需進行χ光檢測或其他細部之檢測， 方能得知確切之短路或開路位置。 η此，，如圖5a所示，為配合各接點與焊點之走線位置，亦 可以若干接點及焊點配合線路形成除第一迴路，與第二迴 11 (S ) 1375045 路b-b’外之第三迴路c~c’。藉由量測各迴路間之電阻、電流、 _. · 訊3虎波形或其他5凡该·或電性變化’即可測知各迴路間是否產生 通路’以確認相鄰之接點與焊點間是否有短路狀況。 如圖5a所示，部分之第一基板線路150係跨越第二基板線 路250。雖然第一基板1〇〇及第二基板2〇〇均為單層板，但由 於第一基板線路150與第二基板線路250係分別設置於第一基 板100及第一基板200，因此第一基板線路15〇與第二基板線 路250可在保持隔離絕緣的狀態下形成交錯結構。缺而由於配 鲁娜無點11〇之分佈位置，部分之第一基板線由路^ 與第二基板線路250則未與其他線路交錯。特別是位置鄰近外 織角落之:^點210及接點110易造成此種情況。此時需藉由 第-基板線路150與第二基板線路25〇將焊點21〇 與其他行狀焊幽及接麵她吨接職第接 及第二迴路。 如圖5a所示，當接點11〇解點轉列方式分佈時， • 部分相焊接之接點110及辉點210分別藉由第-基板線路150 及第二基板線路250與同為次一行列且不相谭接之接點11〇及 焊點210輕接。例如第—接點⑴藉由第一基板線路⑽與第 四接點114輕接；第四接點114即位於第一接.點出之次一 列。與第-接點111焊接之第一焊點211則藉由第二基板線路 250與第五焊點215其中第五焊點加係與第四接點出 位於同-列。然而在不同實施射，第1點2ιι亦可藉由第 -基板線路250與其他非第四焊點214之桿點21〇相接。此 12 (S ) 1375045 . 外’同一行列中第一迴路a-a，中相鄰之二焊點210間設有至少 ’· 屬於第二迴路b_b’之焊點210。例如圖5a中第四焊點214 -* 與第五焊點215均屬於同一迴路’而其間之第二焊點212則屬 另一迴路。因此當第二焊點212與最近距相鄰之第四烊點214 與第五焊點215發生短路時，即會造成兩迴路之通路，進而可 由系統測知。 第一基板100與第二基板2〇〇係可為印刷電路板、軟性電 • 路板、主動元件、被動元件或其他需測試本體或焊接狀況之電 路7G件。焊點21 〇則可由各式焊接材料、焊錫、焊膏等所形成。 接點110與焊‘點210之焊接方式可包含表面黏著技術(SMT)製 程、貫穿孔焊接製程⑽)或其他接著方式。在目&所示之實 施例中’第一基板1〇〇較佳為電路元件，而第二基板則為 測試用之電路板。第-測試點51〇及第二測試點52〇較佳均形 成於第二基板200上。藉由測試結果所得之參數，即可用於正 式產品製程中電路元件與電路板連接之參數設定上。 » 在® 5b所示之實施例中’除原本測試短路之功能外，更加 強開路測試之完整性。如圖所示，第二迴路㈣，之測試點b 所連接之焊點29卜不再經由第二基板線路25〇與其他焊點連 接，而是經由其所焊接之接‘點191連通至第一基板線路15〇。 與圖Sa所示之實施例相較，兩士於進行短路測試時之功能相 當’然而於進行開路測試時’圖5b中之第二迴路b_b，更具有 迴路之完整性，而不會忽略掉與焊點291連接之接點191所產 生之開路狀況。此外’在圖5c所示之實施例中，係將原本三 13 审匕路之叹4調整，而由兩個迴路a—a，與b_b，包含所有之接 點U〇及焊點210。然而由於接點110及焊點210之數目為奇 數因此在第一迴路b—b，中需加設另—測試點b”，方能把所 有之接點110及焊點210納入兩個迴路之中。 夕如圖6所不，第一基板100與第二基板200亦可為雙層或 夕層电路板。在圖6所示之實施例中，第一接點⑴可藉由第 基板線路150與第四接點114減；第二接點112可藉由另 一條第-基板線路15〇與第三接點113輕接。由於兩條第一基 板線路150分別位於第一基板1〇〇之不同層中，因此可互相跨 越而不生短路的問題。同理，當第二基板2Q◦為多層電路板 時’亦可以相同方式處理焊點210與第二基板線路250之關係。 在前述實施例中，焊點21〇多設置於第一基板1〇〇與第二 基板200之間。然而在圖％所示之實施例中，焊點21〇與第 一基板100亦可位於第二基板2〇〇之相對兩侧。如_ 7a所示， 焊點210係經由第二基板2〇〇上之穿孔與第一基板1〇〇上之接 點110相焊接。藉由焊點21〇與接點π〇之連接，得以形成獨 立之第一迴路及第二迴路供各式測試之進行。其餘各測試點， 例如a、a，、b、b，、c及c，仍設置於第二基板2〇〇上’供進行 測量之用。 在圖7b所示之實施例中，接點11〇與焊點21〇則分為三個 有一定間距之區塊分佈。每一區塊均有兩排之接點n〇與焊點 210。換言之’分佈於不同區塊之接點11〇與焊點21〇，即使 直接相鄰’其距離亦可能不是最接近。例如接點193與接點 1375045 I95為相鄰之左右二接點，但其間之距離則大於接點195與接 “-占197間之距離。在此種狀況下，分佈於不同區塊之接點1 及焊點210可選擇分佈於同一迴路或不同迴路。例如接點193 與接點195分別屬於b-b’迴路與c-c，迴路；而接點195與接 點197則同屬於a_a’迴路。 如圖8a所示之實施例，接點11〇與焊點21()之數量均為偶 數個，接點110與焊點210係以非方陣之陣列形式排列。最近 距之三個接點與焊點210分別組成一正三角形；換言之， 母接點110及焊點210具有兩個最近距之相鄰接點丨及焊 點210。此時最近距之三個接點11〇與相焊接之焊點21〇需分 佈於二個以上之獨立迴路，以進行短路或其他之測試。在此種 狀況下，第一基板100與第二基板200中至少其一具有雙層或 夕層之電路架構，方能使各迴路互相跨越而維持隔離。 如圖8a所示，第一接點11卜第一焊點21卜第四接點114 與第四蟬點214屬於第一迴路a_a，，第二接點112、第二焊點 212、第二接點113及第三焊點213則屬於第二迴路b-b，。第 五接點115係分別與第一接點111及第二接•點112 f距相鄰， 亦即第五焊點215分別與第一焊點211及第二焊點212等距相 鄰。因此第五接點115及第邱點2i5係屬於與第-迴路a_a， 及第二迴路b-b，相獨立之第三迴路c_c，。藉由隔離第五接點 L15及第五點215與第一迴路a_a，及第二迴路b-b，，得以測 =第五接點115及第五焊點215與最近距相鄰之焊點及接點間 是否有短路發生。 ‘Ill and the fourth connection ‘point 114 is lightly connected. In addition, in this embodiment, one of the contacts 111 and the fourth contact 114 are connected to the second close contact; however, in different embodiments, the first contact ηι can also be further away. The contacts are connected without being connected to the fourth contact 114, such as the fourth junction, the junction on the right side of the point 114. Further, in the preferred embodiment, each of the contacts m has a maximum of one first connection; that is, each contact UG may or may not be connected to the first substrate line = 150. Since the number of the joints is not - the number of turns or even numbers, when the number of # chicks (10) is an odd number, there may be a case where the contacts are not connected to the other contacts 110 on the first substrate (10) by the second The wiring of the substrate is shown in the middle of the other contacts 13 . Heart arrangement As shown in Figures 2 and 4, the second substrate comprises a plurality of tan points (10) to = a plurality of second substrate lines 25A. In the embodiment shown in Fig. 2, the second may include a connection pad 2〇1 for the tan point 21, and the second line =〇 is also transferred via the connection port 201 ugly point 210. The position of the solder joint 21〇 corresponds to the contact point on the substrate (10), and is used for the combination of the contact point and the contact point, and the solder joint is present above the substrate-substrate 200. 'However, the solder joint 21〇 can also be placed on the second substrate. The second substrate line may be present in the second substrate, the array side or the buried side in the middle. As shown in Fig. 4, the solder joints (10) are preferably decorated in a special form, in the form of a square array. The second solder joint 211, the second solder joint 212, the third solder joint 213, and the fourth solder joint 214 are shown. The second moment (four) column 'and the first solder joint 211 and the fourth solder joint 214 are diagonally distributed; 1375045 the second solder joint 212 and the third solder joint 213 are also diagonally distributed. However, in various embodiments, the solder joints 210 may also be arranged on the second substrate 200 in an array or other form of other forms. The two ends of each of the second substrate lines 250 are respectively connected to the two solder joints 21A, and the connected solder joints 210 are not the closest adjacent solder joints 21〇. For example, in FIG. 4, the second solder joint 212 and the third solder joint 213 are connected to each other by the second substrate line 250, and the first solder joint 211 and the fourth solder joint 214 are not connected to the second solder joint 212 and the second solder joint 212. The second solder joint 213 is coupled. The distance between the third solder joint 213 and the first solder joint 211 is smaller than the distance between the second solder joint 213 and the second solder joint 212; in other words, the third solder joint 213 and the first solder joint 211 are the nearest two adjacent solder joints. Point, and the third solder joint and the first solder joint 212 are not the nearest two solder joints. The fourth solder joint 214 has a similar relative position to the first solder joint 211, and therefore is not lightly connected to the second solder joint 212 and the third solder joint 213. In addition, in this embodiment, the connected second solder joint 212 and the third solder joint 213 are second closely spaced points; however, in different embodiments, the second solder joint 212 can also be further away. The solder joints are connected without being connected to the third solder joint 213, such as the solder joint on the right side of the third solder joint 213. Further, in the preferred embodiment, each of the -to-to-single-single-strip second _ 卩-- solder joints 2 ig may be connected to the second strip substrate; ^ - - 2 is not connected to the second substrate line. Since the number of solder joints 210 is not the same, there may be a case where the solder joints 210 are connected to the second substrate 2〇0 and the known point 210. For example, Figure 4 (4) except for the fine. M, as shown in FIG. 2 and FIG. 5a, after the contact U0 of the first substrate (10) is soldered to the solder joint 210 of the second substrate 1375045, the first substrate line 15 and the second substrate line 250 are connected. The point 11〇 and the solder joint 21〇 are turned on to form an electrically independent first loop a-a' and a second loop bb. The electrical independence referred to herein means that the first loop is designed to be electrically isolated between the sections of a-a' and the sections of the second loop at b_b. By detecting the first circuit a-a, and the second circuit b-b, the signal fluorescing or electrical characteristics between the first circuit a_a and the second circuit b_b can be tested to detect whether there is a path. Since the closest solder joints 21〇 belong to different loops respectively, so when there is no path between the first loop aa and the second loop bb, it means that any one of the solder joints 210 and the second loop in the first loop a_a' Bb, there is no short circuit between any of the solder joints 210; when a path is formed between the first loop a_a' and the second loop b_b, it indicates that there is a short circuit between some of the contacts 11〇 or the solder joints 21〇. The circuit detection circuit may further include a first test point 510 and a second test point 520 connected to the first loop a_a' and the second loop b_b. The first test point 51A and the first test point 520 are preferably disposed on the second substrate 200 together. By measuring the resistance, current, signal waveform or other signal or electrical change between the first test point 510 and the second test point 52, the first loop aa can be detected, and the second loop b-b' Whether to create a pathway. In addition, the first loop a-a may be connected in series with the second loop b b for other evaluation tests, such as an open circuit test. When a short circuit or _ condition is detected, it is still necessary to perform a light detection or other detail detection to know the exact short circuit or open circuit position. η this, as shown in Figure 5a, in order to match the wiring position of each contact and solder joint, it is also possible to form a plurality of contacts and solder joints to form a circuit other than the first loop, and the second back 11 (S) 1375045 road b The third loop outside c-c' is c~c'. By measuring the resistance, current, _., signal, or other changes in the circuit, you can detect whether or not a path is formed between the circuits to confirm adjacent contacts and soldering. Is there a short circuit between the points? As shown in Figure 5a, a portion of the first substrate line 150 spans the second substrate line 250. The first substrate 1 and the second substrate 2 are both single-layer boards. However, since the first substrate line 150 and the second substrate line 250 are respectively disposed on the first substrate 100 and the first substrate 200, the first The substrate line 15A and the second substrate line 250 may form a staggered structure while maintaining isolation insulation. Due to the distribution position of the Luna no point 11〇, part of the first substrate line is not interlaced with the other lines by the road ^ and the second substrate line 250. In particular, the location is adjacent to the outer corner: ^ point 210 and the contact 110 are liable to cause this. At this time, it is necessary to use the first substrate line 150 and the second substrate line 25 to connect the solder joints 21〇 with the other rows of solder joints and the junctions of the second and second loops. As shown in FIG. 5a, when the contacts 11 are distributed in a point-and-forward manner, the partially-welded contacts 110 and the bright spots 210 are respectively the same by the first substrate line 150 and the second substrate line 250. The contacts and the solder joints 210 are lightly connected. For example, the first contact (1) is lightly connected to the fourth contact 114 by the first substrate line (10); the fourth contact 114 is located at the first row of the first connection. The first solder joint 211 soldered to the first contact 111 is connected to the fourth solder joint 215 by the second substrate line 250 and the fifth solder joint 215. However, in different implementations, the first point 2 ιι can also be connected to the other non-fourth solder joints 214 by the first substrate line 250. The 12 (S) 1375045. outer first row a-a in the same row, and at least two solder joints 210 belonging to the second loop b_b' are disposed between the adjacent two solder joints 210. For example, in Figure 5a, the fourth solder joint 214 -* and the fifth solder joint 215 are both in the same loop ' while the second solder joint 212 is in the other loop. Therefore, when the second pad 212 is short-circuited with the fourth adjacent point 214 and the fifth pad 215 which are adjacent to each other, the path of the two circuits is caused, which can be detected by the system. The first substrate 100 and the second substrate 2 may be printed circuit boards, flexible electrical boards, active components, passive components or other circuit 7G parts that require testing of the body or soldering conditions. Solder joints 21 can be formed from various types of solder materials, solder, solder paste, and the like. Contact 110 and solder 'point 210 soldering may include surface mount technology (SMT) process, through-hole soldering process (10)) or other subsequent means. In the embodiment shown in the &>, the first substrate 1 is preferably a circuit component, and the second substrate is a circuit board for testing. The first test point 51 and the second test point 52 are preferably formed on the second substrate 200. By using the parameters obtained from the test results, it can be used for parameter setting of circuit components and circuit board connections in the formal product process. » In the example shown in ® 5b, the integrity of the open-circuit test is enhanced in addition to the original short-circuit test function. As shown in the figure, the second circuit (4), the solder joint 29 connected to the test point b is no longer connected to other solder joints via the second substrate line 25, but is connected to the solder via the soldered point 191. A substrate line 15 turns. Compared with the embodiment shown in FIG. Sa, the functions of the two conductors in performing the short-circuit test are equivalent. However, in the case of the open-circuit test, the second loop b_b in FIG. 5b has the integrity of the loop and is not neglected. The open circuit condition generated by the contact 191 connected to the solder joint 291. In addition, in the embodiment shown in Fig. 5c, the original sigh 4 is adjusted, and the two loops a-a and b_b contain all the contacts U and solder joints 210. However, since the number of the contacts 110 and the solder joints 210 is an odd number, another test point b" is added in the first circuit b-b, so that all the contacts 110 and the solder joints 210 can be incorporated into the two circuits. As shown in Fig. 6, the first substrate 100 and the second substrate 200 may also be double-layer or slab circuit boards. In the embodiment shown in Fig. 6, the first contact (1) may be through the substrate line 150 and the fourth contact 114 are subtracted; the second contact 112 can be lightly connected to the third contact 113 by another first substrate line 15A. Since the two first substrate lines 150 are respectively located on the first substrate 1〇〇 In the different layers, the problems can be crossed without causing a short circuit. Similarly, when the second substrate 2Q is a multilayer circuit board, the relationship between the solder joint 210 and the second substrate line 250 can also be handled in the same manner. In the embodiment, the solder joints 21 〇 are disposed between the first substrate 1 〇〇 and the second substrate 200. However, in the embodiment shown in FIG. %, the solder joints 21 〇 and the first substrate 100 may also be located in the second The opposite sides of the substrate 2, as shown in _7a, the solder joint 210 is through the second substrate 2 through the perforation and the first The contacts 110 on the board 1 are soldered together. By connecting the solder joints 21〇 to the contacts π〇, an independent first loop and a second loop are formed for each type of test. a, a, b, b, c and c are still disposed on the second substrate 2' for measurement. In the embodiment shown in Figure 7b, the contacts 11〇 and the pads 21〇 It is divided into three blocks with a certain spacing. Each block has two rows of contacts n〇 and solder joints 210. In other words, 'the contacts are distributed in different blocks 11〇 and solder joints 21〇, even if Directly adjacent 'the distance may not be the closest. For example, the contact 193 and the contact 1375045 I95 are adjacent left and right contacts, but the distance between them is greater than the distance between the contact 195 and the "- 197". In this case, the contacts 1 and the solder joints 210 distributed in different blocks may be selectively distributed in the same circuit or in different circuits. For example, the contacts 193 and 195 belong to the b-b' loop and the c-c, respectively, and the contacts 195 and 197 belong to the a_a' loop. In the embodiment shown in Fig. 8a, the number of contacts 11 〇 and pads 21 () is an even number, and the contacts 110 and the pads 210 are arranged in an array of non-square arrays. The three closest contacts and the solder joints 210 respectively form an equilateral triangle; in other words, the female contacts 110 and the solder joints 210 have two nearest neighbors and solder joints 210. At this time, the closest joint of the three joints 11〇 and the phase welded joints 21 need to be distributed to more than two independent loops for short circuit or other tests. In this case, at least one of the first substrate 100 and the second substrate 200 has a circuit structure of a double layer or a layer to enable the circuits to cross each other to maintain isolation. As shown in FIG. 8a, the first contact 11 and the first solder joint 21, the fourth joint 114 and the fourth defect 214 belong to the first loop a_a, the second joint 112, the second solder joint 212, and the second The contact 113 and the third solder joint 213 belong to the second loop bb. The fifth contact 115 is adjacent to the first contact 111 and the second contact 112 f, respectively, that is, the fifth solder joint 215 is equidistant from the first solder joint 211 and the second solder joint 212, respectively. Therefore, the fifth contact 115 and the second point 2i5 belong to the third loop c_c which is independent of the first loop a_a and the second loop b-b. By isolating the fifth contact L15 and the fifth point 215 from the first loop a_a and the second loop bb, it is determined that the fifth contact 115 and the fifth solder joint 215 are connected to the nearest adjacent solder joint. Is there a short circuit between the points? ‘
15 (S ^圖肋所示之實施例中，接點no與焊點210之數量均為 奇數個。此時可加設多組迴路並於某一組迴路中增加測試點， 使所有接點110與焊點210均包含於數組迴路的其令之―。如 圖8b所示，第二迴路b_b，即加設一職點b”於第二基板咖 上’以包含最右下角之接‘點11〇及焊點21〇於迴圈中。在進行 開路測試時，可先量測b_b’間之通路狀況；若確認^，間無 異狀時，再連接b”點進行量測。此外，亦可直接量測卜匕，，或 b’—b”間之通路狀況。在進行短路測試時，則可以b-b，迴路先 與其他迴路進行測試；若確認b_b，迴路與其他迴關無短路 時’再連接b”點進行測試。此外，亦可直接以b_b，，迴路或匕,七, 迴路與其他迴路進行短路測試。 如圖8b所示，接點11〇可分為第一迴路接點群、弟二迴 路接點群、第二迴路接點群、第四迴路接•點群及第五迴路接點 群。第-迴路接點群中包含複數個第一迴路接點61〇，第二迴 路接點群t包含複油第二轉無㈣，“ 接點群中 包3複數個第二迴路接點咖。第四迴路接點群及第五迴路接 點群中亦分別包含複數個接點11〇。每一接點11〇係選擇性籍 由第-基板線路15G純同-迴路接點群中之接點nQ。例如 第一迴路接點_可藉由第—基板線路15〇連接至另一第一迴 路接點610 ;第-迴路接點_亦可不藉由第一基板線路15〇 ，任何接點no連接’而經由焊點21〇及第二基板線路25〇與 第厂迴路a-a’連接。此外，每一接點.11〇與同一迴路接點群中 最近之接點11G距離係大於其與不同迴路接點群中最近之接 1375045 點1_。例如第一迴路接點 點_間距離為X，而溆田，“垃 网之弟—迴路接 則距射大於取近之第二®路接點咖間距離為Y， 群210可分為第一爾點群、第二迴路焊點 ,—、路知點群、第四迴路焊點群及第五迴路蟬點 焊點群中包含複數個第一迴路焊點训，第二迴路 群中包含複數個第二迴路焊點720，第三迴路焊 Μ =第三迴路焊點730。第四迴路焊點群及第五迴路焊二 ’、刀別包含複數個嬋點2iG β每一蟬點21G係選擇性藉由第二 基板線路250 _同一迴路蟬點群中之軸训。例^第一^ 7^71 由第二基板線路250連接至另一第一迴路焊點 1〇，第一迴路谭點710亦可不藉由第二基板線路250盥任何 知點21G it接，而經由接點11()及第—基板線路 路a-a，連接。 穴矛、 、每了焊點21(H系對應焊接同一迴路接點群中之接點ιι〇，以 連接形成該迴路。例如第—迴路接點群中之第—迴路接點⑽ ，分別與第-迴料點710耦接，並搭配第一基板線路⑽與 第二基板線路250以組成第一迴路a_a，。同理各迴路接點群及 焊點群分別形成第二迴路b_b，、第三迴路c_c，、第四迴路㈣， 以及第五祕e-e，。各迴關均輕_立，以供職各迴路 中所含之接點UG與焊點綱是否與其他迴路中之接點110盘 焊點210短路。 、 圖9所示為祕檢_路之檢測方法實關流糊。步驟 ) 17 砂第2 點。喻时施例而言， 第—触、第二她、第三獅及第四接15 (In the embodiment shown by S ^ rib, the number of contact no and solder joint 210 is an odd number. At this time, multiple sets of loops can be added and test points can be added to a certain set of loops to make all joints 110 and solder joint 210 are both included in the array loop - as shown in Figure 8b, the second loop b_b, that is, add a job point b" on the second substrate coffee to "include the bottom right corner" Point 11〇 and solder joint 21 are in the loop. When performing the open circuit test, the path condition between b_b' can be measured first; if there is no abnormality between ^, then connect b) point for measurement. It is also possible to directly measure the path condition between the dice, or b'-b". When performing the short-circuit test, it can be bb, the circuit is tested with other circuits first; if b_b is confirmed, the circuit is not short-circuited with other switches. When the 'reconnect b' point is tested, in addition, it can be directly tested by b_b, loop or 匕, seven, loop and other circuits. As shown in Figure 8b, the contact 11〇 can be divided into the first loop. Point group, brother second circuit contact group, second circuit contact group, fourth circuit connection point group and fifth circuit contact group The first loop contact group includes a plurality of first loop contacts 61〇, and the second loop contact group t includes the second turn of the re-oil (4), “the plurality of second loop contacts in the contact group” The fourth loop contact group and the fifth loop contact group also respectively include a plurality of contacts 11〇. Each contact 11 is selectively selected from the first-substrate line 15G in the same-loop contact group. The contact nQ, for example, the first loop contact _ can be connected to the other first loop contact 610 by the first substrate line 15 ;; the first loop contact _ can also be bypassed by the first substrate line 15 Point no connection 'and is connected to the first plant circuit a-a' via the solder joint 21〇 and the second substrate line 25〇. In addition, each contact point .11〇 is the closest contact point to the 11G in the same circuit contact group. It is larger than the closest connection to the different circuit contact group, 1375045 points 1_. For example, the first circuit contact point _ distance is X, and Putian, "the brother of the net - the distance of the circuit is greater than the second The distance between the ® junctions is Y, and the group 210 can be divided into the first point group, the second circuit joint, the -, the road point group, and the fourth circuit point group. The fifth circuit 蝉 spot welding point group includes a plurality of first circuit welding points, the second circuit group includes a plurality of second circuit welding points 720, and the third circuit welding Μ = third circuit welding point 730. The fourth circuit The solder joint group and the fifth loop solder 2', the knife includes a plurality of defects 2iG β each point 21G is selectively controlled by the second substrate line 250 _ the same circuit in the group of axes. Example ^ first ^ 7^71 is connected to the other first circuit pad 1〇 by the second substrate line 250, and the first circuit tan point 710 can also be connected by the second substrate line 250 without any known point 21G, but via the contact 11 () and the first substrate line aa, connected. The hole spear, each solder joint 21 (H system corresponding to the joint in the same circuit contact group ιι〇, to form the loop. For example, the first loop contacts (10) in the first loop contact group are respectively coupled to the first return point 710, and are matched with the first substrate line (10) and the second substrate line 250 to form the first loop a_a. Similarly, each loop contact group and the solder joint group form a second loop b_b, a third loop c_c, a fourth loop (4), and a fifth secret e-e, respectively. Each switch is lightly erected, and the contacts UG and solder joints contained in the respective circuits are short-circuited with the 110 pads of the other circuits. Figure 9 shows the secret detection _ road detection method is really clear. Step) 17 Sand 2nd point. In the case of Yu Shi, the first touch, the second she, the third lion and the fourth
點。弟-槪與細接關技軸A =及Γ接點間之距離，第二接點與第三接败 接與第—接點及第四接點間之雜。此外，佈設 /可隨[基板之性質及種_整；例如當第-基板 ί—’ _可以_之方式形成於第一基板上；當 元料’無财叫路製财細彡成於第一 ^ = 930包含w第—基板線路分別連接非最近距相鄰之二 =2之較佳實施例中’係以第一基板線路·於第- f點H板魏之形成及與接_接之方式亦 2 : 性f及_調整’·例如當第一基板為印刷電路point. The distance between the younger brother and the fine contact axis A = and the contact point, the second contact and the third connection are disconnected from the first contact and the fourth contact. In addition, the layout/may be formed on the first substrate along with the nature and type of the substrate; for example, when the first substrate _ _ can be formed on the first substrate; A ^= 930 includes a w-substrate line connected to a non-nearest neighboring second=2. In the preferred embodiment, the first substrate line is formed at the first-f point, and the H-plate is formed and connected. The way is also 2: sex f and _ adjustment '· for example when the first substrate is a printed circuit
Hi基姆路可以_之方式職於第—基板，並與接 4一基板為主動元件時，第一基板線路則可以電路 衣程方式形成於第一基板。 =950包含於第二基板上佈設複數焊點，以分別對應於 -:板上之接點。在上述之較佳實施例中，係於第二基板上 =第-焊點 '第二焊點、第三谭點及第四焊點分別對應於第 點兄第了接點、第三接點及第四接點。在於第二基板上佈 汉焊^可先於第二基板上佈對目應之連接墊。連接塾之 形成方式可隨第二基板之性質及麵調整；例如當第二基板為 印刷電路板時，連齡可以印刷之方式形成於第二基板上；當 1375045 第二基板為主動元件時，連接_可以電路製程方式形成於第 二基板上。此外，焊點佈設之方式係可以表面黏著技術(SMT) 製程、貫穿孔嬋接製程(Dip)或其他製程方式佈設。 曰步驟970包含以第二基板線路分別連接非最近距相鄰之二 焊點。在上述之較佳實施例中，係以第二基板線路麵接於第二 谭2及第二焊點。第二基板線路之形成及與烊點連接之方式亦 可隨第广基板之性質及種類調整；例如當第二基板為印刷電路 板時，第二基板線路可以印刷之方式形成於第二基板，並與 I占連接，·當第二基板a主動元件時’第二基板線路則可以電路 j程方式形成於第二基板。 、步驟990包含烊接對應之焊點與接點，以形成獨立之第— 迴路及第二迴路，每一焊點與最近距相鄰之谭點係分屬於 迴路與第二迴路。在上述之較佳實施例中，此時部分之第 板線路會跨越第二基板線路。焊接之方式較佳可包含表面 技術(SMT麻、貫穿孔_製程_或其鱗接製程。* 圖广所示為電路檢測迴路檢測方法之另一實施例流程圖。 在㈣所示之實施例中，更包含測試步驟1010，_第—.回 路與第二"1路間之訊號變化。藉由_第-迴路及第二迴路^ 之訊號變化或電性特徵，即可測試第—迴路及第二迴路二 赵。由於最近蚊各焊财_於不狀迴路^此 田迴路與第二迴路間無通路產生時，表示最近距之各谭點 S產生短路；當第一迴路與第二迴路間產生通路時： 焊點之間存在短路的現象。 又不 (S ) 19 1375045 訊號變化之侦測包含量測第-迴路與第二迴路間之電阻、 電流、訊號波形或其他訊號或電性變化，以測知第一迴路與第 二迴路間是否產生通路。此外，亦可將第一迴路與第二迴路串 耳外’以進打其他評估測試，例如開路測試等。 、本發明已由上述糊實施例加以描述，然而上述實施例僅 為實施本發明之制。必需指_是，已揭露之實施顺未限 制本發明之棚。相反地，包含於申請專利細之精神及範圍 之修改及均等設置均包含於本發明之範圍内。 【圖式簡單說明】 圖1a至圖1c為習知電路檢測迴路之示意圖； 圖2為本發明電路檢測迴路之實施例示意圖； 圖3為第一基板之實施例示意圖； 圖4為第二基板之實施例示意圖； 圖5a為電路檢測迴路之組合示意圖； 圖5b為電路檢測迴路之另一實施例示意圖； 圖5c為電路檢測迴路之另一實施例示意圖； 圖6為電路檢測迴路之另一實施例示意圖； 圖7a為電路檢測迴路之另一實施例示意圖； 圖7b发 苟電路檢測迴路之另一實施例示意圖； "8a為電路檢測迴路之另一陣列形式示意圖； :8b為奇數接點時之實施例示意圖； 圖9兔φ 電路檢测迴路之檢測方法之實施例流程圖； 20 1375045 圖10為電路檢測迴路之檢測方法之實施例流程圖。 【主要元件符號說明】 100第一基板 110接點 111第一接點 112第二接點 113第三接點 114第四接點 115第五接點 150第一基板線路 200第二基板 201連接墊 210焊點 211第一焊點 212第二焊點 213第三焊點 214第四焊點 215第五焊點 250第二基板線路 510第一測試點 520第二測試點 610第一迴路接點 21 1375045 620第二迴路接點 630第三迴路接點 710第一迴路焊點 720第二迴路焊點 730第三迴路焊點When Hi Kim Road can work on the first substrate, and the substrate is connected to the active device, the first substrate circuit can be formed on the first substrate in a circuit-packed manner. = 950 includes a plurality of solder joints disposed on the second substrate to correspond to the contacts on the -: board. In the above preferred embodiment, the second solder joint, the second solder joint, the third solder bump, and the fourth solder joint are respectively corresponding to the first point and the third joint. And the fourth junction. The bonding pads on the second substrate may be disposed on the second substrate before the bonding pads of the target substrate. The manner of forming the connection can be adjusted according to the nature and surface of the second substrate; for example, when the second substrate is a printed circuit board, the connection can be formed on the second substrate by printing; when the first substrate is the active component, the 1375045 The connection_ can be formed on the second substrate in a circuit process manner. In addition, the solder joint layout can be laid by surface mount technology (SMT) process, through-hole splicing process (Dip) or other process methods. Step 970 includes connecting the second solder joints that are not closest to each other by the second substrate line. In the above preferred embodiment, the second substrate line is connected to the second tan 2 and the second solder joint. The formation of the second substrate line and the manner of connecting with the defect can also be adjusted according to the nature and type of the first substrate; for example, when the second substrate is a printed circuit board, the second substrate line can be formed on the second substrate by printing. And connected to I, when the second substrate a active device, the second substrate line can be formed on the second substrate in a circuit manner. Step 990 includes splicing the corresponding solder joints and contacts to form an independent first loop and a second loop, and each solder joint is adjacent to the nearest tan point and belongs to the loop and the second loop. In the preferred embodiment described above, a portion of the first board line will now traverse the second substrate line. Preferably, the soldering method may include surface technology (SMT hemp, through hole_process_ or its squashing process. * The figure shows a flow chart of another embodiment of the circuit detecting loop detecting method. The embodiment shown in (4) In addition, the test step 1010, the signal change between the _th.. and the second "1. The first loop can be tested by the signal change or electrical characteristics of the _th-loop and the second loop^ And the second circuit of the second Zhao. Because of the recent mosquito welding money _ in the non-loop circuit ^ when there is no path between the field circuit and the second circuit, it means that the short distance from each of the Tan points S is short; when the first circuit and the second When a path is created between the loops: There is a short circuit between the solder joints. No (S) 19 1375045 The detection of signal changes involves measuring the resistance, current, signal waveform or other signal or electricity between the first loop and the second loop. Sexual change to detect whether a path is generated between the first loop and the second loop. In addition, the first loop and the second loop may be externally struck to perform other evaluation tests, such as an open circuit test, etc. Described from the above paste embodiment, However, the above-described embodiments are merely examples of the implementation of the present invention. It is to be understood that the disclosed embodiments are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1a to FIG. 1c are schematic diagrams of a conventional circuit detection circuit; FIG. 2 is a schematic diagram of an embodiment of a circuit detection circuit of the present invention; FIG. 3 is a schematic view of an embodiment of a first substrate; 4 is a schematic diagram of an embodiment of a second substrate; FIG. 5a is a schematic diagram of a combination of circuit detection loops; FIG. 5b is a schematic diagram of another embodiment of a circuit detection loop; FIG. 5c is a schematic diagram of another embodiment of a circuit detection loop; FIG. 7a is a schematic diagram of another embodiment of the circuit detection circuit; FIG. 7b is a schematic diagram of another embodiment of the circuit detection circuit; "8a is a schematic diagram of another array form of the circuit detection circuit; Fig. 9 is a schematic diagram of an embodiment of an odd number of contacts; Fig. 9 is a flow chart of an embodiment of a method for detecting a rabbit φ circuit detection circuit; 20 1375045 Fig. 10 is a circuit Flow chart of embodiment of detecting method of measuring circuit. [Description of main component symbols] 100 first substrate 110 contact 111 first contact 112 second contact 113 third contact 114 fourth contact 115 fifth contact 150 First substrate line 200 second substrate 201 connection pad 210 solder joint 211 first solder joint 212 second solder joint 213 third solder joint 214 fourth solder joint 215 fifth solder joint 250 second substrate line 510 first test point 520 Second test point 610 first loop contact 21 1375045 620 second loop contact 630 third loop contact 710 first loop solder joint 720 second loop solder joint 730 third loop solder joint