1373982 九、發明說明 【發明所屬之技術領域】 本發明是關於有機EL裝置之技術，尤其關於 ITO(Indium-tin oxide)之有機 EL 裝置。 【先前技術】 於頭盗顯示器（Head Mount Display)或投影機 有機EL顯示裝置時，必須作成小型且高畫質之有卷 顯示裝置。爲了作成小型且高畫質之有機EL，必須 作成發光元件部。 但是，要如以往般利用在玻璃基板上形成ITO等 明電極的方法，來實現如此微細之發光元件則有困難 是因一般ITO膜以濺鍍所形成膜，故有發生凹凸或缺 或者，由於飛濺使得ITO膜有發生凹凸缺陷的情形。 了實現小型有機EL而薄化ITO膜時，如此之缺陷則 造成短路。 並且，以濺鍍所作成之ITO膜因異方生長，故非 密組織。因此，於圖案製作時所使用之蝕刻液有進 ITO膜之情形，被形成在ITO膜上之有機層有受損 形。因此，於使用ITO時，製作小型之有機EL裝置 困難。 並且，ITO膜爲了降低電阻，必須在200 °C以 火。 [專利文獻1]日本特開2〇〇 1 -76884號 使用 使用 I EL 微細 之透 。該 陷， 當爲 容易 爲細 入至 之情 則爲 上退 1373982 [專利文獻2]日本特開2002-237383號 【發明內容】 [發明所欲解決之課題] 本發明之目的爲以使用Si晶圓代替玻璃基板，作成 小型且高畫質之有機EL顯示裝置。 再者，本發明之目的是提供一種不使用ITO，而具有 微細之發光元件的有機EL顯示裝置。 [用以解決課題之手段] 爲了解決上述課題，申請專利範圍第1項所記載之發 明，是一種顯示裝置，其特徵爲：具備有 半導體基板；被形成在上述半導體基板上之複數連接 電晶體：被形成在上述半導體基板之複數孔；各被配置在 上述各孔內，當流通電流時發光的有機發光層；和各被配 置在上述有機發光層之表面上的畫素電極，上述各連接電 晶體是各具有第1、第2之主端子，和用以控制上述第 1、第2主端子間之導通的控制端子，上述各有機發光層 上之畫素電極是互相電性分離，上述各畫素電極是被連接 於不同之上述連接電晶體之上述第1主端子^ 申請專利範圍第2項所記載之發明，是如申請專利範 圍第1項所記載之顯示裝置，其中，上述各孔是被形成有 底面’在底面露出共通電極，上述有機發光層之底面是接 觸至上述共通電極。 -6- 1373982 申請專利範圍第3項所記載之發明，是如申請專利範 圍第2項所記載之顯示裝置，其中，上述共通電極是被形 成在上述半導體基板之內部的雜質區域。 申請專利範圍第4項所記載之發明，是如申請專利範 圍第3項所記載之顯示裝置，其中，上述半導體基板之底 面和上述各孔之底面之間的厚度是被設爲5 OOnm以下， 上述有機發光層之發光光線是透過上述孔底面之上述半導 體基板而被放射至外部。 申請專利範圍第5項所記載之發明，是如申請專利範 圍第3項或第4項中之任一項所記載之顯示裝置，其中， 上述雜質區域之導電型是與上述半導體基板相反的導電 型。 申請專利範圍第6項所記載之發明，是一種顯示裝 置，其特徵爲：構成爲具備有半導體基板；被形成在上述 半導體基板上之複數孔；各位於上述各孔之底面的共通電 極；各被配置在上述各孔內之有機發光層；和被配置在上 述各有機發光層之表面上，互相電性分離的畫素電極，在 上述共通電極和上述畫素電極之間施加電壓，當電流流通 於上述有機發光層時，上述有機發光層則發光的顯示裝 置，上述共通電極是由被形成在上述半導體基板內之雜質 區域所構成。 申請專利範圍第7項所記載之發明，是如申請專利範 圍第6項所記載之顯示裝置，其中，在上述半導體基板內 形成複數連接電晶體，上述各連接電晶體是各具有第1、 1373982 第2主端子，和用以控制上述第1、第2主端子間之導通 的控制端子，上述各畫素電極是被連接於不同上述連接電 晶體之上述第1主端子。 請專利範圍第8項所記載之發明，是如申請專利範圍 第6項或第7項中之任一項所記載之顯示裝置，其中，上 述半導體基板之底面和上述各孔之底面之間的厚度是被設 爲200nm以上500nm以下，上述有機發光層之發光光線 是透過上述孔底面之上述半導體基板而被放射至外部。 申請專利範圍第9項所記載之發明，是如申請專利範 圍第1〜5、7、8項中之任一項所記載之顯示裝置，其中， 在上述半導體基板上，形成包含與上述連接電晶體不同之 電晶體的複數電子元件，藉由上述電子元件，在上述半導 體基板上，形成被連接於上述各連接電晶體之上述控制端 子的導通控制電路，和被連接於上述第2主端子之電壓施 加電路，藉由上述導通控制電路和上述電壓施加電路，使 上述複數連接電晶體中之所欲的電晶體予以導通，將電流 流通於被連接於該被導通之連接電晶體之上述第1主端子 的上述有機發光層上，構成使上述有機發光層予以發光。 申請專利範圍第1 〇項所記載之發明，是一種顯示裝 置之製造方法，其特徵爲：具備有將第2導電型之雜質導 入至第1導電型之半導體基板之背面，形成共通電極之步 驟；在上述半導體基板之表面形成複數孔，使上述共通電 極露出至上述各孔內的步驟；在上述孔內形成有機發光層 之步驟；和在上述各有機發光層表面形成畫素電極之步 -8- 1373982 驟。 申請專利範圍第11項所記載之發明，是如申請專利 範圍第〗〇項所記載之顯示裝置之製造方法，其中，具備 有在上述半導體基板內形成第2導電型之通道區域，在上 述通道區域內各形成以第1導電型互相被分離之第1、第 2區域，形成連接電晶體的步驟，並將上述第1區域連接 於上述畫素電極。 本發明是在半導體基板上形成有底的孔，並在該孔內 形成有機發光層。 在孔底面上，藉由雜質擴散配置電阻率低之擴散區 域。將此當作共通電極。然後，當將存在於各孔底面之共 通電極的厚度，即是共通電極以構成半導體基板之半導體 結晶所構成之時’該部分之半導體結晶之厚度，先設爲有 機發光層之發光光線可以透過的厚度時，發光光線則透過 共通電極，而被放射至外部。 因此，必須要自有機發光層之面中，與共通電極相反 側之面放射發光光線，故可以在與共通面相反側之面上配 置金屬電極。 [發明效果] 本發明因將半導體晶圓之一部分當作電極使用，故即 使不使用ITO亦可以作成具有微細發光元件之有機EL顯 示裝置。 再者，本發明因不需要LSI作成所要求之高品質半導 1373982 體晶圓，故可以使用至此被廢棄或是不合被當作回收資源 再利用的LSI規格，例如規格外之Si晶圓。 【實施方式】 第18圖之符號101爲半導體晶圓，形成複數個本發 明之顯示裝置102。 各顯示裝置102是被行列狀配置，在各顯示裝置102 之行與行之間和列與列之間，各配置有劃線1 〇3 X、 l〇3y»劃線103x、103y上之半導體晶圓101之表面是被 露出，當切斷劃線I〇3x、103y之部分時，各顯示裝置 102則各被分離。 第19圖是用以說明1個顯示裝置102之構造的模式 性平面圖，省略保護膜及後述之第1、第2層間絕緣膜 等。 該顯示裝置102具有複數個相當於最小1像點之顯示 單位的畫素110»各畫素110被配置成行列狀，在各畫素 1 1 〇之行與行之間和列與列之間，各圍繞有掃描線1 1 2和 資料線11 1。 第20圖是放大畫素110之模式平面圖，各畫素no 是各具有有機EL層40，和連接電晶體115。 連接電晶體115是具有由輸出端子或是輸入端子所形 成之第1、第2主端子，和用以控制上述第1、第2之主 端子間之導通的控制端子。 在此，連接電晶體H5爲η通道MOSFET，控制端子 -10- 1373982 被稱爲閘極端子。該閘極端子被連接於資料線111。 有機EL層40之表面上被配置有畫素電極43。控制 電晶體115之第1主端子爲汲極端子，畫素電極43被連 接於其汲極端子上。 再者，第2主端子爲源極端子，該源極端子是被連接 於掃描線1 12。 資料線111和掃描線112是各被連接於導通控制電路 113和電壓施加電路114。導通控制電路113和電壓施加 電路114是被構成各可施加電壓至所欲之資料線111和掃 描線112上，當特定之資料線111和掃描線112被施加電 壓時，則選擇被連接於其資料線111和掃描線112之雙方 的畫素110，僅導通其畫素110之連接電晶體115。 藉由連接電晶體115之導通，被連接於其連接電晶體 1 15之畫素電極43是連接於掃描線1 12上，有機EL層 則被施加電壓。依據該電壓當電流流通於有機EL層 4〇時，有機EL層40則發光，自所選擇之畫素1 1〇放射 發光光線。 以下，針對將P型和η型之一方當作第1導電型’且 將另一方當作第2導電型的畫素110之構造及製造工程予 以說明。 第1圖之符號1 〇是由以矽單晶構成之矽晶圓1 0 1之 一部分所形成之第1導電型之半導體基板。當將第2導電 型之雜質注入至其背面側，並予以擴散時，則如第2圖所 示般，形成由第2導電型之擴散層所形成之共通電極 -11 - 1373982 11。第1導電型爲η型，第2導電型爲P型之時，第2導 電型之雜質則可以使用硼。該是第2導電型之雜質被注入 至半導體基板10背面之全面，因此’共通電極11是被形 成在半導體基板10之背面側之全面上。共通電極11之厚 度設成2000A~5000A。電阻以5~10Ω/□左右爲佳。 接著，對於與形成有半導體基板1〇之共通電極11之 面相反的面，反複執行微影成像工程或蝕刻工程或雜質注 入工程或擴散工程等，除了 η通道MOSFET或Ρ通道 MOSFET之外，因應所需，形成電阻元件或電容器等之電 子元件。 第3圖之符號115是表示形成擴散區域後之狀態的連 接電晶體，具有屬於第2導電型之雜質區域之通道區域 31;被配置在該通道區域31之內部的第1導電型之源極 區域32和汲極區域33。 以下，在圖面上表示該連接電晶體115，不圖示構成 導通控制電路113或電壓施加電路114之電子零件之剖 面。 通道區域31是在形成1個顯示裝置102之區域內被 配置成行列狀，源極區域32和汲極區域33是一個一個互 相分開被設置在1個通道區域31內。 然後，在至少使以源極區域32和汲極區域33所包夾 之部分的通道區域31之表面予以露出之狀態下，如第4 圖所示形成由絕緣性物質所形成之閘極絕緣膜13。該雖 然是閘極絕緣膜13爲矽氧化膜，使包含有通道區域31和 -12- 1373982 元及區域32和汲極區域33之表面的半導體基板10之表 面全部露出，藉由熱氧化處理等.所形成，但是並不限定於 氧化膜。 接著，如第5圖所示般，在閘極絕緣膜13之表面形 成聚矽等之導電性材料所構成之導電性薄膜14。 接著，如第6圖所示般，圖案製作導電性薄膜14, 至少除去形成有後述之孔20或開口 16之部分。另一方 面，殘留源極區域32和汲極區域33之間的位置部分，依 據殘留之部分構成閘極電極34。 接著，如第7圖所示般，在包含有閘極絕緣膜13或 閘極電極3 4之表面的半導體基板1 0之單側表面上，形成 由絕緣材料所形成之第1層絕緣膜15,依據微影成像工 程和蝕刻工程，至少除去第1層間絕緣膜1 5中，源極區 域3 2上之部分和汲極區域3 3上之部分，如第8圖所示 般，在源極區域32和汲極區域33上形成開口 16。 在該開口 16之底面上，露出有源極區域32或汲極區 域33之表面，在其狀態下依據濺鍍法等，如第9圖所示 般，在層間絕緣膜15之表面和開口 16之內部形成金屬膜 17。開口 16之內部是由金屬膜17塡充。當除去金屬膜 17中，開口 16之內部部分以外之部分時，則如第10圖 所示般，取得下端接觸於源極區域32或是汲極區域33之 插塞18»位於不同開口 16之內部的插塞18彼此爲互相 分離，在第1 〇圖之狀態中，插塞1 8彼此是互相電性絕 緣0 -13- 1373982 接著，藉由微影成像工程和蝕刻工程 體115之間之位置的第1層間絕緣膜15禾 和半導體基板10，如第11圖所示般，形总 各孔20是被形成在通道區域31或源 極區域33不接觸之位置上，貫通第1層間 極絕緣膜1 3 »在各孔20之上部側面上露！ 1 3和第1層間絕緣膜1 5。 各孔20不貫通半導體基板10，各孔 通電極11被露出在各孔20之底面的深度 面除了位於共通電極Π之表面的情形外 電極11之內部，共通電極Π露出於各孔 端亦可。 在比各孔側面之共通電極1 1還上方 10之表面還下方之部分，露出有半導體基 電型之部分。再者，各孔20是以一定距ρ 行列狀。 接著，藉由噴墨法等噴出電洞輸送性；； 至各孔20內，並予以加熱，當蒸發溶劑時 所示般，在孔20內形成電洞輸送性之第1 在此，第1有機薄膜35雖然與共通電 是即使在第1有機薄膜35和共通電極11 t 電性之緩衝層，不使第1有機薄膜35和共 接觸亦可。 接著，如第13圖所示般，圖所示般， ，蝕刻連接電晶 0閘極絕緣膜1 3 ^複數孔。 極區域32或汲 絕緣膜1 5和閘 ±1有閘極絕緣膜 20是被形成共 。各孔20之底 ，即使位於共通 20之側面的下 ，比半導體基板 板10之第1導 维分開被配置成 匕有機薄膜原料 ，則如第1 2圖 有機薄膜35。 極1 1接觸，但 匕間設置具有導 通電極11直接 在第1有機薄 -14 · 1373982 膜35之表面上，藉由噴墨法噴出並加熱有機材料，而形 成發光性之第2有機薄膜36,接著，如第ι4圖所示般， 在第2有機薄膜36表面上，當與第1、第2有機薄膜 35、36之形成方法相同，噴出並加熱有機材料而形成電 子輸送性之第3有機薄膜37時，藉由第丨〜第3之有機薄 膜35〜3 7而在各孔20內形成有機發光層40。不同之孔20 內之有機發光層40是互相被分離。有機材料是不被噴出 至孔20之外部。 在此’有機發光層40是被形成有機發光層40之表面 的高度與第1層間絕緣膜40之表面高度大略一致的厚 度。 接著’在閘極電極34上之無圖示位置中，於第1層 間絕緣膜1 5上形成開口，使閘極電極34表面露出至開口 之底面》 該狀態是第1層間絕緣膜15之表面，有機發光層40 之第3有機薄膜37之表面，和插塞18之上端也被露出， 其狀態如第15圖所示般，當藉由濺鍍法等形成第i配線 薄膜22時，插塞18之上端、有機發光層40之表面及閘 極電極34之表面等接觸於第1配線薄膜22。該第1配線 薄膜22、上述金屬膜17及後述之第2配線薄膜是可以使 用鋁等之金屬薄膜。 接著，圖案製作第1配線薄膜22，如第16圖所示 般，形成經由插塞18而被連接至源極區域32之源極配線 42，同樣的經由插塞1 8而被連接於汲極區域33，並覆蓋 -15- 1373982 有機發光層4表面之畫素電極43，和在無圖示之位 連接於閙極電極3 4之閘極配線。 源極配線42是被連接於掃描線112，閘極配線 連接於資料線111 » 在各有機發光層4G上各配置有畫素電極43，各 電極43彼此爲分離，被電性絕緣。再者，各晝素電ί 和源極配線42也分離，被電性絕緣。 第16圖之符號110是表示畫素。該畫素110是 具有1個連接電晶體115，和經由畫素電極43而被 於該連接電晶體Π5之汲極區域33(第1主端子）的1 機發光層40的畫素。 第1配線薄膜22之圖案製作時，藉由第1配線 22也形成掃描線112，與源極配線42連接。 接著，在源極配線42或畫素電極43或第1層間 膜15上，形成第2層間絕緣膜後，在第2層間絕緣 規定位置形成開口，使閘極電極34之一部分，或是 接於閘極電極34之第1配線薄膜22之一部分，露出 開口底面上的狀態下，在第2層間絕緣膜上形成第2 薄膜，當圖案製作，形成資料線1 1 1時，則如第1 7 示般，取得本發明之顯示裝置102。第17圖之符號1 表示第2層間絕緣膜，資料線Π1和掃描線112之間 由第2層間絕緣膜19而被絕緣。再者，掃描線112 極電極35之間是藉由第1層間絕緣膜15而被絕緣。 當形成顯示裝置1 之連接電晶體丨丨5時，則在 置被 是被 畫素 函43 表示 連接 個有 薄膜 絕緣 膜之 被連 在其 配線 圖所 9是 是藉 和閘 配置 -16- 1373982 有畫素110之區域外側，也形成與連接 電晶體（在此，爲η通道MOSFET或p 阻元件或二極體等之電子元件，依據該 有被連接於各連接電晶體115之控制端 路113和被連接於第2主端子之電壓施 該顯示裝置102是在半導體基板 以第1配線薄膜22或第2配線薄膜19 複數腳位（pad)，當該些腳位藉由打線 部電路時，導通控制電路113或電壓施 接至外部電路上。 再者，當共通電極11之表面被 102搭載在導線架（lead frame)使成 成藉由施加電壓至導線架而可以施力 11° —條資料線111上連接有被配置成 相同列的所有連接電晶體1 1 5之控制端 相同資料線111之所有連接電晶體1 ! 5 被連接於互相銅之掃描線112。 再者’一條掃描線112上連接有被 置1 02內之相同行之所有連接電晶體1 並且’被連接於相同掃描線1 1 2之所有 控制端子是互相被連接於不同資料線！ 當依據導通控制電路113和電壓施 1條資料線111和1條掃描線112而施 :電晶體115不同之 通道MOSFET)或電 丨些電子元件，形成 ί子上的導通控制電 加電路1 1 4。 1 〇之表面側上具有 之一部分所構成之 接合等而連接於外 加電路1 1 4則被連 露出，將顯示裝置 電性連接時，則構 口電壓至共通電極 1個顯示裝置102 子，並且被連接於 之第2主端子，是 配置成1個顯示裝 15之第2主端子， 連接電晶體1 1 5之 1 1上。 丨加電路1 1 4，選擇 加電壓時，則僅被 -17- 1373982 連接該資料線111和掃描線112之1個連接電晶體115導 通》 第1導電型爲η，連接電晶體115爲η通道MOSFET 時，先將正電壓施加至1條資料線111，將另—資料線 111連接至接地電位上。並且’先將1條掃描線112連接 於接地電位，將另一掃描線112施加至正電壓。 因在共通電極11和半導體基板10之第1導電型1〇 之第1導電型之部分之間形成有ρη接合，故第1導電型 爲η型’共通電極11爲ρ型之時，則在將正電壓施加至 共通電極11，並對與共通電及11接觸之半導體基板1〇 之第1導電型之部分，施加與共通電極11相同或比較高 之正電壓’而使ρη接合逆偏壓之狀態下，當導通所選擇 之連接電晶體115而將畫素電極43連接於資料線η時， 則在有機發光層40之表面和背面之間施加電壓。 當施加電壓至有機發光層40時，則在第1、第3有 機薄膜35、37內各流通電洞和電子，在第2有機薄膜36 內結合而第2有機薄膜36發光。 共通電極 11被設定成 200nm(200 xl(T9m)以上 500nm(500xl(T9m)以下之厚度，以單晶矽構成半導體基板 1〇時，可是光之透過率則爲85%以上。 因此，發光光線透過第1有機薄膜35或共通電極 Π，並被放射至外部》 共通電極 Π被架設在導線架時，則在配置有畫素 110之區域上之導線架之部分上先形成貫通孔等，使不會 -18- 1373982 遮蔽到發光光線。 然後，藉由在形成有畫素電極43之側面上形成凸 塊，將凸塊連接於硬配線基板或是撓性配線基板，當將顯 示裝置102搭載於配線基板時，因可以使共通電極11表 面予以露出，故不截斷發光光線。此時，藉由打線接合等 將共通電極11連接於硬配線基板或撓性配線基板，共通 電極11也被連接於外部電路。例如，可以在不遮蔽到共 通電極11之發光光線的部分上形成金屬薄膜，將其金屬 薄膜當作電極而連接打線接合之金屬細線。 上述實施例雖然是連接電晶體115爲η通道MOSFET 時，但是亦可以使用Ρ通道電晶體或雙極電晶體等，其他 開關元件。 再者，上述實施例雖然將η通道MOSFET之汲極端 子連接至畫素電極43，使掃描線112成爲接地電位而將 正電壓施加至共通電極11，但是即使將η通道MOSFET 之源極端子連接至畫素電極，並使共通電極11成接地電 位而將正電壓施加至掃描線112上，在有機發光層流通電 流亦可。此時，接觸於共通電極之第1有機薄膜35成爲 電子輸送性，接觸於畫素電極43之第3有機薄膜37成爲 電子輸送性。 上述實施例中，雖然共通電極Π被設爲1個，各有 機發光層40之單面被設爲電性相同電位，但是於將第2 導電型之雜質注入至半導體基板1 〇之背面時，亦可以將 圖案製作後的矽氧化膜等當作罩幕，圖案製作共通電極 -19- 1373982 11。例如，亦可以依據共通電極11形成平行之複數配 線，將被配置成行列狀之有機發光層40之相同行或是相 同列之有機發光層40連接於相同之共通電極11之配線^ 再者，上述實施例中，雖然半導體基板10是由單晶 矽所構成，但是即使除了矽之多晶外，即使爲以 GaAs 等、其他之半導體之單晶或多晶所構成之半導體基板亦 可。 本發明並不限定於以各畫素爲相同單色之光所發光之 情形，也包含以RGB三色之R、G、B所發光，可以執行 彩色顯示之情形。再者，以單色發光時，也包含在共通電 極1 1側配置彩色濾光片，執行彩色顯示之時。 並且，在半導體基板10上形成共通電極11後，即使 硏磨其共通電極11之表面，或硏磨半導體基板10之背 面，薄化半導體基板10之厚度後，形成共通電極，薄化 存在於孔20底面之半導體基板10之厚度（上述實施例中 爲共通電極11之厚度）亦可。 【圖式簡單說明】 第1圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（1 )。 第2圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（2 )。 第3圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（3 )。 -20- 1373982 第4圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（Ο 。 第5圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（5 )。 第6圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（6 )。 第7圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（7 )。 第8圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（8 )。 第9圖是用以說明本發明之顯示裝置之製造工程的剖 面圖（9 )。 第10圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 0 )。 第11圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 1 ).。 第12圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 2 )。 第13圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 3 )。 第14圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 4 )。 第15圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 5 )。 -21 - 1373982 第16圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 6 )。 第17圖是用以說明本發明之顯示裝置之製造工程的 剖面圖（1 7 )。 第18圖是用以說明本發明之顯示裝置之半導體基板 內之配置的平面圖。 第19圖是用以說明本發明之顯示裝置之模式性平面 圖β 第20圖是用以說明本發明之顯示裝置之畫素的模式 性平面圖。 【主要元件符號說明】 10 :半導體基板 Π :共通電極 20 :孔 4〇 :有機發光層 43 :畫素電極 102 :顯示裝置 1 1 5 :連接電晶體 -22-1373982 IX. Description of the Invention [Technical Field] The present invention relates to the technology of an organic EL device, and more particularly to an organic EL device of ITO (Indium-tin oxide). [Prior Art] When a head mounted display or a projector organic EL display device is used, it is necessary to produce a compact and high-quality roll display device. In order to produce a small and high-quality organic EL, it is necessary to form a light-emitting element portion. However, it is difficult to realize such a fine light-emitting element by a method of forming a bright electrode such as ITO on a glass substrate as in the related art. Since a film is formed by sputtering on a general ITO film, unevenness or deficiency may occur. Splash causes the ITO film to have uneven defects. When the ITO film is thinned by realizing a small organic EL, such a defect causes a short circuit. Further, since the ITO film formed by sputtering is grown in an anisotropic manner, it is not dense. Therefore, in the case where the etching liquid used in patterning is introduced into the ITO film, the organic layer formed on the ITO film is damaged. Therefore, when ITO is used, it is difficult to produce a small organic EL device. Further, in order to lower the electric resistance, the ITO film must be fired at 200 °C. [Patent Document 1] Japanese Patent Application No. 2 -76884 is used. In the case of the smear, it is easy to be fine, and it is the first to be retracted 1 371 982. [Patent Document 2] Japanese Laid-Open Patent Publication No. 2002-237383 [Draft of the Invention] The object of the present invention is to use a Si wafer. Instead of the glass substrate, a compact and high-quality organic EL display device was produced. Further, an object of the present invention is to provide an organic EL display device having a fine light-emitting element without using ITO. [Means for Solving the Problem] In order to solve the above problems, the invention according to claim 1 is a display device comprising: a semiconductor substrate; and a plurality of connected transistors formed on the semiconductor substrate a plurality of holes formed in the semiconductor substrate; an organic light-emitting layer that is disposed in each of the holes and emits light when a current flows; and a pixel electrode that is disposed on a surface of the organic light-emitting layer, and each of the connections The transistor is a control terminal having first and second main terminals, and a control terminal for controlling conduction between the first and second main terminals, wherein the pixel electrodes on the respective organic light-emitting layers are electrically separated from each other. The display unit according to the first aspect of the invention, wherein each of the pixel electrodes is connected to the first connection terminal of the above-mentioned connection transistor, wherein the display unit is the display device according to the first aspect of the invention. The hole is formed with a bottom surface ′ with a common electrode exposed on the bottom surface, and the bottom surface of the organic light-emitting layer is in contact with the common electrode. The display device according to the invention of claim 2, wherein the common electrode is an impurity region formed inside the semiconductor substrate. The invention according to claim 4, wherein the thickness of the bottom surface of the semiconductor substrate and the bottom surface of each of the holes is set to be 500 nm or less. The light emitted by the organic light-emitting layer is radiated to the outside through the semiconductor substrate on the bottom surface of the hole. The display device according to any one of claims 3, wherein the conductivity type of the impurity region is opposite to the semiconductor substrate. type. The invention described in claim 6 is a display device comprising: a semiconductor substrate; a plurality of holes formed on the semiconductor substrate; and common electrodes each located on a bottom surface of each of the holes; An organic light-emitting layer disposed in each of the holes; and a pixel electrode disposed on the surface of each of the organic light-emitting layers and electrically separated from each other, a voltage is applied between the common electrode and the pixel electrode, and a current is applied In the display device in which the organic light-emitting layer emits light when the organic light-emitting layer is circulated, the common electrode is formed of an impurity region formed in the semiconductor substrate. The invention according to claim 6, wherein the display device according to claim 6 is characterized in that a plurality of connection transistors are formed in the semiconductor substrate, and each of the connection transistors has a first, a first, a The second main terminal and the control terminal for controlling conduction between the first and second main terminals, wherein the pixel electrodes are connected to the first main terminal of the different connection transistor. The display device according to any one of claims 6 to 7, wherein the bottom surface of the semiconductor substrate and the bottom surface of each of the holes are The thickness is set to be 200 nm or more and 500 nm or less, and the light emitted by the organic light-emitting layer is radiated to the outside through the semiconductor substrate that penetrates the bottom surface of the hole. The display device according to any one of claims 1 to 5, 7 and 8, wherein the semiconductor substrate is formed to be electrically connected to the semiconductor substrate. a plurality of electronic components having different crystals, wherein the electronic component forms a conduction control circuit connected to the control terminal of each of the connection transistors, and is connected to the second main terminal. a voltage application circuit that turns on a desired transistor in the plurality of connected transistors by the conduction control circuit and the voltage application circuit, and supplies a current to the first electrode connected to the connected transistor The organic light-emitting layer of the main terminal is configured to cause the organic light-emitting layer to emit light. The invention according to claim 1 is a method of manufacturing a display device, comprising the step of introducing a second conductivity type impurity into a back surface of a semiconductor substrate of a first conductivity type, and forming a common electrode a step of forming a plurality of holes on the surface of the semiconductor substrate, exposing the common electrode to the respective holes; forming an organic light-emitting layer in the holes; and forming a pixel electrode on the surface of each of the organic light-emitting layers - 8- 1373982. The invention of the display device according to the invention, wherein the invention provides a method of manufacturing a display device according to the invention, wherein the channel region in which the second conductivity type is formed in the semiconductor substrate is provided in the channel Each of the first and second regions in which the first conductivity type is separated from each other is formed in the region, and a step of connecting the transistors is formed, and the first region is connected to the pixel electrodes. In the present invention, a bottomed hole is formed on a semiconductor substrate, and an organic light-emitting layer is formed in the hole. On the bottom surface of the hole, a diffusion region having a low resistivity is disposed by impurity diffusion. Think of this as a common electrode. Then, when the thickness of the common electrode existing on the bottom surface of each hole, that is, the thickness of the semiconductor crystal of the portion when the common electrode is formed of the semiconductor crystal constituting the semiconductor substrate, the illuminating light of the organic luminescent layer can be transmitted first. At the thickness of the light, the illuminating light is transmitted to the outside through the common electrode. Therefore, it is necessary to emit light from the surface opposite to the common electrode from the surface of the organic light-emitting layer, so that the metal electrode can be disposed on the surface opposite to the common surface. [Effect of the Invention] In the present invention, since a part of a semiconductor wafer is used as an electrode, an organic EL display device having a fine light-emitting element can be formed without using ITO. Further, since the present invention does not require an LSI to manufacture a high-quality semi-conductive 1373982 bulk wafer, it is possible to use an LSI specification that has been discarded or not used as a recycling resource, for example, a Si wafer other than the specification. [Embodiment] The reference numeral 101 in Fig. 18 is a semiconductor wafer, and a plurality of display devices 102 of the present invention are formed. Each of the display devices 102 is arranged in a matrix, and semiconductors on the scribe lines 1 〇 3 X, l 〇 3 y » scribe lines 103 x , 103 y are arranged between rows and columns and between columns and columns of the display devices 102 . The surface of the wafer 101 is exposed, and when the portions of the scribe lines I?3x, 103y are cut, the display devices 102 are separated. Fig. 19 is a schematic plan view for explaining the structure of one display device 102, and the protective film and the first and second interlayer insulating films to be described later are omitted. The display device 102 has a plurality of pixels 110 corresponding to a display unit of a minimum of 1 pixel. Each pixel 110 is arranged in a matrix, between rows and columns of pixels 1 1 and between columns and columns. Each is surrounded by a scan line 1 1 2 and a data line 11 1 . Fig. 20 is a schematic plan view of the magnified pixel 110, each of which has an organic EL layer 40, and a connection transistor 115. The connection transistor 115 has a first and a second main terminal formed by an output terminal or an input terminal, and a control terminal for controlling conduction between the first and second main terminals. Here, the connection transistor H5 is an n-channel MOSFET, and the control terminal -10- 1373982 is called a gate terminal. The gate terminal is connected to the data line 111. A pixel electrode 43 is disposed on the surface of the organic EL layer 40. The first main terminal of the control transistor 115 is a 汲 terminal, and the pixel electrode 43 is connected to its 汲 terminal. Further, the second main terminal is a source terminal, and the source terminal is connected to the scanning line 112. The data line 111 and the scan line 112 are each connected to the conduction control circuit 113 and the voltage application circuit 114. The turn-on control circuit 113 and the voltage application circuit 114 are configured to apply voltages to the desired data lines 111 and scan lines 112. When a particular data line 111 and scan line 112 are applied with a voltage, they are selectively connected to them. The pixel 110 of both the data line 111 and the scan line 112 turns on only the connection transistor 115 of the pixel 110. By the conduction of the connection transistor 115, the pixel electrode 43 connected to the connection transistor 1 15 is connected to the scanning line 112, and the organic EL layer is applied with a voltage. According to this voltage, when the current flows through the organic EL layer 4, the organic EL layer 40 emits light, and emits light from the selected pixel 1 1 . Hereinafter, the structure and manufacturing process of the pixel 110 in which one of the P type and the η type is regarded as the first conductivity type and the other is regarded as the second conductivity type will be described. The symbol 1 in Fig. 1 is a first conductivity type semiconductor substrate formed of a part of a germanium wafer 10 made of a germanium single crystal. When the second conductivity type impurity is implanted into the back surface side and diffused, as shown in Fig. 2, the common electrode -11 - 1373982 11 formed of the second conductivity type diffusion layer is formed. When the first conductivity type is an η type and the second conductivity type is a P type, boron can be used as the impurity of the second conductivity type. Since the impurities of the second conductivity type are implanted into the entire surface of the back surface of the semiconductor substrate 10, the common electrode 11 is formed on the entire back side of the semiconductor substrate 10. The thickness of the common electrode 11 is set to 2000A to 5000A. The resistance is preferably about 5 to 10 Ω/□. Next, for the surface opposite to the surface on which the common electrode 11 of the semiconductor substrate 1 is formed, lithography imaging engineering or etching engineering or impurity implantation engineering or diffusion engineering is repeatedly performed, except for the n-channel MOSFET or the germanium channel MOSFET. It is necessary to form an electronic component such as a resistor element or a capacitor. Reference numeral 115 in Fig. 3 denotes a connection transistor in a state in which a diffusion region is formed, a channel region 31 having an impurity region belonging to the second conductivity type, and a source of a first conductivity type disposed inside the channel region 31. Region 32 and drain region 33. Hereinafter, the connection transistor 115 is shown on the drawing, and the cross section of the electronic component constituting the conduction control circuit 113 or the voltage application circuit 114 is not shown. The channel region 31 is arranged in a matrix in a region where one display device 102 is formed, and the source region 32 and the drain region 33 are disposed one by one in one channel region 31. Then, in a state where at least the surface of the channel region 31 sandwiched by the source region 32 and the drain region 33 is exposed, a gate insulating film formed of an insulating material is formed as shown in FIG. 13. Although the gate insulating film 13 is a tantalum oxide film, the surface of the semiconductor substrate 10 including the channel region 31 and the surface of the region 12 and the drain region 33 is exposed, and is subjected to thermal oxidation treatment or the like. Formed, but not limited to an oxide film. Next, as shown in Fig. 5, a conductive thin film 14 made of a conductive material such as polyfluorene is formed on the surface of the gate insulating film 13. Next, as shown in Fig. 6, the conductive film 14 is patterned to remove at least a portion in which the hole 20 or the opening 16 to be described later is formed. On the other hand, the positional portion between the residual source region 32 and the drain region 33 constitutes the gate electrode 34 in accordance with the remaining portion. Next, as shown in Fig. 7, on the one-side surface of the semiconductor substrate 10 including the surface of the gate insulating film 13 or the gate electrode 34, a first insulating film 15 formed of an insulating material is formed. According to the lithography imaging process and the etching process, at least the portion of the first interlayer insulating film 15, the portion of the source region 3 2 and the portion of the drain region 3 3 are removed, as shown in Fig. 8, at the source An opening 16 is formed in the region 32 and the drain region 33. On the bottom surface of the opening 16, the surface of the source region 32 or the drain region 33 is exposed, and in the state thereof, the surface of the interlayer insulating film 15 and the opening 16 are formed according to a sputtering method or the like as shown in FIG. A metal film 17 is formed inside. The inside of the opening 16 is filled with a metal film 17. When the portion other than the inner portion of the opening 16 of the metal film 17 is removed, as shown in Fig. 10, the plug 18» having the lower end contacting the source region 32 or the drain region 33 is located at a different opening 16. The internal plugs 18 are separated from each other. In the state of the first figure, the plugs 18 are electrically insulated from each other 0 - 13 - 1373982. Next, by lithography imaging engineering and etching the work body 115 In the position of the first interlayer insulating film 15 and the semiconductor substrate 10, as shown in FIG. 11, the total holes 20 are formed at positions where the channel region 31 or the source region 33 does not contact, and penetrate the first interlayer. The insulating film 1 3 » is exposed on the upper side of each hole 20! 1 3 and a first interlayer insulating film 15 . Each of the holes 20 does not penetrate the semiconductor substrate 10, and the hole-passing electrodes 11 are exposed on the bottom surface of each of the holes 20 except for the surface of the common electrode, and the common electrode is exposed to each of the holes. . A portion of the semiconductor-based electric type is exposed at a portion below the surface of the upper surface 10 of the common electrode 1 1 on the side of each of the holes. Further, each of the holes 20 is arranged in a line ρ of a certain distance. Then, the hole transport property is ejected by an inkjet method or the like; the inside of each of the holes 20 is heated, and as shown in the case of evaporating the solvent, the first hole transport property is formed in the hole 20, and the first The organic thin film 35 is electrically connected to the first organic thin film 35 and the common electrode 11 t, and the first organic thin film 35 may not be in common contact with each other. Next, as shown in Fig. 13, as shown in the figure, the connection of the electro-crystal 0 gate insulating film 13 3 ^ plurality of holes is etched. The pole region 32 or the 绝缘 insulating film 15 and the gate ±1 gate insulating film 20 are formed in common. The bottom of each of the holes 20 is disposed as a thin film of the organic thin film material, as shown in Fig. 2, even if it is located below the side surface of the common layer 20, and is disposed apart from the first guide of the semiconductor substrate 10. The pole 11 is in contact with the conductive electrode 11 directly on the surface of the first organic thin-14 · 1373982 film 35, and the organic material is sprayed and heated by an inkjet method to form a second organic thin film 36. Then, as shown in Fig. 4, on the surface of the second organic film 36, in the same manner as the first and second organic thin films 35 and 36, the organic material is discharged and heated to form the third electron transport property. In the case of the organic thin film 37, the organic light-emitting layer 40 is formed in each of the holes 20 by the third to third organic thin films 35 to 37. The organic light-emitting layers 40 in the different holes 20 are separated from each other. The organic material is not ejected to the outside of the hole 20. Here, the organic light-emitting layer 40 has a thickness at which the height of the surface on which the organic light-emitting layer 40 is formed is substantially the same as the surface height of the first interlayer insulating film 40. Then, in the unillustrated position on the gate electrode 34, an opening is formed in the first interlayer insulating film 15 to expose the surface of the gate electrode 34 to the bottom surface of the opening. This state is the surface of the first interlayer insulating film 15. The surface of the third organic film 37 of the organic light-emitting layer 40 and the upper end of the plug 18 are also exposed, and the state is as shown in Fig. 15, when the ith wiring film 22 is formed by sputtering or the like. The upper end of the plug 18, the surface of the organic light-emitting layer 40, and the surface of the gate electrode 34 are in contact with the first wiring film 22. The first wiring film 22, the metal film 17 and a second wiring film to be described later may be formed of a metal film such as aluminum. Next, the first wiring film 22 is patterned, and the source wiring 42 connected to the source region 32 via the plug 18 is formed as shown in Fig. 16, and is similarly connected to the drain via the plug 18. The region 33 covers the pixel electrode 43 on the surface of the -15-1373982 organic light-emitting layer 4, and the gate wiring connected to the drain electrode 34 at a position not shown. The source wiring 42 is connected to the scanning line 112, and the gate wiring is connected to the data line 111. Each of the organic light-emitting layers 4G is provided with a pixel electrode 43, and the electrodes 43 are separated from each other and electrically insulated. Further, each of the halogen electrodes and the source wiring 42 are also separated and electrically insulated. The symbol 110 of Fig. 16 is a representation of a pixel. The pixel 110 is a pixel having one connected transistor 115 and a single-layer light-emitting layer 40 connected to the drain region 33 (first main terminal) of the transistor 经由5 via the pixel electrode 43. At the time of patterning of the first wiring film 22, the scanning line 112 is also formed by the first wiring 22, and is connected to the source wiring 42. Next, after the second interlayer insulating film is formed on the source wiring 42 or the pixel electrode 43 or the first interlayer film 15, an opening is formed at a predetermined position between the second interlayer insulation, and a part of the gate electrode 34 is connected to When one of the first wiring films 22 of the gate electrode 34 is exposed on the bottom surface of the opening, a second film is formed on the second interlayer insulating film, and when the pattern is formed to form the data line 1 1 1 , the first 7 is formed. In general, the display device 102 of the present invention is obtained. Reference numeral 1 in Fig. 17 denotes a second interlayer insulating film, and the data line Π1 and the scanning line 112 are insulated by the second interlayer insulating film 19. Further, the scanning line 112 between the electrode electrodes 35 is insulated by the first interlayer insulating film 15. When the connection transistor 丨丨5 of the display device 1 is formed, the connection is indicated by the pixel 43 to indicate that a thin film insulating film is connected to the wiring pattern. The wiring pattern is 9 and is a gate arrangement-16-1373982 On the outer side of the region having the pixel 110, an electronic component such as an n-channel MOSFET or a p-resistive element or a diode is formed and connected, and the control terminal connected to each of the connected transistors 115 is formed according to the electronic circuit. 113 and a voltage connected to the second main terminal, the display device 102 is a plurality of pads on the semiconductor substrate by the first wiring film 22 or the second wiring film 19, and when the pins are connected by the wire portion circuit The conduction control circuit 113 or the voltage is applied to the external circuit. Further, when the surface of the common electrode 11 is mounted on the lead frame so as to be applied to the lead frame by applying a voltage to the lead frame, the force can be applied by 11°. All the connecting transistors 1 ! 5 of the same data line 111 connected to the control terminals of all the connected transistors 1 1 5 arranged in the same column are connected to the scanning lines 112 of the mutual copper. Connected to line 112 All the connected transistors 1 in the same row of 1 02 are placed and all the control terminals connected to the same scanning line 1 1 2 are connected to different data lines! When the data is applied according to the conduction control circuit 113 and the voltage The line 111 and the one scanning line 112 are applied to: a different channel MOSFET of the transistor 115) or the electronic components are electrically connected to form a conduction control electric adding circuit 1 14 on the ί. 1 is connected to the external circuit 1 1 4 on the surface side of the crucible and connected to the external circuit 1 1 4, and when the display device is electrically connected, the voltage is applied to the common electrode 1 display device 102, and The second main terminal to be connected is a second main terminal that is disposed in one display package 15, and is connected to the eleven of the transistors 1 1 5 . When the voltage is applied, the voltage is selected, and only one of the data lines 111 and the scan line 112 connected to the signal line 111 is turned on by -17-1373982. The first conductivity type is η, and the connection transistor 115 is η. For the channel MOSFET, a positive voltage is first applied to one data line 111, and the other data line 111 is connected to the ground potential. And, one scanning line 112 is first connected to the ground potential, and the other scanning line 112 is applied to the positive voltage. Since the ρη junction is formed between the common electrode 11 and the portion of the first conductivity type of the first conductivity type 1〇 of the semiconductor substrate 10, when the first conductivity type is the n-type 'common electrode 11 is p-type, then A positive voltage is applied to the common electrode 11, and a positive voltage "the same as or higher than the common electrode 11" is applied to a portion of the first conductivity type of the semiconductor substrate 1 that is in contact with the common current and 11 to make the ρη junction reverse bias In the state where the selected connection transistor 115 is turned on and the pixel electrode 43 is connected to the data line η, a voltage is applied between the surface and the back surface of the organic light-emitting layer 40. When a voltage is applied to the organic light-emitting layer 40, holes and electrons are distributed in the first and third organic thin films 35 and 37, and the second organic thin film 36 is combined in the second organic thin film 36 to emit light. The common electrode 11 is set to have a thickness of 200 nm (200 x 1 (T9 m) or more and 500 nm (500 x 1 (T9 m) or less), and when the semiconductor substrate is formed of single crystal germanium, the light transmittance is 85% or more. When the first organic film 35 or the common electrode Π is radiated to the outside, when the common electrode 架 is mounted on the lead frame, a through hole or the like is formed in a portion of the lead frame on the region where the pixel 110 is disposed. The illuminating light is not blocked by -18 - 1373982. Then, by forming a bump on the side surface on which the pixel electrode 43 is formed, the bump is connected to the hard wiring substrate or the flexible wiring substrate, and the display device 102 is mounted. In the case of the wiring board, the surface of the common electrode 11 can be exposed, so that the illuminating light is not cut off. In this case, the common electrode 11 is connected to the hard wiring board or the flexible wiring board by wire bonding or the like, and the common electrode 11 is also connected. In the external circuit, for example, a metal thin film may be formed on a portion where the illuminating light of the common electrode 11 is not shielded, and the metal thin film may be used as an electrode to connect the wire-bonded metal thin wires. In the embodiment, although the connection transistor 115 is an n-channel MOSFET, a germanium channel transistor, a bipolar transistor, or the like may be used, and other switching elements. Further, although the above embodiment connects the anode terminal of the n-channel MOSFET to The pixel electrode 43 causes the scanning line 112 to have a ground potential and applies a positive voltage to the common electrode 11, but even if the source terminal of the n-channel MOSFET is connected to the pixel electrode and the common electrode 11 is grounded, a positive voltage is applied. It is applied to the scanning line 112, and a current may flow through the organic light-emitting layer. At this time, the first organic thin film 35 that is in contact with the common electrode has electron transport properties, and the third organic thin film 37 that is in contact with the pixel electrode 43 serves as electron transporting property. In the above embodiment, the common electrode Π is one, and the single surface of each of the organic light-emitting layers 40 is electrically the same potential, but when the second conductivity type impurity is implanted into the back surface of the semiconductor substrate 1 Alternatively, the patterned ruthenium oxide film or the like can be used as a mask to pattern the common electrode -19- 1373982 11. For example, it is also possible to form a parallel complex according to the common electrode 11. For wiring, the same row of the organic light-emitting layers 40 arranged in the matrix or the wirings of the same column of the organic light-emitting layer 40 are connected to the same common electrode 11 . In the above embodiment, the semiconductor substrate 10 is Although it is composed of a germanium, it may be a semiconductor substrate composed of a single crystal or a polycrystal of another semiconductor such as GaAs, in addition to polycrystalline germanium. The present invention is not limited to the same single pixel. The case where the light of the color is emitted also includes the case where the color is displayed by R, G, and B of the three colors of RGB, and the color display can be performed. Further, when the light is emitted in a single color, the color filter is also disposed on the side of the common electrode 1 1 . Light sheet, when performing color display. Further, after the common electrode 11 is formed on the semiconductor substrate 10, even if the surface of the common electrode 11 is honed or the back surface of the semiconductor substrate 10 is honed, the thickness of the semiconductor substrate 10 is thinned, and a common electrode is formed, and thinning is present in the hole. The thickness of the semiconductor substrate 10 on the bottom surface (the thickness of the common electrode 11 in the above embodiment) may be used. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view (1) for explaining a manufacturing process of a display device of the present invention. Fig. 2 is a cross-sectional view (2) for explaining the manufacturing process of the display device of the present invention. Fig. 3 is a cross-sectional view (3) for explaining the manufacturing process of the display device of the present invention. -20- 1373982 Fig. 4 is a cross-sectional view for explaining the manufacturing process of the display device of the present invention (Fig. 5 is a cross-sectional view (5) for explaining the manufacturing process of the display device of the present invention. Fig. 6 It is a cross-sectional view (6) for explaining the manufacturing process of the display device of the present invention. Fig. 7 is a cross-sectional view (7) for explaining the manufacturing process of the display device of the present invention. Fig. 8 is a view for explaining the present invention. Sectional view (8) of the manufacturing process of the display device. Fig. 9 is a cross-sectional view (9) for explaining the manufacturing process of the display device of the present invention. Fig. 10 is a view for explaining the manufacturing process of the display device of the present invention. Figure 11 is a cross-sectional view (1 1 ) for explaining the manufacturing process of the display device of the present invention. Fig. 12 is a cross-sectional view for explaining the manufacturing process of the display device of the present invention. (1 2 ) Figure 13 is a cross-sectional view (13) for explaining the manufacturing process of the display device of the present invention. Figure 14 is a cross-sectional view (1 4) for explaining the manufacturing process of the display device of the present invention. Figure 15 is a view for explaining the display device of the present invention Sectional view of the manufacturing process (15). -21 - 1373982 Fig. 16 is a cross-sectional view (16) for explaining the manufacturing process of the display device of the present invention. Fig. 17 is a view showing the display device of the present invention. Fig. 18 is a plan view showing the arrangement in the semiconductor substrate of the display device of the present invention. Fig. 19 is a schematic plan view showing the display device of the present invention. 20 is a schematic plan view for explaining the pixels of the display device of the present invention. [Description of main components] 10: semiconductor substrate Π: common electrode 20: hole 4: organic light-emitting layer 43: pixel electrode 102: display Device 1 1 5: Connected to the transistor-22-