1373749 九、發明說明： 【發明所屬之技術領域】 . 本發明係關於一種測試系統及測試方法，特別關於一 種平面顯示模組之測試系統及測試方法。 ψ 【先前技術】 平面顯示模組可依據驅動方式而區分為被動矩陣型 (Passive-Matrix, PM )及主動矩陣型（Active-Matrix, 鲁 AM)，其中，由於主動矩陣型較被動矩陣型可提供更優良 的性能而成為主流。較常見的主動矩陣型顯示模組有主動 矩陣型液晶顯示模組（AM-LCD Module )或是主動矩陣型 有機發光二極體模組。 請參照圖1所示，一般平面顯示模組1包含一顯示面 板11及一特殊應用積體電路（ASIC) 12，且在顯示面板 U之一侧設置一垂直移位暫存器Vertical Shift Register， φ VSR) ’其係與顯示面板u、特殊應用積體電路η電性連 接，在顯示面板丨丨之另一側設置一水平移位暫存器 (Horizontal Shift Register，HSR) 15，其係分別與顯示面 板11及特殊應用積體電路12電性連接。垂直移位暫存器 14與水平移位暫存器15係可同時整合於顯示面板U的同 一個基板13上。 顯示面板π係區分為N個顯示區m〜11N，特殊應 用積體電路12係發送-對反相之時脈訊號121、122、— 起始脈衝訊號123以及影像訊號124至水平移位暫存器 丄373749 ^特殊躺㈣電路12並發送f彡像㈣124 貝料線（S〇urce Line)傳送至水平移位暫存器15。i '122、起始脈衝訊號123及影像訊號m之 4序係晴參照圖2A所示。 動，器Γ系依捧起始脈衝訊號⑵開始作 動/、係減時脈訊號121、122產生複數個顯 訊號，藉以控制影像訊號124分別傳送至 。。幵 ^ χγ 0_ 乐一顯示區111〜 第Ν顯示區11Ν，其中第Ν顯示區開啟 號124傳送至第Ν顯示區11Ν以將各晝素的:身^^象= 此一來顯示區111〜11Ν即可顯示影像。 然而，受到製程或線路長度等影響， 存器15來說’影像訊號124並非和_訊號立暫 起始脈衝訊號123及顯示區開啟訊號同步。二 22、 所示，若各顯示區開啟訊號之相位領 ％參照圖2Α 時，將導致顯.示區111〜11Ν的晝素寫入時間 汛唬U4 產生殘影（Remnant Image );另一情況如圖。短以致於 顯示區開啟訊號之相位落後於影像訊货 所示，各 一顯示區之影像訊號124過早寫入，以致於 今導致下 (Overlapping Image)。 重邊影像 習知的解決方式是在平面顯示模組丨中内1 整功能，藉由人工方式來進行相位調整以達到相位調 然而’由於成本及生產時間的考量，不1位—欵； 顯 J月fci針對命^ 示模組1來單獨作調整，而是針對同一批 平面 面顯示 面顯示模組1來一起作調整及設定，即同—抵的出來的平 7 1373749 模組1具有相同的相位調整值，但如此仍會有一些平面顯. 示模組1無法適用，以致於需回收無法適用的平面顯示模 組1並逐一檢查以進行相位調整，如此一來，便大幅增加 成本並浪費時間，且降低平面顯示模組1之可靠度及效能。 因此，如何提供一種平面,顯示模組之測試系統及測試 方法，能夠自動針對各平面顯示模組進行相位調整以提高 影像顯示品質，進而節省成本、提升產品可靠度及效能， 實為當前重要課題之一。 【發明内容】 有鑑於上述課題，本發明之目的為提供一種能夠自動 測試平面顯示模組之訊號相位並自動做最佳化調整之測 試糸統及測試方法。 緣是，為達上述目的，依本發明之一種平面顯示模組 之測試系統包含一測試影像產生電路、一影像感測單元、 一相位調整電路以及一時序控制電路。測試影像產生電路 係產生一測試影像，且平面顯示模組係由時脈訊號所驅動 以顯示測試影像；影像感測單元係感測平面顯示模組所顯 示之測試影像以產生一擷取影像；相位調整電路係與影像 感測單元電性連接以接收擷取影像，並記錄擷取影像與測 試影像之一影像差異，且藉由改變相位調整訊號反覆測試 來得到最小的影像差異，產出最佳的相位調整信號；時序 控制電路係接收相位調整訊號，並依據相位調整訊號調整 時脈訊號之相位。 8 1373749 為達上述目的，依本發明之一種平面顯示模組之測試 方法包含一測試影像產生程序、一設定調整程序、一相位 調整程序、一影像感測程序、一差異記錄程序、再次執行 設定調整程序、相位調整程序、影像感測程序及差異記錄 程序以得到複敫個影像差異以，及一最佳化程序。測試影像 產生程序係產生一測試影像至平面顯示模組；設定調整程 序係產生一相位調整訊號；相位調整程序依據相位調整訊 號調整一時脈訊號之相位，其中平面顯示模組係由時脈訊 • 號所驅動以顯示測試影像；影像感測程序係感測平面顯示 模組所顯示之測試影像以產生一擷取影像；差異記錄程序 係記錄擷取影像與測試影像之一影像差異；最佳化程序係 從該等影像差異中判斷出差異最小者，並選取差異最小者 所對應之相位調整訊號作為一最佳值。 承上所述，因依本發明之一種平面顯示模組之測試系 統及測試方法_，係將影像感測單元來感測到的擷取影像 ^ 來和原始的測試影像進行比較，並依據比較的結果自動地 進行訊號的相位調整。因而免去習知所需要之回收、人工 再檢查等工作，進而降低成本，並提升產品之可靠度及效 能0 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之一 種平面顯示模組之測試系統及其測試方法。 請參照圖3所示，本發明較佳實施例之一測試系統2 9 /4^ 係包含-相位調整 時序控制電路23、〜21、一測試影像產生電路22、一 25以及―影像❹^㈣校正電路24、—雜驅動電路 別與測試影像產生|疋26。其中，相位調整電路21係分 測試影像產生電路22路22及影像感測單元26電性連接； 路24電性連接；伽2係與時夺控制電路23及伽瑪校正電 電性連接。 碼校正電路24係與源極驅動電路25 平面顯示模組3#&a 存器32與—水平移位暫3;顯不面板3卜—垂直移位暫 存器32與水平移位暫：器：:/3⑽，其中垂直移位暫 的同-個基板上，_ 何同時整合於顯示面板31 此外，本實施例之==模1係具有複數個顯示區域。 ;機=:::係—，顯 4::: 極驅= 傳送至源 MDS’並將賢料訊號Ds傳送至平面顯莫產生資料 移位暫存器33,時序控制電路^係輸出=的水平 CKH、XCKH *起始脈衝訊號咖至平模脈tfL號 水平移位料㈣，水平移㈣料33錢^=30的 CKH'XCKH及起始脈衝訊號订 ^寺脈吼號 訊號以讓各顯示區域依據資料訊號=區開啟 訊號⑽、取H、起始脈衝訊號則、資料時脈 顯不區開啟訊號之時序作動係請參照圖4所示。US及 1373749 請參照圖5所示，其係為圖 驟之流程圖。 之 測武系統2之測試步 首先，在測試影像產生程 路22係產生-測試影像TI，且測試^J試影像產生電 校jL電路24進行^彡;^i ^ 1係先經由伽瑪. 1 W W ^校正之後傳送至源極 源極驅動電路25依據測試影像TI產生 電路5平1373749 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a test system and a test method, and more particularly to a test system and test method for a flat display module. ψ [Prior Art] The flat display module can be divided into passive matrix type (Passive-Matrix, PM) and active matrix type (Active-Matrix, Lu AM) according to the driving method, wherein the active matrix type is more passive matrix type. Provide better performance and become mainstream. The more common active matrix display modules include an active matrix liquid crystal display module (AM-LCD Module) or an active matrix organic light emitting diode module. As shown in FIG. 1 , the general flat display module 1 includes a display panel 11 and an application specific integrated circuit (ASIC) 12 , and a vertical shift register Vertical Shift Register is disposed on one side of the display panel U. φ VSR) 'The system is electrically connected to the display panel u and the special application integrated circuit η, and a horizontal shift register (HSR) 15 is disposed on the other side of the display panel 15, The display panel 11 and the special application integrated circuit 12 are electrically connected. The vertical shift register 14 and the horizontal shift register 15 can be simultaneously integrated on the same substrate 13 of the display panel U. The display panel π is divided into N display areas m to 11N, and the special application integrated circuit 12 is a transmission-to-inverted clock signal 121, 122, a start pulse signal 123, and an image signal 124 to a horizontal shift temporary storage.丄 373749 ^ Special lay (four) circuit 12 and send f 彡 image (4) 124 料 urce line to the horizontal shift register 15 . The sequence of i '122, the start pulse signal 123 and the image signal m is shown in Fig. 2A. The motion signal is generated by the start pulse signal (2), and the clock signals 121 and 122 are generated to generate a plurality of display signals, so that the control image signals 124 are respectively transmitted to the signal. .幵^ χγ 0_ 乐一 display area 111~ Ν display area 11Ν, wherein the second display area opening number 124 is transmitted to the second display area 11Ν to display the respective elements: the body image = the display area 111~ 11Ν to display the image. However, due to the influence of the process or the length of the line, the memory 15 is not synchronized with the _ signal initial start pulse signal 123 and the display area turn-on signal. As shown in Fig. 22, if the phase collar % of each display area turn-on signal is as shown in Fig. 2, it will cause the pixel write time 汛唬U4 of the display area 111~11Ν to generate a residual image (Remnant Image); As shown. So short that the phase of the display area turn-on signal lags behind that of the video message, the image signal 124 of each display area is written too early, so that the Overlapping Image is now. The solution to the problem of heavy-edge image is to use the whole function in the flat display module. The phase adjustment is performed manually to achieve the phase adjustment. However, due to the consideration of cost and production time, it is not one-bit; J month fci is adjusted separately for the module 1 , but for the same batch of flat surface display surface display module 1 to be adjusted and set together, that is, the same as the flat 7 1373749 module 1 has the same Phase adjustment value, but there will still be some flat display. Module 1 is not suitable, so that it is necessary to recycle the unsuitable flat display module 1 and check them one by one for phase adjustment. As a result, the cost is greatly increased. It wastes time and reduces the reliability and performance of the flat display module 1. Therefore, how to provide a test system and test method for a flat display module can automatically adjust the phase of each flat display module to improve image display quality, thereby saving cost, improving product reliability and performance, and is currently an important issue. one. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a test system and a test method capable of automatically testing the signal phase of a flat display module and automatically optimizing the adjustment. Therefore, in order to achieve the above object, a test system for a flat display module according to the present invention comprises a test image generating circuit, an image sensing unit, a phase adjusting circuit and a timing control circuit. The test image generating circuit generates a test image, and the flat display module is driven by the clock signal to display the test image; the image sensing unit senses the test image displayed by the flat display module to generate a captured image; The phase adjustment circuit is electrically connected to the image sensing unit to receive the captured image, and records the image difference between the captured image and the test image, and the minimum image difference is obtained by changing the phase adjustment signal to obtain the smallest image difference. A good phase adjustment signal; the timing control circuit receives the phase adjustment signal and adjusts the phase of the clock signal according to the phase adjustment signal. 8 1373749 In order to achieve the above object, a test method for a flat display module according to the present invention comprises a test image generation program, a setting adjustment program, a phase adjustment program, an image sensing program, a difference recording program, and a re-execution setting. The adjustment program, the phase adjustment program, the image sensing program, and the difference recording program are used to obtain a plurality of image differences, and an optimization program. The test image generation program generates a test image to the flat display module; the set adjustment program generates a phase adjustment signal; the phase adjustment program adjusts the phase of the pulse signal according to the phase adjustment signal, wherein the flat display module is controlled by the pulse signal. The number is driven to display the test image; the image sensing program senses the test image displayed by the flat display module to generate a captured image; the difference recording program records the image difference between the captured image and the test image; The program determines the smallest difference from the image differences, and selects the phase adjustment signal corresponding to the smallest difference as an optimal value. According to the above, the test system and the test method of the flat display module according to the present invention compare the captured image detected by the image sensing unit with the original test image, and compare them according to the comparison. The result is automatically adjusted for the phase of the signal. Therefore, the recycling, manual re-inspection, and the like required by the conventional knowledge are eliminated, thereby reducing the cost and improving the reliability and performance of the product. [Embodiment] Hereinafter, a preferred embodiment of the present invention will be described with reference to the related drawings. Test system for flat display module and its test method. Referring to FIG. 3, a test system according to a preferred embodiment of the present invention includes phase adjustment timing control circuits 23, 21, a test image generation circuit 22, a 25, and an image (4). Correction circuit 24, - hybrid drive circuit and test image generation | 疋 26. The phase adjustment circuit 21 is electrically connected to the test image generation circuit 22 and the image sensing unit 26; the circuit 24 is electrically connected; the gamma 2 system is coupled to the time control circuit 23 and the gamma correction. The code correction circuit 24 and the source drive circuit 25 plane display module 3#&a register 32 and - horizontal shift temporary 3; display panel 3 - vertical shift register 32 and horizontal shift temporary: The device:: / 3 (10), wherein the vertical shift is temporarily on the same substrate, and is integrated into the display panel 31. In addition, the == modulo 1 of the embodiment has a plurality of display areas. ; machine =::: system -, display 4::: pole drive = transfer to the source MDS' and transfer the signal Ds to the plane display data shift register 33, timing control circuit ^ output = Horizontal CKH, XCKH * Start pulse signal coffee to flat mode pulse tfL horizontal shift material (four), horizontal shift (four) material 33 money ^ = 30 CKH 'XCKH and start pulse signal set ^ temple pulse number signal to let each Please refer to Figure 4 for the timing of the display area according to the data signal = area enable signal (10), take H, start pulse signal, and data clock display. US and 1373749 are shown in Figure 5, which is a flow chart of the drawing. The test step of the measurement system 2 firstly generates a test image TI in the test image generation path 22, and the test image generation image is generated by the test JJ circuit 24; ^i ^ 1 is first via gamma. 1 WW ^ correction is transmitted to the source source driving circuit 25 according to the test image TI generating circuit 5
面顯示模組3,以供平面顯示模組3顯示測千 另外，在測試影像產生程序開始前，^傳送一 啟動訊號L S至相位難電路2丨來啟動測試系二2 在設定調整程序P02中，相位調整電路^產生一相 位調整訊號PAS並傳送至—暫存器28，相位調整訊號⑽ 係-取樣保持的設定值，用來調整訊號的相位。暫存器Μ 係分別與相位調整電路2i及時序控制電路幻電性連接。 在相位調整程序P03巾，時序控制電路23依據自暫 存器28所得之相位調整訊號PAS來調整時脈訊號ckh、 XCKH及起始脈衝訊號STH之相位，其中相位調整方向可 如圖4所示’並傳送至平面顯示模組3。 在影像感測程序P04中’影像感測單元26咸測平面 顯示模組3所顯示之測試影像以產生一擷取影像CI。於 此’影像感測單元26可具有一電荷輕合元件（charge Coupled Device, CCD )或一互補金屬氧化導體元件 (Complementary Metal-Oxide Semiconductor, CMOS)等 等具有光電性質之元件。另外，影像感測單元26對測試 影像之感測方式係可一次定位並進行感測，亦可移動位置 1373749 並進行感測；並且影像感測單元26可對整個測試影像或 局部測試影像進行感測而產生擷取影像CI。The display module 3 is displayed for the flat display module 3 to display the measurement. In addition, before the test image generation program starts, a start signal LS is sent to the phase difficulty circuit 2 to start the test system 2 in the setting adjustment program P02. The phase adjustment circuit generates a phase adjustment signal PAS and transmits it to the buffer 28, and the phase adjustment signal (10) is a set value of the sample hold to adjust the phase of the signal. The register system is phantomically connected to the phase adjustment circuit 2i and the timing control circuit, respectively. In the phase adjustment program P03, the timing control circuit 23 adjusts the phases of the clock signals ckh, XCKH and the start pulse signal STH according to the phase adjustment signal PAS obtained from the register 28, wherein the phase adjustment direction can be as shown in FIG. 'And transferred to the flat display module 3. In the image sensing program P04, the image sensing unit 26 displays the test image displayed by the module 3 to generate a captured image CI. The image sensing unit 26 may have an element having photoelectric properties such as a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS). In addition, the image sensing unit 26 can sense and sense the test image once, and can also move the position 1373749 and perform sensing; and the image sensing unit 26 can sense the entire test image or the partial test image. The captured image CI is generated by the measurement.
接著’在差異記錄程序P05中，由於時脈訊號CKH、 XCKH及起始脈衝訊號STH已藉由相位調整訊號PAS而 調整相位’以致顯示區開啟訊,號與資料訊號DS之相位並 非同步；當然’就算時脈訊號CKH、XCKH及起始脈衝訊 號STH未受相位調整訊號PAS調整相位，顯示區開啟訊 號1與貧料訊號DS之相位亦會受到製程或線路長度等影響 而f非同步。因此’實際擷取到的顯示影像與應當顯示的 式衫像有所不同。相位調整電路21記錄擷取影像ci與 測试影像TI之—影像差異，影像差異係可記錄測試影像 及_取衫像CI之間的亮度差異、或色度差異等等，影 _ t異可儲存於與相位調整電路21電性連接之一記憶單 7L 27以供後續處理之用。 期性圖ίΓ:::種-周期性圖案，周 期性地與白之條紋係周 異。 來即可間早地檢測出影像的差 若資料訊號DS和 訊號STH及顯示區開啟虎CKH、XCKH、起始脈衝 影像係如目6(a)所示，同步1平面顯示模組3顯示的 CI的内容係如圖6(b)所=像$測單兀26產生的擷取影像 元26之水平位置，縱其中’検軸係代表影像感測單 色時’亮度強度係位於彻代表宂度強度值。當條紋為黑 • 1立，當條紋為白色時，亮度強 12 1373749 度係位於1¾準位。 若資料訊號DS和時脈訊號CKH、XCKH、起始脈衝 訊5虎STH及顯不區開啟訊號不同步，平面顯示模組3〇顯 示的影像係如圖7(a)所示，可能產生殘影或重疊等現象， 影像感測早元26產生的榻取影像CI的内容係如圖7(b)所 示’在黑與白條紋之間具有灰色條紋，在高準位及低準位 之間具有灰色條紋所對應之中間準位。如此一來，圖6(b) 及圖7(b)之間便有一些影像差異可供比較並記錄。 • 然後，再次執行設定調整程序P02、與相位調整程序 P〇3、影像感測程序P04、差異記錄程序P〇5數次，如此相 位凋整電路21便可逐次調整相位調整訊號pAS，藉由擷 取影像CI的回授而得到不同的影像差異，且這些影像差 異可儲存於記憶單元27中。 在最佳化程序P06中，相位調整電路21係從這些影 像差異中判斷出差異最小者，並選取差異最小考所對應之 %相位調整訊號PAS作為一最佳值。時序控制電路23係可 依據此最佳值來調整時脈訊號CKH、XCKH及起始脈衝訊 號STH之最佳相位。 最佳值係可於初始化時讀入至暫存器28中，以供時 序控制電路23於初始化時讀取，藉以調整時脈訊號CKH、 XCKH及起始脈衝訊號STH之最佳相位。 經由具有最佳調整相位之時脈訊號CKH、XCKH及起 始脈衝錢STH所產生之各顯示區開啟訊號係與資料訊 戒DS具有-致的相位’以致水平移位暫存器能夠正確 13 1373749 的依據各顯示區開訊號來取樣對應之資料訊號DS，使平 面顯示模組3之各顯示區能夠依序並正確的經由資料訊號 DS充電’而顯示出資料訊號DS所應具有的影像。 综上所述，在本實施例中，相位調整電路21係可逐 次調整相位調整訊號PAS ;晻序控制電路23係逐次依據 經調整之相位調整訊號PAS調整時脈訊號CKH、XCKH 及起始脈衝訊號STH之相位；平面顯示模組3係由經調整 之時脈訊號CKH、XCKH及起始脈衝訊號STH所驅動以 翁顯示測試影像TI ;影像感測單元26係逐次感測平面顯示 模組30所顯示之測試影像以產生不同内容之擷取影像 CI ;相位調整電路21係逐次記錄榻取影像CI與測試影像 TI之影像差異，並從這些影像差異中選擇差異最小者所對 應之相位調整訊號pAS作為一最佳值。 在此而注意者，本實施例之測試方法之流程步驟的順 序僅為舉例，並非限制本發明.例如，在測試方法一開始 籲時，測試影像產生電路程序p〇1之後，可先進行影像感測 程序P〇4及差異記錄程序p〇5，然後再執行設定調整程序 P02及相位調整程序p〇3以得到其他的影像差異。 另外’本實施例之最佳化程序除了可藉由判斷最小的 影像差異以得到純調整之最佳值之外，亦可藉由其他計 算方式，例如内插法或外插法以得到最佳值。 在本實施例令，相位調整電路21、測試影像產生 22、日=電路23、伽瑪校正電路24、源極驅動電路 25及矽感測早元26係以實現於一積體電路為例，並且 14 1373749 積體電路可作為平面顯示模組3之驅動積體電路（Driver 1C)。此外，可如圖8所示，將相位調整電路21實現於一 計算裝置21，，例如為一計算機程式（Computer program); 亦可將測試影像產生電路22實現於一啟動裝置22,，且啟 .動裝置22,除了傳送測試影像；ΓΙ至平面顯示模組3之外， 更啟動測試系統2作動。 此外，本實施例之測試系統及測試方法除了可用來得 到相位調整訊號PAS之最佳值之外，亦可應用於產品的統 馨计上’例如查看每一批出產之平面顯示模組之良率、或顯 示區開啟訊號與資料訊號之間的相位差分佈等等，以利缺 失改正並提高效能。 綜上所述’因依本發明之一種平面顯示模組之測試系 統及測試方法中，係將影像感測單元感測到的榻取影像來 和原始的測試影像進行比較，並依據比較的結果自動地進 行訊號的相位調整。因而免去習知所需要之回收、人工再 鲁—冬作進而降低成本，並提升產品之可靠度及效能。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範鳴，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1為一種習知之平面顯示模組之—示意圖； 圖2A及圖2B為-種習知之平面顯示模組所具有之各 顯示區開啟訊號與影像訊號具有不同相位之示意圖； 15 1373749 圖3為依據本發明較佳實施例之一種平面顯示模組之 測试系統之一示意圖； 圖4為依據本發明較佳實施例之一種平面顯示模組之 測試系統所具有之時脈訊號、各顯示區開啟訊號及資料訊 號之一示意圖； ° φ 圖5為依據本發明較佳實施例之一種平面顯示模袓之 測試方法之一流程圖； 、· 圖6為依據本發明較佳實施例之—種平面顯示模組之 分佈^統所顯示之測試影像於相位—致時所具有之亮度 圖7為依據本發明較佳實施例之一種 測續备从& β 卞面‘，，、員不模組之 度;佈圖ΓΓ測試影像於相位不一致時所具有之亮 測試系統之另一示意圖。 元件符號說明： 1、3 平面顯示模組 11 ' 31 顯示面板 111 〜11Ν 顯示區 12 特殊應用積體電路 121 、 122 時脈訊號 123 > STH 起始脈衝訊號 124 影像訊號 16 1373749Then, in the difference recording program P05, since the clock signals CKH, XCKH and the start pulse signal STH have been adjusted by the phase adjustment signal PAS, so that the display area is turned on, the phase of the signal and the data signal DS are not synchronized; Even if the clock signals CKH, XCKH and the start pulse signal STH are not phase-adjusted by the phase adjustment signal PAS, the phase of the display area turn-on signal 1 and the lean signal DS will also be affected by the process or line length and f. Therefore, the actual captured image is different from the one that should be displayed. The phase adjustment circuit 21 records the image difference between the captured image ci and the test image TI, and the image difference can record the brightness difference, or the chromaticity difference between the test image and the _taken image CI, and the like. The memory unit 7L 27 is electrically connected to the phase adjustment circuit 21 for subsequent processing. The periodicity diagram::: species-periodic pattern, periodically and white stripes are different. If the information signal DS and the signal STH and the display area are turned on, the CKH, XCKH, and the initial pulse image system are as shown in item 6(a), and the synchronous 1 plane display module 3 displays. The content of the CI is as shown in Fig. 6(b) = the horizontal position of the captured image element 26 generated by the measurement unit 26, and the vertical axis is the 'bright axis intensity representing the image sensing monochrome. Degree strength value. When the stripes are black • 1 vertical, when the stripes are white, the brightness is 12 1373749 degrees at the 13⁄4 level. If the data signal DS and the clock signal CKH, XCKH, the start pulse signal 5 tiger STH and the display area open signal are not synchronized, the image displayed by the flat display module 3〇 is as shown in Fig. 7(a), and may be disabled. Shadow or overlap, the content of the couch image CI generated by the image sensing early 26 is as shown in Figure 7(b) 'has gray stripes between the black and white stripes, at high level and low level. There is an intermediate level corresponding to the gray stripes. As a result, there are some image differences between Figure 6(b) and Figure 7(b) that can be compared and recorded. • Then, the setting adjustment program P02, the phase adjustment program P〇3, the image sensing program P04, and the difference recording program P〇5 are executed again several times, so that the phase trimming circuit 21 can sequentially adjust the phase adjustment signal pAS by Different image differences are obtained by capturing the feedback of the image CI, and these image differences can be stored in the memory unit 27. In the optimization program P06, the phase adjustment circuit 21 judges the smallest difference from among these image differences, and selects the % phase adjustment signal PAS corresponding to the difference minimum test as an optimum value. The timing control circuit 23 can adjust the optimum phase of the clock signals CKH, XCKH and the start pulse signal STH according to the optimum value. The optimum value can be read into the register 28 during initialization for the timing control circuit 23 to read during initialization to adjust the optimum phase of the clock signals CKH, XCKH and the start pulse signal STH. The display area of the display signal and the data signal DS generated by the clock signal CKH, XCKH and the initial pulse money STH having the best adjustment phase have the same phase 'so that the horizontal shift register can be correct 13 1373749 According to the display area of each display area, the corresponding data signal DS is sampled, so that each display area of the flat display module 3 can be accurately and sequentially charged via the data signal DS to display the image which the data signal DS should have. In summary, in the embodiment, the phase adjustment circuit 21 can adjust the phase adjustment signal PAS one by one; the dark sequence control circuit 23 sequentially adjusts the clock signals CKH, XCKH and the start pulse according to the adjusted phase adjustment signal PAS. The phase of the signal STH; the flat display module 3 is driven by the adjusted clock signals CKH, XCKH and the start pulse signal STH to display the test image TI; the image sensing unit 26 sequentially senses the flat display module 30. The displayed test image is used to generate the captured image CI of different content; the phase adjustment circuit 21 sequentially records the image difference between the couch image CI and the test image TI, and selects the phase adjustment signal corresponding to the smallest difference from the image differences. pAS is an optimal value. It should be noted here that the sequence of the flow steps of the test method of the present embodiment is merely an example and does not limit the present invention. For example, after the test method is initially called, after the image generation circuit program p〇1 is tested, the image may be first performed. The sensing program P〇4 and the difference recording program p〇5 are executed, and then the setting adjustment program P02 and the phase adjustment program p〇3 are executed to obtain other image differences. In addition, the optimization procedure of the present embodiment can be optimized by other calculation methods, such as interpolation or extrapolation, in addition to determining the smallest image difference to obtain the optimal value of the pure adjustment. value. In the embodiment, the phase adjustment circuit 21, the test image generation 22, the day=circuit 23, the gamma correction circuit 24, the source drive circuit 25, and the 矽-sensing early element 26 are implemented as an integrated circuit. And 14 1373749 integrated circuit can be used as the drive integrated circuit (Driver 1C) of the flat display module 3. In addition, as shown in FIG. 8, the phase adjustment circuit 21 can be implemented in a computing device 21, such as a computer program. The test image generation circuit 22 can also be implemented in a startup device 22, and The moving device 22, in addition to transmitting the test image; in addition to the flat display module 3, activates the test system 2 to operate. In addition, the test system and the test method of the present embodiment can be applied to the product of the product, in addition to the optimum value of the phase adjustment signal PAS, for example, the quality of the flat display module produced by each batch is obtained. Rate, or the display of the phase difference between the signal and the data signal in the display area, etc., in order to facilitate the lack of correction and improve performance. In summary, in the test system and the test method of the flat display module according to the present invention, the image taken by the image sensing unit is compared with the original test image, and the result is compared according to the comparison. The phase adjustment of the signal is performed automatically. Therefore, the recycling, manual re-lubrication and winter work required by the conventional method are eliminated, thereby reducing the cost and improving the reliability and performance of the product. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional flat display module; FIG. 2A and FIG. 2B are schematic diagrams showing a different phase of each display area open signal and image signal of a conventional flat display module. 15 1373749 FIG. 3 is a schematic diagram of a test system for a flat display module according to a preferred embodiment of the present invention; FIG. 4 is a timing of a test system for a flat display module according to a preferred embodiment of the present invention; FIG. 5 is a flow chart of a test method for a flat display module according to a preferred embodiment of the present invention; FIG. 6 is a flow chart of a test method for a flat display module according to a preferred embodiment of the present invention; The distribution of the test image displayed by the preferred embodiment of the flat display module is the brightness of the phase when the test image is displayed. FIG. 7 is a view of the test from the & beta face in accordance with a preferred embodiment of the present invention. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component symbol description: 1, 3 flat display module 11 ' 31 display panel 111 ~ 11 Ν display area 12 special application integrated circuit 121, 122 clock signal 123 > STH start pulse signal 124 image signal 16 1373749
13 基板 14、32 垂直移位暫存器 15、33 水平移位暫存器 2 測試系統 21 相位調整電路 ， 21， 計算裝置 22 測試影像產生電路 22' 啟動裝置 23 時序控制電路 24 伽瑪校正電路 25 源極驅動電路 26 影像感測單元 27 記憶單元 28 暫存器 Cl 擷取影像 CKH 時脈訊號 XCKH 時脈訊號 DS 資料訊號 LS 啟動訊號 PAS 相位調整訊號 TI 測試影像 P01-P06 測試方法之程序 1713 Substrate 14, 32 Vertical Shift Registers 15, 33 Horizontal Shift Register 2 Test System 21 Phase Adjustment Circuit, 21, Computing Device 22 Test Image Generation Circuit 22' Startup Device 23 Timing Control Circuit 24 Gamma Correction Circuit 25 Source Drive Circuit 26 Image Sensing Unit 27 Memory Unit 28 Register C Capture Image CKH Clock Signal XCKH Clock Signal DS Data Signal LS Start Signal PAS Phase Adjustment Signal TI Test Image P01-P06 Test Method Procedure 17