TWI702546B - Image test system and its image capture card - Google Patents

Abstract

A image testing device including a prober and an image capture card. The prober has a DUT load board; the image capture card is used to obtain a clock signal and a data signal of an image data, and comprises a data convert unit, a clock convert unit, a logic process unit and a fist delay unit. The first delay unit is used to regulate a timing of the clock signal, so that the timing of the clock signal can correspond to that of the data signal.

Description

Image testing system and image capture card

The invention relates to a test system and its interface card, in particular to an image test system and its image capture card.

The image capture card associated with the existing semiconductor device testing device usually has a logic processing unit that can pre-decode the image data, and then transmit the decoded image data to the back-end image processing device for processing. Under the specifications of some video transmission protocols, the clock signal and data signal of the video data often need to be transmitted through different signal traces, and the length of the signal traces may be inconsistent under different wiring methods of different test devices. It is possible that the clock signal received by the image capture card cannot correspond to the data signal, resulting in insufficient signal integrity during decoding.

In addition, the logic processing unit of the image capture card currently on the market has limitations on the operating frequency, and therefore the operating frequency of the image data input to the image capture card should not be too high, which also causes inconvenience and restrictions in use. .

In view of this, the present invention provides an improved image testing system and image capture card thereof to solve the above-mentioned problems.

An object of the present invention is to provide an image testing system, including: a needle tester and an image capture card. The probe tester includes a stage for placing the object to be tested; the image capture card is used to obtain image data of the object to be tested, wherein the image data includes the first clock signal and at least one data signal, and the image capture card includes data The conversion unit, the clock conversion unit, the logic processing unit and the first delay unit. The data conversion unit is used to obtain the data signal; the clock conversion unit is used to obtain the first clock signal; the logic processing unit is connected to the data conversion unit and the clock conversion unit to process the image data; the first delay unit is used to adjust the first clock signal The timing position of a clock signal causes the first clock signal to form a second clock signal, wherein the timing position of the second clock signal corresponds to the timing position of the data signal.

In an embodiment of the image testing system, the image capture card may further include a frequency divider unit for performing frequency down processing on the second clock signal so that the second clock signal forms a third clock signal. Further, the frequency divider unit can be integrated into the logic processing unit.

Further, the logic processing unit may be an electric field programmable logic gate array chip, and the system clock of the logic processing unit adopts the third clock signal.

In an embodiment of the image test system, the image capture card may further include a second delay unit, which is arranged between the data conversion unit and the logic processing unit to adjust the timing position of the data signal.

In an embodiment of the image testing system, the logic processing unit may further store timing correction information, and the first delay unit adjusts the timing position of the first clock signal according to the timing correction information.

In an embodiment of the image test system, the test system further includes a first adjustment chip and a second adjustment chip. The first adjustment chip is used to transmit the data signal of the image data to the data conversion unit. Yuan, the second adjusting chip is used to transmit the first clock signal of the image data to the clock conversion unit. Further, the first regulating chip and the second regulating chip can be arranged in the image capture card.

In an embodiment of the image test system, the test system further includes a customized adjustment chip for transmitting the data signal of the image data to the data conversion unit, and the first clock signal of the image data to the clock conversion unit . Furthermore, the customized adjustment chip can be set in the image capture card.

Another object of the present invention is to provide an image capture card for an image test system, including: a data conversion unit, a clock conversion unit, a logic processing unit, and a first delay unit. The data conversion unit is used to receive at least one data signal of the image data of the object to be tested; the clock conversion unit is used to receive the first clock signal of the image data; the logic processing unit is connected to the data conversion unit and the clock conversion unit to compare the image The data is processed; the first delay unit is used to adjust the timing position of the first clock signal so that the first clock signal forms a second clock signal, wherein the timing position of the second clock signal corresponds to the timing position of the data signal .

In an embodiment of the image capture card, it further includes a frequency dividing unit for performing frequency down processing on the second clock signal so that the second clock signal forms a third clock signal. Further, the frequency divider unit can be integrated into the logic processing unit.

Further, the logic processing unit may be an electric field programmable logic gate array chip, and the system clock of the logic processing unit adopts the third clock signal.

In an embodiment of the image capture card, it may further include a second delay unit, which is arranged between the data conversion unit and the logic processing unit to adjust the timing position of the data signal.

In an embodiment of the image capture card, the logic processing unit can further store timing correction information, and the first delay unit adjusts the timing position of the first clock signal according to the timing correction information.

In an embodiment of the image capture card, it may further include a first adjustment chip and a second adjustment chip. The first adjustment chip is used to transmit the data signal of the image data to the data conversion unit, and the second adjustment chip is used to transfer The first clock signal of the image data is transmitted to the clock conversion unit.

In an embodiment of the image capture card, it may further include a customized adjustment chip to transmit the data signal of the image data to the data conversion unit, and transmit the first clock signal of the image data to the clock conversion unit. Furthermore, the customized adjustment chip can be set in the image capture card.

1: Image test device

2: Test head

21: Test carrier board

221~228: Test card

3: Needle testing machine

31: Test interface panel

32: Probe card

33: Probe

34: Stage

4: Image capture card

41: adapter board

411: first end

412: second end

5: Spring pin tower

6a: Light source supply device

61a: light source controller

62a: Hollow pipe diameter

7: Object to be tested

8: Optical fiber cable or wireless transmission

9: Image processing unit

40: Clock conversion unit

42: The first delay unit

43: data conversion unit

44: Frequency division unit

45: logic processing unit

451: System Clock

452: Signal Decoder

Data, Data1~4, Data1’~4’: data signal

Clk: the first clock signal

Clk2: second clock signal

Clk3: third clock signal

92: The first adjustment chip

94: second regulating chip

96: Third adjustment chip

FIG. 1 is a schematic diagram of the basic structure of an image testing system and an image capture card according to an embodiment of the present invention; FIG. 2 is a detailed structure diagram of an image testing system according to an embodiment of the present invention; FIG. 3(A) is a first embodiment of the present invention Fig. 3(B) is a signal timing diagram of the first embodiment of the present invention; Fig. 3(C) is a schematic diagram of an improved structure of the image capture card of the first embodiment of the present invention; 4(A) is a schematic diagram of the structure of the image capture card of the second embodiment of the present invention; Fig. 4(B) is the signal timing diagram of the second embodiment of the present invention; Fig. 4(C) is the second embodiment of the present invention Schematic diagram of the improved structure of the image capture card.

Fig. 5 is a schematic diagram of the application of an image capture card according to an embodiment of the present invention; Fig. 6 is a schematic diagram of the application of an image capture card according to another embodiment of the present invention; Fig. 7 is a schematic diagram of the image capture card according to another embodiment of the present invention Application schematic diagram; FIG. 8 is an application schematic diagram of an image capture card according to another embodiment of the present invention

Hereinafter, the implementation mode and operation principle of the image testing system and image capture card of the present invention will be described through a number of embodiments. Those with ordinary knowledge in the technical field of the present invention can understand the features and effects of the present invention through the above-mentioned embodiments, and can make combinations, modifications, substitutions or transfers based on the spirit of the present invention.

The term "connected" referred to herein includes direct connection or indirect connection, and is not limiting. The terms "when..." and "...when" in this text mean "now, before or after", and are not limiting.

The ordinal numbers used herein, such as "first", "second", etc., are used to modify the request element, and it does not imply or represent any previous ordinal number of the request element, nor does it represent a request The order of the element and another request element, or the order in the manufacturing method, the use of these ordinal numbers is only used to clearly distinguish a request element with a certain name from another request element with the same name.

FIG. 1 is a schematic diagram of the basic structure of an image measurement system 1 and an image capture card 4 according to an embodiment of the present invention. As shown in FIG. 1, the image measuring system 1 includes a needle measuring machine 3 and an image capture card 4. The probe tester 3 can be used to contact an object 7 to be tested, where the object 7 to be tested can be a wafer or other objects that need to be electrically tested. The image capture card 4 can be used to obtain image data from the object under test 7. For example, if the object under test 7 is a lens device, the image capture card 4 can obtain the image data taken by the object under test 7, and The image data is converted into a data format applicable to an image processing component 9 (for example, an external computer) at the back end, and if the object under test 7 is the processing chip of the display, the image capture card 4 can obtain the image data being played on the display. And convert the image data into the data format applicable to the back-end image processing component 9 (such as the processor of the computer); in other words, the image capture card 4 can be regarded as the image data of the object 7 under test and a shadow The medium between the image processing components 9 is used to convert the data format of the image data and send it to the image processing unit 9 for processing. The above examples are only examples and not limitations. In one embodiment, the data transmission between the image capture card 4 and the image processing unit 9 can be carried out through an optical fiber cable or wireless transmission 8, but it is not limited. One of the characteristics of the present invention is that the image capture card 4 includes a first delay unit 42 for adjusting the clock signal of the image data.

In order to make the image measurement system 1 of the present invention clearer, an embodiment is described below, and it should be noted that this embodiment is not limited. 2 is a schematic diagram of the detailed structure of an image testing system according to an embodiment of the present invention. As shown in FIG. 2, the image measurement system 1 may include a test head 2, a needle tester 3, a plurality of image capture cards 4 and a plurality of adapter boards 41.

The test head 2 may include a test carrier 21 and a plurality of test cards 221 to 228 that can be inserted into the test carrier 21, where the test cards 221 to 228 may be various interface cards that provide necessary test procedures, such as electronic integrated cards ( PE card), device power supply card (DPS card), sequence test card (SEQ card), etc., but not limited to this. The probe tester 3 can include a test interface panel 31, a probe card 32 connected to the test interface panel 31, and a carrier 34. A plurality of probes 33 can be provided on the probe card 32, and the object 7 (for example, a wafer) to be tested can be placed on the carrier 34. The probe 33 can contact a pin of the object 7 to be tested, so that the test head 2 can perform an electrical test on the object 7 to be tested. In addition, the image testing device 1 is also provided with a light source supply device 6a. The light source supply device 6a can be a tube-diameter light source supply device and is arranged on the test head 2. In one embodiment, the light source supply device 6a uses a light source controller 61a to control the start time, and uses a long cylindrical hollow tube 62a to focus the light source on the object 7 (such as a wafer) to be tested. Test the actual receiving range of the image sensor in the object 7 under test for comprehensive image detection.

In one embodiment, a plurality of transfer boards 41 are arranged around the test carrier board 21, and each transfer board 41 can be inserted with multiple image capture cards 4 to construct a serial transfer structure. As shown, every An adapter board 41 can include a first end 411 and a second end 412. The first end 411 is directly inserted into the test carrier 21, and the second end 412 is directly inserted into the test interface panel. 31 on. It should be noted that the image capture card 4 can also be installed in other ways, and the present invention is not limited; since this part is not the focus of the present invention, it will not be described in detail here. .

In one embodiment, the image capture card 4 can be a mobile industry processor interface (Mobile Industry Processor Interface, MIPI) transmission interface card, which has the characteristics of high performance, low power consumption, and low electromagnetic interference, which can provide a large number of Image data processing capacity and transmission efficiency.

One of the features of the present invention is the improvement of the image capture card 4. FIG. 3(A) is a schematic diagram of the detailed structure of the image capture card 4 according to the first embodiment of the present invention. As shown in FIG. 3(A), the image capture card 4 may include a clock conversion unit 40, a first delay unit 42, a data conversion unit 43, a frequency divider unit 44, and a logic processing unit 45. The clock conversion unit 40 is used to obtain a first clock signal Clk of the image data, and can convert the data format of the first clock signal Clk into a data format suitable for the logic processing unit 45. The data conversion unit 43 is used to obtain at least one data signal Data of the image data, and can convert the at least one data signal Data into a data format suitable for the logic processing unit 45. The clock conversion unit 40 is connected to the first delay unit 42, wherein the first delay unit 42 is used to adjust the timing position of the first clock signal Clk so that the first clock signal Clk forms a second clock signal Clk2, and the The timing position of the two clock signal Clk2 corresponds to the timing position of at least one data signal Data; here, "adjusting the timing position" means that the signal is displaced on the time axis or the frequency axis. The frequency dividing unit 44 is connected to the first delay unit 42 to perform frequency down processing on the second clock signal Clk2, so that the second clock signal Clk2 forms a third clock signal Clk3, and the third clock signal Clk3 is The frequency is not greater than the maximum operating frequency that the logic processing unit 45 can load. In one embodiment, the data conversion unit 43 can be connected to the logic processing unit 45 to transmit at least one data signal Data to the logic processing unit 45. In one embodiment, the logic processing unit 45 further includes a system clock 451 And a signal decoder 452, wherein the signal decoder 452 can decode the received at least one data signal Data according to the frequency of the system clock 451 to convert the at least one data signal Data into a data format applicable to the image processing unit 9 In other words, the signal decoder 452 uses the system clock 451 as its operating frequency.

In one embodiment, the clock conversion unit 40, the first delay unit 42, the data conversion unit 43, and the frequency divider unit 44 can realize their functions through circuits, chips, etc., it should be noted that the present invention is not limited in time. The circuit structures of the pulse conversion unit 40, the first delay unit 42, the data conversion unit 43, and the frequency divider unit 44 are within the scope of the present invention as long as they can realize the functions described in this text. In one embodiment, the logic processing unit 45 may be a field programmable gate array (FPGA) chip, the image data may adopt the data format of the MIPI D-PHY protocol, and the image capture card 4 may be MIPI For the convenience of description, the image capture card is taken as an example below, but the present invention is not limited to this.

It should be noted that under the MIPI D-PHY protocol architecture, image data is usually divided into one clock signal (such as the first clock signal Clk) and four data signals Data (note that when using different According to the protocol, the image data may have different numbers of data signals), and are transmitted to the image capture card 4 through different signal routing paths. Therefore, the data conversion unit 43 usually receives four data signals. However, because the layout of each test system 1 is not necessarily the same, and the length of the signal routing path is not necessarily the same, so the first clock signal Clk received by the image capture card 4 and the data The timing of the signal Data may be inconsistent, which will cause problems when the logic processing unit 45 performs signal decoding. The first delay unit 42 of the present invention can solve this problem. The first delay unit 42 can adjust the timing position of the clock signal Clk so that the clock signal Clk corresponds to the timing position of the data signals Data; it should be noted that, In this embodiment, “the timing of the clock signal Clk corresponding to the data signals Data” can be defined as the high-potential period of the clock signal Clk and the high-potential period of each data signal Data substantially overlap or completely overlap.

Fig. 3(B) is a signal timing diagram of the first embodiment of Fig. 3(A), in which the left half of Fig. 3(B) is the signal timing of the first clock signal Clk and a plurality of data signals Data1~Data4. The right half shows the signal timing of the clock signal (the second clock signal Clk2) and the plurality of data signals Data1 to Data4 after adjusting the timing position of the first delay unit 42. As shown in the left half of Figure 3(B), when the timing position is not adjusted, although the timing positions of the first clock signal Clk and part of the data signals Data1 and Data4 can completely or roughly correspond (that is, the high potential period of both In fact, it can be completely overlapped), but the timing positions of the first clock signal Clk and the remaining data signals Data2 and Data3 cannot correspond (also the overlap of the high-potential period of the real-time pulse signal Clk and the high-potential periods of the data signals Data2 and Data3) If the period is too short, the signal integrity may be affected, and the logic processing unit 45 may cause problems in signal decoding, such as signal skew. As shown in the right half of Figure 3(B), After adjusting the timing of the clock signal Clk through the first delay unit 42, the high-potential period of the clock signal Clk and the high-potential periods of all the data signals Data1 to Data4 are substantially overlapped or completely overlapped, and therefore the logic processing unit 45 is performing A certain degree of signal integrity can still be maintained when the signal is decoded. With this, problems such as signal distortion can be solved.

In addition, another feature of the present invention is that the frequency dividing unit 44 is provided, and the system clock 451 of the logic processing unit 45 is a clock signal after frequency down processing (the third clock signal Clk3). Thereby, even if the clock frequency of the image data obtained by the image capture card 4 is higher than the working frequency that the logic processing unit 45 can load, the frequency dividing unit 44 can still reduce the clock frequency of the image data to the load. Working frequency. As a result, the image capture card 4 of the present invention can be adapted to the operating frequencies of various MIPI D-PHY specifications, such as 1.5Gbps, 2.5Gbps, 4.5Gbps, etc. In contrast, the image capture cards currently on the market are only The frequency specification of 1.5Gbps can be applied.

In addition, the first embodiment can also have various improvements. FIG. 3(C) is a schematic diagram of an improved structure of the image capture card 4 according to the first embodiment of the present invention. As shown in Figure 3(C), the frequency divider 44 is integrated in the logic Among the logical processing unit 45, that is, the logic processing unit 45 itself can have a built-in function of the frequency removing unit 44. In one embodiment, the frequency dividing unit 44 in the logic processing unit 45 can be a computer program product, which enables the logic processing unit 45 to perform signal down-frequency processing, but it is not limited. Under this improved structure, the second clock signal Clk2 after adjusting the timing position by the first delay unit 42 is directly input to the logic processing unit 45, and the frequency reduction processing is performed in the logic processing unit 45 to form the third timing. The third clock signal Clk3 can be used as the system clock 451 of the logic processing unit 45. The present invention can also have different implementation aspects. FIG. 4(A) is a schematic diagram showing the detailed structure of the image capture card 4 according to the second embodiment of the present invention. 4(A), the image capture card 4 may include a clock conversion unit 40, a first delay unit 42, a data conversion unit 43, a frequency division unit 44, a logic processing unit 45, and a second The delay unit 46, in which the clock conversion unit 40, the first delay unit 42, the data conversion unit 43, the frequency divider unit 44 and the logic processing unit 45 can be applied to the content of the first embodiment, and therefore will not be described in detail. The second delay unit 46 is connected to the data conversion unit 43 to adjust the timing position of the data signal Data obtained by the data conversion unit 43. In other words, compared to the first embodiment, only the clock signal Clk will adjust the timing position In the second embodiment, both the clock signal Clk and the data signal Data will adjust the timing position. In addition, in an embodiment, the second delay unit 46 can realize its function through a circuit, a chip, or the like.

Fig. 4(B) is a signal timing diagram of the second embodiment of Fig. 4(A), in which the left half of Fig. 4(B) is the signal timing of the first clock signal Clk and a plurality of data signals Data1~Data4, The right half shows the signal timing of the clock signal adjusted by the first delay unit 42 (the second clock signal Clk2) and the data signal Data1'~Data4' adjusted by the second delay unit 46. As shown in the left half of Figure 4(B), although the timing positions of the first clock signal Clk and some of the data signals Data1 and Data4 can completely or roughly correspond to each other, the first clock signal Clk and the remaining data signals Data2 and Data3 The timing position cannot be corresponding, and this may cause problems when the logic processing unit 45 performs signal decoding. As shown in the right half of Figure 4(B), the After the delay unit 42 adjusts the timing position of the first clock signal Clk and adjusts the timing positions of the data signals Data1~Data4 through the second delay unit 46, the high potential period of the second clock signal Clk2 and all the data signals Data1'~Data4' The high potential period completely or roughly corresponds. In this way, problems such as signal distortion can be solved.

As shown in Figure 4(B), due to the second delay unit 46, the timing positions of the data signals Data1~Data4 can also be adjusted, so the timing positions of the second clock signal Clk2 and the data signals Data1'~Data4' can be accurate Corresponding to the ground, thereby enhancing the signal integrity during signal decoding.

Please refer to Figure 4(A) and 4(B) again. The first delay unit 42 and the second delay unit 46 can make the timing positions of the clock signal Clk and the data signals Data1 to Data4 consistent through various achievable methods. For example, the image capture card 4 may further include a storage unit 47 for storing a clock correction data, and the first delay unit 42 and the second delay unit 46 can adjust the clock signal Clk and the clock signal according to the clock correction data. The timing position of data signal Data1~Data4. In one embodiment, the storage unit 47 may pre-store a test image data (such as a test picture), and before receiving the actual image data, the image data source may send the test picture to the image capture through the signal traces. The card 4 is retrieved, and the image capture card 4 can compare the received test picture with the test picture stored in the storage unit 47 to generate timing correction information. In one embodiment, the first delay unit 42 in the first embodiment can also obtain timing correction information by the above-mentioned method, and adjust the timing position of the clock signal Clk according to the timing correction information. It should be noted that the present invention can also perform timing position correction in other ways.

In addition, the second embodiment can also have different improvements. 4(C) is a schematic diagram of an improved structure of the image capture card 4 according to the second embodiment of the present invention. As shown in FIG. 4(C), the frequency divider unit 44 is integrated into the logic processing unit 45, that is, the logic processing unit 45 itself can build in the function of the frequency divider unit 44. In one embodiment, the frequency dividing unit 44 in the logic processing unit 45 may be a computer program product, so that the logic processing unit Element 45 performs signal down-frequency processing, but it is not limited. Under this improved structure, the second clock signal Clk2 after adjusting the timing position by the first delay unit 42 is directly input to the logic processing unit 45, and the frequency reduction processing is performed in the logic processing unit 45 to form the third timing. The third clock signal Clk3 can be used as the system clock 451 of the logic processing unit 45.

In addition, with the architecture of the first and second embodiments described above (that is, the first delay unit 42 performs timing adjustment of the clock signal Clk and the frequency dividing unit 44 performs frequency down processing on the second clock signal Clk2), Any transmission interface can be used between the image data and the image capture card 4. Figures 5 and 6 are respectively schematic diagrams of the application of image capture cards according to different embodiments of the present invention. It should be noted that although Figures 5 and 6 are examples with the image capture card 4 of Figure 3(A), they are actually The above FIGS. 5 and 6 can also be implemented with the image capture card 4 of FIG. 3(C), FIG. 4(A) or FIG. 4(C), and are not limited. As shown in FIG. 5, a signal conditioning chip can be used for data transmission between the image data and the image capture card 4, and the data signal Data of the image data can be combined with a first adjustment chip 92 to be transmitted to the data conversion unit 43. The clock signal Clk of the image data can be combined with the second adjusting chip 94 to be transmitted to the clock conversion unit 40, but it is not limited. In one embodiment, the first adjusting chip 92 and the second adjusting chip 94 may be, for example, a buffer integrated circuit chip (buffer IC), which is used to buffer or amplify the signal, thereby achieving signal delay or increasing signal strength. The effect. In an embodiment, the first regulating chip 92 and the second regulating chip 94 may also be, for example, a transceiver chip (transceiver chip) for maintaining or buffering signals. In an embodiment, the first regulating chip 92 and the second regulating chip 94 may also be other various regulating chips. In addition, the first conditioning wafer 92 and the second conditioning wafer 94 may be different wafers. As shown in FIG. 6, a third adjusting chip 96 can also be used for data transmission between the image data and the image capture card 4, wherein the data signal Data and the clock signal Clk can be matched with the same third adjusting chip 96 for transmission. The data conversion unit 43 and the clock conversion unit 40 are not limited. In one embodiment, the third adjustment chip 96 may be a customized adjustment chip, such as a special application integrated circuit The (application specific integrated circuit, ASIC) chip is used to customize the signal according to different product requirements; however, the third adjustment chip 96 can also be other various adjustment chips. According to the embodiments of FIG. 5 and FIG. 6, no matter what transmission protocol is used for the input signal, the first delay unit 42 and the frequency divider unit 44 can adjust the signal to be suitable for the logic processing unit 45. Thereby, the image capture card 4 of the present invention has a wide range of adaptability, and can be applied to signals of various transmission protocols.

In addition, the structure of FIG. 5 can also be adjusted. FIG. 7 is a schematic diagram of the application of the image capture card 4 according to another embodiment of the present invention, which is modified from the structure of FIG. 5. The embodiment in FIG. 7 is similar to the embodiment in FIG. 5, and the difference between the two is that the first regulating chip 92 and the second regulating chip 94 in the embodiment in FIG. 7 are arranged in the image capture card 4. Therefore, when the MIPI signal is transmitted to the image capture card 4, the first adjusting chip 92 adjusts the data part of the MIPI signal and transmits the adjusted data signal to the data conversion unit 43; in addition, when the MIPI signal is transmitted to After the image capture card 4 is captured, the second adjusting chip 94 adjusts the clock part of the MIPI signal, and transmits the adjusted clock signal to the clock conversion unit 40.

In addition, the structure of FIG. 6 can also be adjusted. FIG. 8 is a schematic diagram of the application of the image capture card 4 according to another embodiment of the present invention, which is modified from the structure of FIG. 6. The embodiment in FIG. 8 is similar to the embodiment in FIG. 6, and the difference between the two is that the third adjusting chip 96 in the embodiment in FIG. 8 is disposed in the image capture card 4. Therefore, after the MIPI signal is transmitted to the image capture card 4, the third adjusting chip 96 adjusts the data part and the clock part of the MIPI signal, and transmits the adjusted data signal to the data conversion unit 43 and transfers the adjusted data signal to the data conversion unit 43. The clock signal is sent to the clock conversion unit 40.

In this way, the image capture card of the present invention can solve the problems of signal distortion caused by different signal routing path lengths, and can be applied to image signals of various operating frequencies, which can greatly solve the shortcomings of the prior art.

The above-mentioned embodiments are merely examples for the convenience of description, and the scope of rights claimed in the present invention should be subject to the scope of the patent application, rather than limited to the above-mentioned embodiments.

1: Image test system

4: Image capture card

40: Clock conversion unit

42: The first delay unit

43: data conversion unit

44: Frequency division unit

45: logic processing unit

451: System Clock

452: Signal Decoder

8: Optical fiber cable or wireless transmission

9: Image processing unit

Data: data signal

Clk: the first clock signal

Clk2: second clock signal

Clk3: third clock signal

Claims (16)

An image testing system includes: a needle tester, including a stage, for placing an object to be tested; and an image capture card for obtaining an image data of the object to be tested, wherein the image data includes a A first clock signal and at least one data signal, and the image capture card includes: a data conversion unit for obtaining the data signal; a clock conversion unit for obtaining the first clock signal; and a logic processing unit , Connected with the data conversion unit and the clock conversion unit to process the image data; and a first delay unit for adjusting the timing position of the first clock signal so that the first clock signal is formed A second clock signal, wherein the timing position of the second clock signal corresponds to the timing position of the data signal; wherein the image capture card further includes a frequency divider unit for performing the second clock signal Frequency reduction processing, so that the second clock signal forms a third clock signal. The test system according to claim 1, wherein the logic processing unit is an electric field programmable gate array (FPGA) chip, and a system clock of the logic processing unit uses the third time Pulse signal. The test system according to claim 1, wherein the image capture card further includes a second delay unit disposed between the data conversion unit and the logic processing unit to adjust the timing position of the data signal. The test system according to claim 1, wherein the logic processing unit is further used to store timing correction information, and the first delay unit adjusts the timing position of the first clock signal according to the timing correction information. The test system according to claim 1, which further comprises a first adjusting chip and a second adjusting chip, the first adjusting chip is used for transmitting the data signal of the image data to the data conversion unit, and the second adjusting chip The adjusting chip is used for transmitting the first clock signal of the image data to the clock conversion unit. The test system according to claim 5, wherein the first adjusting chip and the second adjusting chip are set in the image capture card. The test system according to claim 1, which further includes a customized adjustment chip for transmitting the data signal of the image data to the data conversion unit, and transmitting the first clock signal of the image data To the clock conversion unit. The test system according to claim 7, wherein the customized adjustment chip is set in the image capture card. The test system according to claim 1, wherein the image capture card further includes a frequency dividing unit for performing frequency down processing on the second clock signal, so that the second clock signal forms a third time Pulse signal, and the frequency divider unit is integrated in the logic processing unit. An image capture card used in an image test system, and includes: a data conversion unit for obtaining at least one data signal of an image data of an object to be tested; a clock conversion unit for obtaining the image data A first clock signal; a logic processing unit connected to the data conversion unit and the clock conversion unit to process the image data; and A first delay unit for adjusting the timing position of the first clock signal so that the first clock signal forms a second clock signal, wherein the timing position of the second clock signal and the timing of the data signal Corresponding to the positions; which further includes a frequency dividing unit for performing frequency down processing on the second clock signal, so that the second clock signal forms a third clock signal. The image capture card according to claim 10, wherein the logic processing unit is an electric field programmable logic gate array chip, and a system clock of the logic processing unit uses the third clock signal. The image capture card according to claim 10, which further includes a second delay unit disposed between the data conversion unit and the logic processing unit to adjust the timing position of the data signal. The image capture card according to claim 10, wherein the logic processing unit is further used to store timing correction information, and the first delay unit adjusts the timing position of the first clock signal according to the timing correction information . The image capture card according to claim 10, further comprising a first adjusting chip and a second adjusting chip, the first adjusting chip is used to transmit the data signal of the image data to the data conversion unit, the The second adjusting chip is used for transmitting the first clock signal of the image data to the clock conversion unit. The image capture card according to claim 10, which further includes a customized adjustment chip for transmitting the data signal of the image data to the data conversion unit, and transmitting the first clock of the image data The signal is transmitted to the clock conversion unit. The image capture card according to claim 11, further comprising a frequency dividing unit for performing frequency down processing on the second clock signal, so that the second clock signal forms a third clock signal, And the frequency dividing unit is integrated in the logic processing unit.

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