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TWI370541B - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
TWI370541B
TWI370541B TW097122545A TW97122545A TWI370541B TW I370541 B TWI370541 B TW I370541B TW 097122545 A TW097122545 A TW 097122545A TW 97122545 A TW97122545 A TW 97122545A TW I370541 B TWI370541 B TW I370541B
Authority
TW
Taiwan
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Application number
TW097122545A
Other languages
English (en)
Other versions
TW200915542A (en
Inventor
Yoshiko Kato
Mitsuhiro Noguchi
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW200915542A publication Critical patent/TW200915542A/zh
Application granted granted Critical
Publication of TWI370541B publication Critical patent/TWI370541B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B63/00Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/482Bit lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/488Word lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW097122545A 2007-07-02 2008-06-17 Semiconductor memory TWI370541B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007174280A JP2009016444A (ja) 2007-07-02 2007-07-02 半導体メモリ

Publications (2)

Publication Number Publication Date
TW200915542A TW200915542A (en) 2009-04-01
TWI370541B true TWI370541B (en) 2012-08-11

Family

ID=40221286

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097122545A TWI370541B (en) 2007-07-02 2008-06-17 Semiconductor memory

Country Status (4)

Country Link
US (2) US7826245B2 (zh)
JP (1) JP2009016444A (zh)
KR (1) KR101022101B1 (zh)
TW (1) TWI370541B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009016444A (ja) * 2007-07-02 2009-01-22 Toshiba Corp 半導体メモリ
KR101435520B1 (ko) * 2008-08-11 2014-09-01 삼성전자주식회사 반도체 소자 및 반도체 소자의 패턴 형성 방법
KR101540083B1 (ko) 2008-10-22 2015-07-30 삼성전자주식회사 반도체 소자의 패턴 형성 방법
JP5720101B2 (ja) * 2010-03-08 2015-05-20 セイコーエプソン株式会社 記憶装置、集積回路装置及び電子機器
JP5395837B2 (ja) * 2011-03-24 2014-01-22 株式会社東芝 半導体装置の製造方法
US20150121156A1 (en) * 2013-10-28 2015-04-30 Sandisk Technologies Inc. Block Structure Profiling in Three Dimensional Memory
JP6137364B2 (ja) * 2016-02-29 2017-05-31 セイコーエプソン株式会社 記憶装置、集積回路装置及び電子機器
KR102471722B1 (ko) 2018-01-03 2022-11-29 삼성전자주식회사 반도체 메모리 장치
JP2021150511A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 半導体記憶装置
TWI785992B (zh) * 2022-02-23 2022-12-01 華邦電子股份有限公司 半導體結構及其製造方法
KR20230164473A (ko) * 2022-05-25 2023-12-04 삼성전자주식회사 반도체 장치

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JP3050965B2 (ja) 1991-09-27 2000-06-12 沖電気工業株式会社 レジストパタンの形成方法
JPH06318680A (ja) * 1993-05-10 1994-11-15 Nec Corp 半導体記憶装置およびその製造方法
JP3745392B2 (ja) * 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
JPH0855920A (ja) 1994-08-15 1996-02-27 Toshiba Corp 半導体装置の製造方法
KR0155886B1 (ko) * 1995-09-19 1998-10-15 김광호 고집적 dram 셀의 제조방법
JPH10242147A (ja) 1997-02-27 1998-09-11 Toshiba Corp 半導体装置およびその製造方法ならびに半導体記憶装置およびその製造方法
KR100265770B1 (ko) * 1998-06-12 2000-09-15 윤종용 워드라인 보다 짧은 비트라인을 갖는 에스램 셀
JP3317279B2 (ja) 1998-08-17 2002-08-26 セイコーエプソン株式会社 半導体装置の製造方法
JP3175705B2 (ja) * 1998-09-18 2001-06-11 日本電気株式会社 不揮発性半導体記憶装置の製造方法
JP2000307084A (ja) * 1999-04-23 2000-11-02 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6348374B1 (en) * 2000-06-19 2002-02-19 International Business Machines Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
JP2002118177A (ja) * 2000-10-11 2002-04-19 Toshiba Corp 半導体装置及びその製造方法
JP2002184875A (ja) 2000-12-11 2002-06-28 Seiko Epson Corp 不揮発性メモリトランジスタを有する半導体装置およびその製造方法
KR100396891B1 (ko) * 2001-03-21 2003-09-03 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
KR20030044341A (ko) * 2001-11-29 2003-06-09 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100456688B1 (ko) * 2002-01-07 2004-11-10 삼성전자주식회사 완전 씨모스 에스램 셀
US6870213B2 (en) 2002-05-10 2005-03-22 International Business Machines Corporation EEPROM device with substrate hot-electron injector for low-power
KR100454131B1 (ko) * 2002-06-05 2004-10-26 삼성전자주식회사 라인형 패턴을 갖는 반도체 소자 및 그 레이아웃 방법
JP4498088B2 (ja) * 2004-10-07 2010-07-07 株式会社東芝 半導体記憶装置およびその製造方法
US7352618B2 (en) * 2004-12-15 2008-04-01 Samsung Electronics Co., Ltd. Multi-level cell memory device and associated read method
US7521351B2 (en) * 2005-06-30 2009-04-21 Infineon Technologies Ag Method for forming a semiconductor product and semiconductor product
US7352018B2 (en) * 2005-07-22 2008-04-01 Infineon Technologies Ag Non-volatile memory cells and methods for fabricating non-volatile memory cells
JP2007194496A (ja) * 2006-01-20 2007-08-02 Toshiba Corp 半導体集積回路
JP4364226B2 (ja) * 2006-09-21 2009-11-11 株式会社東芝 半導体集積回路
JP2009016444A (ja) * 2007-07-02 2009-01-22 Toshiba Corp 半導体メモリ

Also Published As

Publication number Publication date
US7957174B2 (en) 2011-06-07
US7826245B2 (en) 2010-11-02
JP2009016444A (ja) 2009-01-22
US20110019469A1 (en) 2011-01-27
KR20090004640A (ko) 2009-01-12
KR101022101B1 (ko) 2011-03-17
TW200915542A (en) 2009-04-01
US20090010036A1 (en) 2009-01-08

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees