100^.08^ 18 0 、採用該焊接基板之電子封 1364825 六、發明說明： 【發明所屬之技術領域】· [0001] 本發明係關於一種焊接基板 裝構造及其封裝方法。 【先前技術】 [0002]隨著電子科學技術之發展，電子封裝技術正在曰新月異 地進步中。以應高散熱、高傳導速率之電訊需求，各式 電子封裝技術皆已被廣泛應用至半導體器件與薄膜電晶 體基板之封裝、半導體器件與印刷電路板之封裝以及軟 性印刷電路板與硬性印刷電路板之封裝等各種領域中。 _3]通常在各式電子封裝製程中，主要的電子封裝技術包括 .球柵矩陣式封裝（Ball Grid Array Package，BGA Package)技術、覆晶封裝（Filp-Chip Bonding)技術 日日片尺寸封裝（Chip Scale Package, CSP)技術以 及曰日片直貼封裝（Direct Chip Attachment Pack-age, DAC Package)等。 [0004]然而採用上述封裝技術封裝半導㈣件於薄膜電晶體基 板印刷電路板等焊接基板表面時，還存在如下技術瓶 頸： [0005]首先因為上述半導體器件之封裝皆是以焊錫凸塊焊接 方式實現連結’但是焊球之高度太低，不足以承受回谭 (Refl〇w)製程所產生之熱應力，故易因熱力衝擊影響電 子封裝之可靠度； [麵]其:欠，隨著半導體ϋ件及焊接基板表面線路集成度之提 096149369 表單編銳Α0101 第3頁/共20頁 1003302042-0 1364825100^.08^ 18 0. Electronic seal using the solder substrate 1364825 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a solder substrate mounting structure and a packaging method therefor. [Prior Art] [0002] With the development of electronic science and technology, electronic packaging technology is undergoing rapid progress. Various electronic packaging technologies have been widely applied to packaging of semiconductor devices and thin film transistor substrates, packaging of semiconductor devices and printed circuit boards, and flexible printed circuit boards and rigid printed circuits, in order to meet the demand for high heat dissipation and high conduction rate. Board packaging and other fields. _3] Generally, in various electronic packaging processes, the main electronic packaging technologies include: Ball Grid Array Package (BGA Package) technology, and Flip-Chip Bonding technology. Chip Scale Package, CSP) technology and Direct Chip Attachment Pack-age (DAC Package). [0004] However, when the above-mentioned package technology is used to package a semiconductor device on a surface of a solder substrate such as a printed circuit board such as a thin film transistor substrate, the following technical bottlenecks exist: [0005] First, the package of the semiconductor device is soldered by solder bumps. The way to achieve the connection 'but the height of the solder ball is too low, not enough to withstand the thermal stress generated by the Refl〇w process, so it is easy to affect the reliability of the electronic package due to thermal shock; [face] its: owe, with Semiconductor device and soldering substrate surface line integration 096149369 Form editing sharp Α 0101 Page 3 / Total 20 pages 1003302042-0 1364825
[0007] [0008] [0009] 高，球_矩陣時，錫球間距亦進一步縮小，以致達到 0. 5mm，甚至更尔，如:秘勢•必會因為焊球之偏移導動^ ，影響電子封裝之可靠度》 為解決以上技術瓶頸，業界有採用異方性導電膜 (Anisotropic Conductive Film，ACF)直接黏接固 定待焊接之半導體器件於焊接基板之方法，或者於焊接 基板表面設置多層佈線（Lay out)以及扇出（Fanout)來 改變設置佈局’達到設置於半導體器件表面之焊墊與焊 接基板之連結目的。 一種先前技術所示之將半導體晶粒固定於焊接基板之電 子封裝構造如圖1所示《該電子封裝構造1包括一半導體 晶粒11、一異方性導電膜13及一薄膜電晶體基板15。該 薄膜電晶體基板15係一表面設置有一焊接區域ι51之焊接 基板，該半導體晶粒11藉由該異方性導電膜丨3黏接固定 於这悍接區域151 該半導體晶粒1 1表面設置有一焊塾1 Η矩陣。該薄膜電晶 體15之焊接區域151内設置有一焊接點152矩陣及複數位 於該焊接區域151外之扇出導線153。其中部份扇出導線 153與該焊接點152對應電連接，且該扇出導線153之截 面高度與該焊接點丨52之截面高度一致，其截面結構如圖 2所示。 該異方性導電膜13係一摻雜有一定密度導電顆粒之樹脂 ，其使得該焊墊111與該焊接點152於平行於膜厚方向導 通’而於垂直於膜厚方向彼此絕緣。 096149369 表單編號A0101 第4頁/共20頁 1003302042-0 [0010] [0011] [0011] 1364825 丨100 年· 當將該半導體晶粒11封裝於該薄膜電晶體基板i 5時，其 4驟如下： [0012]首先於該薄膜電晶體基板15之焊接區域151内塗佈一層異 方性導電膜13 ;然後，對位該半導體晶粒u之焊墊lu矩 陣與該薄膜電晶體15之焊接點152矩陣；最後，採用熱壓 設備熱壓固化該異方性導電膜13 ’藉由該異方性導電膜 13黏接固定該半導體晶粒11至該薄膜電晶體基板15之焊 接區域151，並使得該焊墊112矩陣與該焊接點152矩陣 對應電連接。 [0013] 惟，因為該薄膜電晶體基板15表面之扇出導線153與該焊 接點152於尚度方向上一致，故當對位該焊墊U1矩陣與 該焊接點152矩陣時，如操作失誤或者對位精度不夠，則 易導致該焊墊111與該扇出導線153在空間上之重疊而短 路；當採用4膜電晶體基板15作為焊接基板進行封裝製 程時，往往會因扇出導線丨53與焊墊U1之短路導致封裝 不良，降低封裝可靠度。 【發明内容】 [0014] 有鑑於此，有必要提供-種封裝可靠度高之焊接基板。 [〇〇15]有鑑於此，亦有必要提供一種封裝可靠度高之電子封裝 構造。 _6]有舰此，還有必要提供—種封裝可靠度高之電子封裝 方法。 種焊接基板，其包括錢扇出導線及複數焊接點，其 中至少-扇出導線電連接該焊接點，且該焊接點之高度 > 士《 表單編號A0101 第5頁/共20苜 ' 1003302042-0 1364825 大於該扇出導線之高度。 [0018] 一種電子封襄構造，其包括一半導禮晶粒及〜 焊接基板 ，該半導體晶粒包括複數焊墊，該焊接基板包括複數扇 出導線及複數焊接點，其中該半導體晶粒之複數焊墊與 該複數焊接點對應電連接，至少一扇出導線電連接該焊 接點，且該焊接點之高度大於該扇出導線之高度。 [0019] -種電子封裝方法’其包括於—半導體晶粒表面形成複 數焊墊；於一焊接基板表面形成複數焊接點及複數與該 焊接點電連接之扇出導線，其中該焊接點之高度大於該 扇出導線之高度；以及使該半導體晶粒之焊墊分別與該 焊接基板之焊接點對應電連接。 [0020] [0021] 相較於先前技術，於該焊接基板表面設置該焊接點之高 度大於该扇出導線之高度，藉由該高度差，避免該半導 體晶粒之焊墊與該焊接基板之焊接點間因短路導致封裝 不良，有效提高採用該焊接基板之電子封裝構造之可靠 度β 相較於先前技術’於該電子封裝方法中，設置該焊接基 板表面之焊接點之高度大於該扇出導線之高度，使得當 需要將該半導體晶粒封裝於該焊接基板時，保證該半導 體晶粒之焊塾與該焊接基板表面之焊接點相互絕緣。即 便是操作失誤或者對位精度不夠高導致該焊墊與該扇出 導線於空間上部份重疊，同樣避免其相互短路導致電子 封裝不良，提高其封裝可靠度。 【實施方式】 096149369 表單編號Α0101 第6頁/共20頁 1003302042-0 1364825 ... 广 '… .· 100年08月18日俊正替_頁 [0022] .請參閱圖3，係本發明電子封裝構造一種較佳實施方式之 丘體組濃π惠圖.。該電子封袁構造2包括—半導體晶粒22 、一焊接基板23及一異方性導電膜25。該半導體晶粒22 . 藉由該異方性導電膜25黏接固定於該焊接基板23。 [0023] 再請參閱圖4，係圖3所示電子封裝構造2之半導體晶粒22 之平面示意圖。該半導體晶粒22係一半導體裝置，其表 面設置有一焊墊矩陣221，該焊墊矩陣221係由複數焊墊 222成矩陣排列形成。 • [0024]請參間圖5 ’係圖3所示電子封裝構造2之焊接基板23之立 體示意圖。該焊接基板23係一薄膜電晶體基板，其表面 設置有複數佈線電路（未標示）及一接腳焊墊區231，該佈 線電路包括複數控制導線235及複數扇出導線236。該複 數控制導線235相互平行設置，該複數扇出導線236—端 連接該複數控制導線235，其另一端連接至該接腳焊墊區 231。該接腳焊墊區231係一用以對應焊接該半導體晶粒 22之矩形平面區域，其包括複數焊接點233，該複數焊接 φ 點233矩陣設置形成一焊接點矩陣232。連接至該接腳焊 墊區231之部份扇出導線236端部與該焊接點233對應電 連接’另一部份扇出導線236端部延伸至該接腳焊墊區 231内，其截面結構如圖6所示，且臨近該扇出導線236之 焊接點233之尚度大於該扇出導線236之尚度，設定該高 度差為Η。 [0025] 該異方性導電膜25係一將導電粒子均勻分佈於高品質樹 脂之高分子薄膜。當對該異方性導電膜25熱壓後，於平 行於膜厚方向上，使得該半導體晶粒22之焊墊222與該焊 096149369 表單編號 Α0101 第 7 頁/共 20 頁 1003302042-0 1364825 [0026] [0027] [0028] [0029] 1ΌΟ年.08月ί8日修正 ^基板23之焊接點233對應電連接，而於垂直於該異方性一 導電膜25厚度方气則彼此絕緣。其中取該導電釦、子之i，;、、.‘、 彺為D，其取值範圍藉由該異方性導電膜25之性能決定， 通系大約·為10微米左右，則該焊接點233與該扇出導線 . 236之高度大於該導電粒子之直徑1)。 在該電子封裝構造2中，該半導體晶粒22之焊墊222與該 焊接基板23之焊接點233相對應，因為部份扇出導線236 夾於該複數焊接點233之間，且其高度低於該焊接點233 之尚度，所以當將該半導體晶粒22封裝於該焊接基板23 時，該半導體晶粒22之焊墊222與該焊接基板23之焊接點 233有效導通，並不會出現該半導體晶粒22之焊墊222與 部份扇出導線236短路之情形。即便是因為操作失誤，使 得該半導體晶粒22之焊墊222與該扇出導線236有部份重 疊之情況，因為該焊接點233與該扇出導線236之高度差H 大於該導電粒子之直徑D，所以該焊接點233與該扇出導 線236仍然不會出現短路之可能。當然，該扇出導線236 還可以貫穿該接腳焊墊區231。該焊接基板23還可以為一 痛 軟性印刷電路板、硬性印刷電路板等。 综上，相較先前技術，採用該焊接基板23以及採用該焊 接基板23之電子封裝構造2，有效避免該焊墊222與該扇 出導線236間之短路，提高其可靠度。 當採用異方性導電膜25將該半導體晶粒22封裝於該焊接 基板23時，其封裝步驟如下： 步雜S1，於該半導體晶粒22表面形成焊塾矩陣221 ; 096149369 表單编號Α0101 第8頁/共20頁 1003302042-0 1364825 —_ 100年·08^Τ8日核正销问 _0]步驟S2 ’於該焊接基板23表面形成焊接點矩陣232及複數 产6亥焊接點233電連辞:\蠢杀筆终2:36;且使得該焊接點一 233之高度大於該扇出導線236之高度； [0031] #驟S3，於該焊接基板23表面設置焊接點矩陣232之區域 塗佈該異方性導電膜25 ; [0032] 步驟s4 ’對位該半導體晶粒22之焊墊矩陣221與該焊接基 板23之焊接點矩陣232 ’並藉由熱壓合設備熱壓合固化該 異方性導電膜25 ’使得該半導體晶粒22藉由該異方性導 φ 電膜25黏接固定於該焊接基板23。 [0033] 在採用該電子封裝構造2封裝該半導體晶粒22於該焊接基 板23時’採用異方性導電膜25直接封裝，有效解決因熱 力衝擊導致電子封裝可靠度低之問題。同時，因為該焊 接點233與該扇出導線236之高度差Η大於該導電粒子之直 徑D ’有效保證該焊墊222與該扇出導線236之彼此絕緣， 提高封裝過程之可靠度。[0007] [0009] [0009] High, ball_matrix, the pitch of the solder ball is further reduced, so as to reach 0. 5mm, even more, such as: the secret • must be guided by the offset of the solder ball ^, Affecting the reliability of electronic packaging. In order to solve the above technical bottleneck, the industry has a method of directly bonding a semiconductor device to be soldered to a soldered substrate by using an anisotropic conductive film (ACF), or a plurality of layers on the surface of the soldered substrate. The wiring (Lay out) and the fanout (Fanout) are used to change the layout layout to achieve the purpose of connecting the pads provided on the surface of the semiconductor device to the solder substrate. An electronic package structure for fixing a semiconductor die to a solder substrate according to the prior art is shown in FIG. 1. The electronic package structure 1 includes a semiconductor die 11, an anisotropic conductive film 13, and a thin film transistor substrate 15. . The thin film transistor substrate 15 is a solder substrate on a surface of which a soldering region ι51 is disposed. The semiconductor die 11 is bonded and fixed to the splicing region 151 by the anisotropic conductive film 1513. There is a solder 塾 1 Η matrix. A solder matrix 152 is disposed in the soldering region 151 of the thin film transistor 15 and a plurality of fan-out wires 153 outside the soldering region 151 are disposed. A portion of the fan-out wire 153 is electrically connected to the soldering point 152, and the cross-sectional height of the fan-out wire 153 is the same as the height of the cross-section of the soldering point 52. The cross-sectional structure is as shown in FIG. The anisotropic conductive film 13 is a resin doped with a certain density of conductive particles, which causes the pad 111 to be electrically insulated from the solder joint 152 in a direction parallel to the film thickness direction and insulated from each other in a direction perpendicular to the film thickness. 096149369 Form No. A0101 Page 4 / Total 20 Page 1003302042-0 [0011] [0011] 1364825 丨100 years · When the semiconductor die 11 is packaged on the thin film transistor substrate i 5, the following steps are as follows: [0012] First, an anisotropic conductive film 13 is coated in the soldering region 151 of the thin film transistor substrate 15; then, the solder pad of the semiconductor die u is soldered to the thin film transistor 15 a matrix of 152; finally, the anisotropic conductive film 13' is heat-cured by a hot pressing device, and the semiconductor die 11 is bonded to the soldered region 151 of the thin film transistor substrate 15 by the anisotropic conductive film 13 and The matrix of the pads 112 is electrically connected to the matrix of the solder joints 152. [0013] However, since the fan-out wire 153 on the surface of the thin film transistor substrate 15 and the soldering point 152 are consistent in the direction of the shank, when the matrix of the pad U1 is aligned with the matrix of the soldering point 152, such as an operation error Or the alignment accuracy is insufficient, which may cause the solder pad 111 and the fan-out wire 153 to overlap in space and short-circuit; when the 4-film transistor substrate 15 is used as the solder substrate for the packaging process, the fan-out wire is often used. The short circuit between the 53 and the pad U1 results in poor package and reduces package reliability. SUMMARY OF THE INVENTION [0014] In view of the above, it is necessary to provide a solder substrate with high package reliability. [〇〇15] In view of this, it is also necessary to provide an electronic package structure with high package reliability. _6] There is a ship, and it is necessary to provide an electronic packaging method with high reliability. A soldering substrate comprising a money fan-out wire and a plurality of solder joints, wherein at least - the fan-out wire is electrically connected to the solder joint, and the height of the solder joint is > "" Form No. A0101 Page 5 / Total 20苜 1003302042- 0 1364825 is greater than the height of the fan-out wire. [0018] An electronic sealing structure comprising a half-lead die and a solder substrate, the semiconductor die comprising a plurality of solder pads, the solder substrate comprising a plurality of fan-out wires and a plurality of solder joints, wherein the plurality of semiconductor grains The solder pad is electrically connected to the plurality of solder joints, and at least one of the lead wires is electrically connected to the solder joint, and the height of the solder joint is greater than the height of the fan-out conductor. [0019] - an electronic packaging method comprising: forming a plurality of pads on a surface of a semiconductor die; forming a plurality of solder joints on a surface of a solder substrate and a plurality of fan-out wires electrically connected to the solder joints, wherein the height of the solder joints Greater than the height of the fan-out wire; and electrically connecting the pads of the semiconductor die to the solder joints of the solder substrate. [0021] Compared with the prior art, the height of the soldering point is higher than the height of the fan-out wire on the surface of the soldering substrate, and the pad of the semiconductor die and the soldering substrate are avoided by the height difference. The package is defective due to short circuit between the solder joints, and the reliability of the electronic package structure using the solder substrate is effectively improved. Compared with the prior art, in the electronic package method, the height of the solder joint on the surface of the solder substrate is greater than the fan-out. The height of the wire is such that when the semiconductor die needs to be packaged on the solder substrate, it is ensured that the solder bump of the semiconductor die is insulated from the solder joint of the solder substrate surface. Even if the operation error or the alignment accuracy is not high enough, the solder pad and the fan-out wire partially overlap in space, and the short circuit between the solder pads and the fan-out wires is also prevented, resulting in poor electronic package and improved package reliability. [Embodiment] 096149369 Form No. 1010101 Page 6 / Total 20 Page 1003302042-0 1364825 ... Wide '... .. 100 years of August 18th, 俊正_Page [0022]. Please refer to Figure 3, the electronic body of the present invention The package constructs a preferred embodiment of the mound group. The electronic seal structure 2 includes a semiconductor die 22, a solder substrate 23, and an anisotropic conductive film 25. The semiconductor die 22 is bonded and fixed to the solder substrate 23 by the anisotropic conductive film 25. [0023] Referring again to FIG. 4, a schematic plan view of the semiconductor die 22 of the electronic package structure 2 shown in FIG. The semiconductor die 22 is a semiconductor device having a pad matrix 221 disposed on the surface thereof. The pad matrix 221 is formed by matrixing a plurality of pads 222. [0024] Referring to Figure 5, a schematic view of the solder substrate 23 of the electronic package structure 2 shown in Figure 3 is shown. The solder substrate 23 is a thin film transistor substrate having a plurality of wiring circuits (not shown) and a pad pad region 231. The wiring circuit includes a plurality of control wires 235 and a plurality of fan-out wires 236. The plurality of control wires 235 are disposed in parallel with each other, and the plurality of fan-out wires 236 are connected to the plurality of control wires 235, and the other ends thereof are connected to the pin pad regions 231. The pin pad region 231 is a rectangular planar region for soldering the semiconductor die 22, and includes a plurality of solder joints 233. The matrix of the plurality of solder bumps 233 is arranged to form a solder joint matrix 232. A portion of the fan-out wire 236 connected to the pin pad region 231 is electrically connected to the soldering point 233. The other portion of the fan-out wire 236 extends to the pin pad region 231. The structure is as shown in FIG. 6, and the degree of soldering point 233 adjacent to the fan-out wire 236 is greater than the degree of the fan-out wire 236, and the height difference is set to Η. [0025] The anisotropic conductive film 25 is a polymer film in which conductive particles are uniformly distributed in a high-quality resin. After the anisotropic conductive film 25 is hot pressed, in parallel with the film thickness direction, the pad 222 of the semiconductor die 22 and the solder 096149369 are numbered Α0101, page 7 of 20, 1003302042-0 1364825 [ [0029] [0029] [0029] The correction of the solder joints 233 of the substrate 23 corresponds to electrical connection, and the square gas perpendicular to the thickness of the anisotropic conductive film 25 is insulated from each other. Wherein the conductive buckle, the sub-i,;,,.', and 彺 are D, and the value range is determined by the performance of the anisotropic conductive film 25, and the pass is about 10 micrometers, and the solder joint is 233 and the fan-out wire. The height of 236 is greater than the diameter of the conductive particle 1). In the electronic package structure 2, the pad 222 of the semiconductor die 22 corresponds to the solder pad 233 of the solder substrate 23 because a portion of the fan-out wire 236 is sandwiched between the plurality of pads 233 and has a low height. At the solder joint 233, when the semiconductor die 22 is packaged on the solder substrate 23, the pad 222 of the semiconductor die 22 and the solder pad 233 of the solder substrate 23 are effectively turned on, and do not appear. The pad 222 of the semiconductor die 22 is shorted to a portion of the fan-out wire 236. Even if the operation is erroneous, the pad 222 of the semiconductor die 22 partially overlaps the fan-out wire 236 because the height difference H between the pad 233 and the fan-out wire 236 is greater than the diameter of the conductive particle. D, so the solder joint 233 and the fan-out wire 236 still have no possibility of short circuit. Of course, the fan-out wire 236 can also extend through the pin pad region 231. The solder substrate 23 may also be a pain sensitive printed circuit board, a rigid printed circuit board or the like. In summary, compared with the prior art, the solder substrate 23 and the electronic package structure 2 using the solder substrate 23 are used to effectively avoid short circuit between the pad 222 and the fan-out wire 236, thereby improving reliability. When the semiconductor die 22 is encapsulated on the solder substrate 23 by using the anisotropic conductive film 25, the packaging step is as follows: Step S1, a solder bump matrix 221 is formed on the surface of the semiconductor die 22; 096149369 Form No. Α0101 8 pages / total 20 pages 1003302042-0 1364825 — _ 100 years · 08 ^ Τ 8 days nuclear sales question _0] step S2 ' on the surface of the welding substrate 23 to form a solder joint matrix 232 and a plurality of 6 Hai welding points 233 electrical connection Word: \Stupid pen end 2:36; and the height of the solder joint 233 is greater than the height of the fan-out wire 236; [0031] #STEPS3, the area of the soldering substrate 23 is provided with a solder joint matrix 232 The anisotropic conductive film 25 is disposed; [0032] step s4' aligns the pad matrix 221 of the semiconductor die 22 with the pad matrix 232' of the solder substrate 23 and cures by thermocompression bonding by a thermocompression bonding apparatus The anisotropic conductive film 25' causes the semiconductor die 22 to be bonded and fixed to the solder substrate 23 by the anisotropic conductive film 25. [0033] When the semiconductor die 22 is packaged on the solder substrate 23 by the electronic package structure 2, it is directly packaged by the anisotropic conductive film 25, thereby effectively solving the problem of low reliability of the electronic package due to thermal shock. At the same time, because the height difference 该 between the solder joint 233 and the fan-out wire 236 is larger than the diameter D ′ of the conductive particles, the solder pad 222 and the fan-out wire 236 are insulated from each other, thereby improving the reliability of the packaging process.
[0034] 綜上所述，本發明霉已符合發明專利之要件，爰依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施例 ’本發明之範圍並不以上述實施例為限’舉凡熟習本案 技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内》 【圖式簡單說明】 [0035] 圖1係一種先前技術電子封裝構造之立體分解示意圖。 [0036] 圖2係圖1所示電子封裝構造之側面局部放大示意圖。 [0037] 圖3係本發明電子封裝構造一較佳實施方式之立體組裝示 096149369 表單編號 Α0101 第 9 買/兴 20 頁 1003302042-0 1364825 , , 100年.08月18日梭正替4吳頁 意圖。 [0038] 圖4係圖3所示電子封裝構造’乏"单晶粒乏平面示意圖 [0039] 圖5係圖3所示電子封裝構造之焊接基板之立體示意圖。 [0040] 圖6係圖3所示電子封裝構造之側面局部放大示意圖。 【主要元件符號說明】 [0041] 電子封裝構造：2 [0042] 焊接點矩陣：232 [0043] 半導體晶粒：22 [0044] 焊接點：233 [0045] 焊墊矩陣：221 [0046] 控制導線：235 [0047] 焊墊：222 [0048] 扇出導線：236 [0049] 焊接基板：23 [0050] 異方性導電膜：25 [0051] 接腳焊墊區：231[0034] In summary, the mold of the present invention has met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only the preferred embodiment of the present invention. The scope of the present invention is not limited to the above-described embodiments. Those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It is intended to be included in the following claims. [FIG. 1] FIG. 1 is a perspective exploded view of a prior art electronic package structure. 2 is a partially enlarged schematic side view showing the electronic package structure shown in FIG. 1. 3 is a three-dimensional assembly of a preferred embodiment of the electronic package structure of the present invention, 096149369, form number Α0101, 9th buy/hing 20 pages, 1003302042-0 1364825, , 100 years, August 18th, shuttle for 4 Wu page intention. 4 is a schematic view of the electronic package structure shown in FIG. 3; FIG. 5 is a perspective view of the solder substrate of the electronic package structure shown in FIG. 3. FIG. 6 is a partially enlarged schematic side view showing the electronic package structure shown in FIG. 3. [Main component symbol description] [0041] Electronic package construction: 2 [0042] Solder joint matrix: 232 [0043] Semiconductor die: 22 [0044] Solder joint: 233 [0045] Solder pad matrix: 221 [0046] Control wire : 235 [0047] Solder pad: 222 [0048] Fan-out wire: 236 [0049] Soldering substrate: 23 [0050] Anisotropic conductive film: 25 [0051] Pin pad area: 231
096149369 表單編號A0101 第10頁/共20頁 1003302042-0096149369 Form No. A0101 Page 10 of 20 1003302042-0